Commit d606ef3f authored by Baruch Siach's avatar Baruch Siach Committed by David S. Miller

phy/micrel: add ability to support 50MHz RMII clock on KZS8051RNL

Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup
routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL
PHY work with 50MHz RMII reference clock.

Cc: David J. Choi <david.choi@micrel.com>
Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 68aa3fd5
...@@ -19,13 +19,7 @@ ...@@ -19,13 +19,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/phy.h> #include <linux/phy.h>
#include <linux/micrel_phy.h>
#define PHY_ID_KSZ9021 0x00221611
#define PHY_ID_KS8737 0x00221720
#define PHY_ID_KS8041 0x00221510
#define PHY_ID_KS8051 0x00221550
/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
#define PHY_ID_KS8001 0x0022161A
/* general Interrupt control/status reg in vendor specific block. */ /* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS 0x1B #define MII_KSZPHY_INTCS 0x1B
...@@ -46,6 +40,7 @@ ...@@ -46,6 +40,7 @@
#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9) #define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14) #define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14) #define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
static int kszphy_ack_interrupt(struct phy_device *phydev) static int kszphy_ack_interrupt(struct phy_device *phydev)
{ {
...@@ -106,6 +101,19 @@ static int kszphy_config_init(struct phy_device *phydev) ...@@ -106,6 +101,19 @@ static int kszphy_config_init(struct phy_device *phydev)
return 0; return 0;
} }
static int ks8051_config_init(struct phy_device *phydev)
{
int regval;
if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
regval = phy_read(phydev, MII_KSZPHY_CTRL);
regval |= KSZ8051_RMII_50MHZ_CLK;
phy_write(phydev, MII_KSZPHY_CTRL, regval);
}
return 0;
}
static struct phy_driver ks8737_driver = { static struct phy_driver ks8737_driver = {
.phy_id = PHY_ID_KS8737, .phy_id = PHY_ID_KS8737,
.phy_id_mask = 0x00fffff0, .phy_id_mask = 0x00fffff0,
...@@ -142,7 +150,7 @@ static struct phy_driver ks8051_driver = { ...@@ -142,7 +150,7 @@ static struct phy_driver ks8051_driver = {
.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
| SUPPORTED_Asym_Pause), | SUPPORTED_Asym_Pause),
.flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
.config_init = kszphy_config_init, .config_init = ks8051_config_init,
.config_aneg = genphy_config_aneg, .config_aneg = genphy_config_aneg,
.read_status = genphy_read_status, .read_status = genphy_read_status,
.ack_interrupt = kszphy_ack_interrupt, .ack_interrupt = kszphy_ack_interrupt,
......
#ifndef _MICREL_PHY_H
#define _MICREL_PHY_H
#define MICREL_PHY_ID_MASK 0x00fffff0
#define PHY_ID_KSZ9021 0x00221611
#define PHY_ID_KS8737 0x00221720
#define PHY_ID_KS8041 0x00221510
#define PHY_ID_KS8051 0x00221550
/* both for ks8001 Rev. A/B, and for ks8721 Rev 3. */
#define PHY_ID_KS8001 0x0022161A
/* struct phy_device dev_flags definitions */
#define MICREL_PHY_50MHZ_CLK 0x00000001
#endif /* _MICREL_PHY_H */
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