Commit d99f1387 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: Add DCN3 HWSEQ

Add HW sequence programing for DCN3
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5baebf61
No related merge requests found
......@@ -893,6 +893,9 @@ struct mcif_buf_params {
unsigned int chroma_pitch;
unsigned int warmup_pitch;
unsigned int swlock;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
unsigned int p_vmid;
#endif
};
......
......@@ -87,6 +87,13 @@ struct dc_writeback_info {
int dwb_pipe_inst;
struct dc_dwb_params dwb_params;
struct mcif_buf_params mcif_buf_params;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct mcif_warmup_params mcif_warmup_params;
/* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
struct dc_plane_state *writeback_source_plane;
/* source MPCC instance. for use by internally by dc */
int mpcc_inst;
#endif
};
struct dc_writeback_update {
......@@ -200,6 +207,10 @@ struct dc_stream_state {
/* writeback */
unsigned int num_wb_info;
struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
const struct dc_transfer_func *func_shaper;
const struct dc_3dlut *lut3d_func;
#endif
/* Computed state bits */
bool mode_changed : 1;
......@@ -251,6 +262,10 @@ struct dc_stream_update {
struct dc_writeback_update *wb_update;
struct dc_dsc_config *dsc_config;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct dc_transfer_func *func_shaper;
struct dc_3dlut *lut3d_func;
#endif
};
bool dc_is_stream_unchanged(
......
......@@ -78,6 +78,24 @@
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \
SRII(PIXEL_RATE_CNTL, blk, 0), \
SRII(PIXEL_RATE_CNTL, blk, 1),\
SRII(PIXEL_RATE_CNTL, blk, 2),\
SRII(PIXEL_RATE_CNTL, blk, 3), \
SRII(PIXEL_RATE_CNTL, blk, 4), \
SRII(PIXEL_RATE_CNTL, blk, 5)
#define HWSEQ_PHYPLL_REG_LIST_3(blk) \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
#endif
#define HWSEQ_DCE11_REG_LIST_BASE() \
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
SR(DCFEV_CLOCK_CONTROL), \
......@@ -200,6 +218,28 @@
SR(VGA_TEST_CONTROL), \
SR(DC_IP_REQUEST_CNTL)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN30_REG_LIST()\
HWSEQ_DCN2_REG_LIST(),\
HWSEQ_DCN_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
HWSEQ_PHYPLL_REG_LIST_3(OTG), \
SR(MICROSECOND_TIME_BASE_DIV), \
SR(MILLISECOND_TIME_BASE_DIV), \
SR(DISPCLK_FREQ_CHANGE_CNTL), \
SR(RBBMIF_TIMEOUT_DIS), \
SR(RBBMIF_TIMEOUT_DIS_2), \
SR(DCHUBBUB_CRC_CTRL), \
SR(DPP_TOP0_DPP_CRC_CTRL), \
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
SR(MPC_CRC_CTRL), \
SR(MPC_CRC_RESULT_GB), \
SR(MPC_CRC_RESULT_C), \
SR(MPC_CRC_RESULT_AR), \
SR(AZALIA_AUDIO_DTO), \
SR(AZALIA_CONTROLLER_CLOCK_GATING)
#endif
#define HWSEQ_DCN2_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
......@@ -546,6 +586,12 @@ struct dce_hwseq_registers {
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
#endif
#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
......
......@@ -1453,6 +1453,11 @@ void dcn10_init_hw(struct dc *dc)
if (dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
if (dc->clk_mgr->funcs->set_hard_max_memclk)
dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
#endif
}
void dcn10_reset_hw_ctx_wrap(
......
......@@ -609,6 +609,31 @@ void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
pipe_ctx->pipe_idx);
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
int opp_cnt)
{
bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing);
int flow_ctrl_cnt;
if (opp_cnt == 2)
hblank_halved = true;
flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable -
stream->timing.h_border_left -
stream->timing.h_border_right;
if (hblank_halved)
flow_ctrl_cnt /= 2;
/* ODM combine 4:1 case */
if (opp_cnt == 4)
flow_ctrl_cnt /= 2;
return flow_ctrl_cnt;
}
#endif
enum dc_status dcn20_enable_stream_timing(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
......@@ -622,6 +647,15 @@ enum dc_status dcn20_enable_stream_timing(
int opp_cnt = 1;
int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
bool interlace = stream->timing.flags.INTERLACE;
int i;
struct mpc_dwb_flow_control flow_control;
struct mpc *mpc = dc->res_pool->mpc;
bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing));
#endif
/* by upper caller loop, pipe0 is parent pipe and be called first.
* back end is set up by for pipe0. Other children pipe share back end
* with pipe 0. No program is needed.
......@@ -668,6 +702,21 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream->signal,
true);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1;
flow_control.flow_ctrl_mode = 0;
flow_control.flow_ctrl_cnt0 = 0x80;
flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt);
if (mpc->funcs->set_out_rate_control) {
for (i = 0; i < opp_cnt; ++i) {
mpc->funcs->set_out_rate_control(
mpc, opp_inst[i],
true,
rate_control_2x_pclk,
&flow_control);
}
}
#endif
for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
odm_pipe->stream_res.opp,
......@@ -1414,6 +1463,37 @@ static void dcn20_update_dchubp_dpp(
if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
|| pipe_ctx->stream->update_flags.bits.gamut_remap
|| pipe_ctx->stream->update_flags.bits.out_csc) {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
if (mpc->funcs->set_gamut_remap) {
int i;
int mpcc_id = hubp->inst;
struct mpc_grph_gamut_adjustment adjust;
bool enable_remap_dpp = false;
memset(&adjust, 0, sizeof(adjust));
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
/* save the enablement of gamut remap for dpp*/
enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap;
/*force bypass gamut remap for dpp/cm*/
pipe_ctx->stream->gamut_remap_matrix.enable_remap = false;
dc->hwss.program_gamut_remap(pipe_ctx);
/*restore gamut remap flag for the top plane and use this remap into mpc*/
if (pipe_ctx->top_pipe == NULL)
pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp;
else
pipe_ctx->stream->gamut_remap_matrix.enable_remap = false;
if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
adjust.temperature_matrix[i] =
pipe_ctx->stream->gamut_remap_matrix.matrix[i];
}
mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust);
} else
#endif
/* dpp/cm gamut remap*/
dc->hwss.program_gamut_remap(pipe_ctx);
......@@ -2173,6 +2253,11 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
blnd_cfg.bottom_inside_gain = 0x1f000;
blnd_cfg.bottom_outside_gain = 0x1f000;
blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (pipe_ctx->plane_state->format
== SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA)
blnd_cfg.pre_multiplied_alpha = false;
#endif
/*
* TODO: remove hack
......
This diff is collapsed.
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_HWSS_DCN30_H__
#define __DC_HWSS_DCN30_H__
#include "hw_sequencer_private.h"
struct dc;
void dcn30_init_hw(struct dc *dc);
void dcn30_program_all_writeback_pipes_in_tree(
struct dc *dc,
const struct dc_stream_state *stream,
struct dc_state *context);
void dcn30_update_writeback(
struct dc *dc,
struct dc_writeback_info *wb_info,
struct dc_state *context);
void dcn30_enable_writeback(
struct dc *dc,
struct dc_writeback_info *wb_info,
struct dc_state *context);
void dcn30_disable_writeback(
struct dc *dc,
unsigned int dwb_pipe_inst);
bool dcn30_mmhubbub_warmup(
struct dc *dc,
unsigned int num_dwb,
struct dc_writeback_info *wb_info);
bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
bool dcn30_set_input_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
bool dcn30_set_output_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream);
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
#endif /* __DC_HWSS_DCN30_H__ */
......@@ -217,6 +217,10 @@ struct resource_pool {
struct dmcu *dmcu;
struct dmub_psr *psr;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
struct abm *multiple_abms[MAX_PIPES];
#endif
const struct resource_funcs *funcs;
const struct resource_caps *res_cap;
......
......@@ -75,6 +75,11 @@ struct mcif_wb {
struct mcif_wb_funcs {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*warmup_mcif)(
struct mcif_wb *mcif_wb,
struct mcif_warmup_params *params);
#endif
void (*enable_mcif)(struct mcif_wb *mcif_wb);
void (*disable_mcif)(struct mcif_wb *mcif_wb);
......
......@@ -205,6 +205,10 @@ struct hw_sequencer_funcs {
void (*set_pipe)(struct pipe_ctx *pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
#endif
};
......
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