Commit dc0aea38 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

ARM: dts: sun6i: Sort pinmux setting nodes

The pinmux setting nodes for the A31 were added out of alphabetical
order. Sort them.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent e5cd7ff7
...@@ -434,13 +434,48 @@ pio: pinctrl@01c20800 { ...@@ -434,13 +434,48 @@ pio: pinctrl@01c20800 {
#interrupt-cells = <3>; #interrupt-cells = <3>;
#gpio-cells = <3>; #gpio-cells = <3>;
uart0_pins_a: uart0@0 { gmac_pins_gmii_a: gmac_gmii@0 {
allwinner,pins = "PH20", "PH21"; allwinner,pins = "PA0", "PA1", "PA2", "PA3",
allwinner,function = "uart0"; "PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA15",
"PA16", "PA17", "PA18", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in GMII mode run at 125MHz and
* might need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_mii_a: gmac_mii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA26", "PA27";
allwinner,function = "gmac";
allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
}; };
gmac_pins_rgmii_a: gmac_rgmii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0@0 { i2c0_pins_a: i2c0@0 {
allwinner,pins = "PH14", "PH15"; allwinner,pins = "PH14", "PH15";
allwinner,function = "i2c0"; allwinner,function = "i2c0";
...@@ -506,47 +541,12 @@ mmc3_8bit_emmc_pins: mmc3@1 { ...@@ -506,47 +541,12 @@ mmc3_8bit_emmc_pins: mmc3@1 {
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
}; };
gmac_pins_mii_a: gmac_mii@0 { uart0_pins_a: uart0@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3", allwinner,pins = "PH20", "PH21";
"PA8", "PA9", "PA11", allwinner,function = "uart0";
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA26", "PA27";
allwinner,function = "gmac";
allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
}; };
gmac_pins_gmii_a: gmac_gmii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA15",
"PA16", "PA17", "PA18", "PA19",
"PA20", "PA21", "PA22", "PA23",
"PA24", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in GMII mode run at 125MHz and
* might need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_rgmii_a: gmac_rgmii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA19",
"PA20", "PA25", "PA26", "PA27";
allwinner,function = "gmac";
/*
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
}; };
timer@01c20c00 { timer@01c20c00 {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment