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Commit dce5ee27 authored by David S. Miller's avatar David S. Miller
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Merge nuts.ninka.net:/home/davem/src/BK/sparcwork-2.5 

into nuts.ninka.net:/home/davem/src/BK/sparc-2.5
parents 5960eccb 1d02c2c0
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Showing with 11653 additions and 3725 deletions
Documentation/magic-number.txt
View file @ dce5ee27
......@@ -51,6 +51,13 @@ kernel before 2.6.x yet.
<pasky@ucw.cz>
03 Nov 2002
Updated the magic table to Linux 2.5.74.
Fabian Frederick
<ffrederick@users.sourceforge.net>
09 Jul 2003
Magic Name Number Structure File
===========================================================================
PG_MAGIC 'P' pg_{read,write}_hdr include/linux/pg.h
......@@ -62,10 +69,12 @@ AURORA_MAGIC 0x0A18 Aurora_port drivers/sbus/char/aurora.h
HDLC_MAGIC 0x239e n_hdlc drivers/char/n_hdlc.c
APM_BIOS_MAGIC 0x4101 apm_user arch/i386/kernel/apm.c
CYCLADES_MAGIC 0x4359 cyclades_port include/linux/cyclades.h
DB_MAGIC 0x4442 fc_info drivers/net/iph5526_novram.c
DL_MAGIC 0x444d fc_info drivers/net/iph5526_novram.c
FASYNC_MAGIC 0x4601 fasync_struct include/linux/fs.h
FF_MAGIC 0x4646 fc_info drivers/net/iph5526_novram.c
ISICOM_MAGIC 0x4d54 isi_port include/linux/isicom.h
PTY_MAGIC 0x5001 (none at the moment)
drivers/char/pty.c
PTY_MAGIC 0x5001 drivers/char/pty.c
PPP_MAGIC 0x5002 ppp include/linux/if_pppvar.h
SERIAL_MAGIC 0x5301 async_struct include/linux/serial.h
SSTATE_MAGIC 0x5302 serial_state include/linux/serial.h
......@@ -81,9 +90,9 @@ TTY_DRIVER_MAGIC 0x5402 tty_driver include/linux/tty_driver.h
MGSLPC_MAGIC 0x5402 mgslpc_info drivers/char/pcmcia/synclink_cs.c
TTY_LDISC_MAGIC 0x5403 tty_ldisc include/linux/tty_ldisc.h
USB_SERIAL_MAGIC 0x6702 usb_serial drivers/usb/serial/usb-serial.h
FULL_DUPLEX_MAGIC 0x6969 drivers/net/tulip/de2104x.c
USB_BLUETOOTH_MAGIC 0x6d02 usb_bluetooth drivers/usb/class/bluetty.c
RFCOMM_TTY_MAGIC 0x6d02 (note at the moment)
net/bluetooth/rfcomm/tty.c
RFCOMM_TTY_MAGIC 0x6d02 net/bluetooth/rfcomm/tty.c
USB_SERIAL_PORT_MAGIC 0x7301 usb_serial_port drivers/usb/serial/usb-serial.h
CG_MAGIC 0x00090255 ufs_cylinder_group include/linux/ufs_fs.h
A2232_MAGIC 0x000a2232 gs_port drivers/char/ser_a2232.h
......@@ -91,6 +100,7 @@ SOLARIS_SOCKET_MAGIC 0x000ADDED sol_socket_struct arch/sparc64/solaris/socksys
RPORT_MAGIC 0x00525001 r_port drivers/char/rocket_int.h
LSEMAGIC 0x05091998 lse drivers/fc4/fc.c
GDTIOCTL_MAGIC 0x06030f07 gdth_iowr_str drivers/scsi/gdth_ioctl.h
RIEBL_MAGIC 0x09051990 drivers/net/atarilance.c
RIO_MAGIC 0x12345678 gs_port drivers/char/rio/rio_linux.c
SX_MAGIC 0x12345678 gs_port drivers/char/sx.h
NBD_REQUEST_MAGIC 0x12560953 nbd_request include/linux/nbd.h
......@@ -120,6 +130,7 @@ SAVEKMSG_MAGIC1 0x53415645 savekmsg arch/*/amiga/config.c
GDA_MAGIC 0x58464552 gda include/asm-mips64/sn/gda.h
RED_MAGIC1 0x5a2cf071 (any) mm/slab.c
STL_PORTMAGIC 0x5a7182c9 stlport include/linux/stallion.h
EEPROM_MAGIC_VALUE 0X5ab478d2 lanai_dev drivers/atm/lanai.c
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state include/linux/hdlcdrv.h
EPCA_MAGIC 0x5c6df104 channel include/linux/epca.h
PCXX_MAGIC 0x5c6df104 channel drivers/char/pcxx.h
......@@ -127,9 +138,11 @@ KV_MAGIC 0x5f4b565f kernel_vars_s include/asm-mips64/sn/klkern
I810_STATE_MAGIC 0x63657373 i810_state sound/oss/i810_audio.c
TRIDENT_STATE_MAGIC 0x63657373 trient_state sound/oss/trident.c
M3_CARD_MAGIC 0x646e6f50 m3_card sound/oss/maestro3.c
FW_HEADER_MAGIC 0x65726F66 fw_header drivers/atm/fore200e.h
SLOT_MAGIC 0x67267321 slot drivers/hotplug/cpqphp.h
SLOT_MAGIC 0x67267322 slot drivers/hotplug/acpiphp.h
LO_MAGIC 0x68797548 nbd_device include/linux/nbd.h
OPROFILE_MAGIC 0x6f70726f super_block drivers/oprofile/oprofilefs.h
M3_STATE_MAGIC 0x734d724d m3_state sound/oss/maestro3.c
STL_PANELMAGIC 0x7ef621a1 stlpanel include/linux/stallion.h
VMALLOC_MAGIC 0x87654320 snd_alloc_track sound/core/memory.c
......@@ -137,11 +150,15 @@ KMALLOC_MAGIC 0x87654321 snd_alloc_track sound/core/memory.c
PWC_MAGIC 0x89DC10AB pwc_device drivers/usb/media/pwc.h
NBD_REPLY_MAGIC 0x96744668 nbd_reply include/linux/nbd.h
STL_BOARDMAGIC 0xa2267f52 stlbrd include/linux/stallion.h
ENI155_MAGIC 0xa54b872d midway_eprom drivers/atm/eni.h
SCI_MAGIC 0xbabeface gs_port drivers/char/sh-sci.h
CODA_MAGIC 0xC0DAC0DA coda_file_info include/linux/coda_fs_i.h
DPMEM_MAGIC 0xc0ffee11 gdt_pci_sram drivers/scsi/gdth.h
STLI_PORTMAGIC 0xe671c7a1 stliport include/linux/istallion.h
YAM_MAGIC 0xF10A7654 yam_port drivers/net/hamradio/yam.c
CCB_MAGIC 0xf2691ad2 ccb drivers/scsi/ncr53c8xx.c
QUEUE_MAGIC_FREE 0xf7e1c9a3 queue_entry drivers/scsi/arm/queue.c
QUEUE_MAGIC_USED 0xf7e1cc33 queue_entry drivers/scsi/arm/queue.c
HTB_CMAGIC 0xFEFAFEF1 htb_class net/sched/sch_htb.c
NMI_MAGIC 0x48414d4d455201 nmi_s include/asm-mips64/sn/nmi.h
......
Documentation/pnp.txt
View file @ dce5ee27
......@@ -22,7 +22,7 @@ user interface is integrated into driverfs.
In addition to the standard driverfs file the following are created in each
device's directory:
id - displays a list of support EISA IDs
possible - displays possible resource configurations
options - displays possible resource configurations
resources - displays currently allocated resources and allows resource changes
-activating a device
......@@ -60,7 +60,7 @@ DISABLED
- Notice the string "DISABLED". THis means the device is not active.
3.) check the device's possible configurations (optional)
# cat possible
# cat options
Dependent: 01 - Priority acceptable
port 0x3f0-0x3f0, align 0x7, size 0x6, 16-bit address decoding
port 0x3f7-0x3f7, align 0x0, size 0x1, 16-bit address decoding
......
Makefile
View file @ dce5ee27
......@@ -781,7 +781,8 @@ rpm: clean spec
tar -cvz $(RCS_TAR_IGNORE) -f $(KERNELPATH).tar.gz $(KERNELPATH)/. ; \
rm $(KERNELPATH) ; \
cd $(TOPDIR) ; \
$(CONFIG_SHELL) $(srctree)/scripts/mkversion > .version ; \
$(CONFIG_SHELL) $(srctree)/scripts/mkversion > .tmp_version ; \
mv -f .tmp_version .version; \
$(RPM) -ta $(TOPDIR)/../$(KERNELPATH).tar.gz ; \
rm $(TOPDIR)/../$(KERNELPATH).tar.gz
......
arch/alpha/kernel/irq.c
View file @ dce5ee27
......@@ -601,7 +601,7 @@ handle_irq(int irq, struct pt_regs * regs)
if ((unsigned) irq > ACTUAL_NR_IRQS && illegal_count < MAX_ILLEGAL_IRQS ) {
irq_err_count++;
illegal_count++;
printk(KERN_CRIT "device_interrupt: illegal interrupt %d\n",
printk(KERN_CRIT "device_interrupt: invalid interrupt %d\n",
irq);
return;
}
......
arch/i386/kernel/cpu/mtrr/cyrix.c
View file @ dce5ee27
......@@ -330,16 +330,16 @@ cyrix_arr_init(void)
set_mtrr_done(&ctxt); /* flush cache and disable MAPEN */
if (ccrc[5])
printk("mtrr: ARR usage was not enabled, enabled manually\n");
printk(KERN_INFO "mtrr: ARR usage was not enabled, enabled manually\n");
if (ccrc[3])
printk("mtrr: ARR3 cannot be changed\n");
printk(KERN_INFO "mtrr: ARR3 cannot be changed\n");
/*
if ( ccrc[1] & 0x80) printk ("mtrr: SMM memory access through ARR3 disabled\n");
if ( ccrc[1] & 0x04) printk ("mtrr: SMM memory access disabled\n");
if ( ccrc[1] & 0x02) printk ("mtrr: SMM mode disabled\n");
*/
if (ccrc[6])
printk("mtrr: ARR3 was write protected, unprotected\n");
printk(KERN_INFO "mtrr: ARR3 was write protected, unprotected\n");
}
static struct mtrr_ops cyrix_mtrr_ops = {
......
arch/i386/kernel/cpu/mtrr/main.c
View file @ dce5ee27
......@@ -64,7 +64,7 @@ __initdata char *mtrr_if_name[] = {
static void set_mtrr(unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type);
static unsigned int arr3_protected;
extern int arr3_protected;
void set_mtrr_ops(struct mtrr_ops * ops)
{
......@@ -75,20 +75,22 @@ void set_mtrr_ops(struct mtrr_ops * ops)
/* Returns non-zero if we have the write-combining memory type */
static int have_wrcomb(void)
{
struct pci_dev *dev = NULL;
/* WTF is this?
* Someone, please shoot me.
*/
struct pci_dev *dev;
if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
/* ServerWorks LE chipsets have problems with write-combining
Don't allow it and leave room for other chipsets to be tagged */
if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
if ((dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
(dev->device == PCI_DEVICE_ID_SERVERWORKS_LE)) {
printk(KERN_INFO
"mtrr: Serverworks LE detected. Write-combining disabled.\n");
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
return 0;
}
/* Intel 450NX errata # 23. Non ascending cachline evictions to
write combining memory may resulting in data corruption */
if (dev->vendor == PCI_VENDOR_ID_INTEL &&
dev->device == PCI_DEVICE_ID_INTEL_82451NX)
{
printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
return 0;
}
}
......@@ -121,7 +123,7 @@ static void init_table(void)
max = num_var_ranges;
if ((usage_table = kmalloc(max * sizeof *usage_table, GFP_KERNEL))
== NULL) {
printk("mtrr: could not allocate\n");
printk(KERN_ERR "mtrr: could not allocate\n");
return;
}
for (i = 0; i < max; i++)
......@@ -310,7 +312,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
return error;
if (type >= MTRR_NUM_TYPES) {
printk("mtrr: type: %u illegal\n", type);
printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
return -EINVAL;
}
......@@ -322,7 +324,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
}
if (base & size_or_mask || size & size_or_mask) {
printk("mtrr: base or size exceeds the MTRR width\n");
printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
return -EINVAL;
}
......@@ -348,7 +350,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
if (ltype != type) {
if (type == MTRR_TYPE_UNCACHABLE)
continue;
printk ("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
base, size, attrib_to_str(ltype),
attrib_to_str(type));
goto out;
......@@ -364,7 +366,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
set_mtrr(i, base, size, type);
usage_table[i] = 1;
} else
printk("mtrr: no more MTRRs available\n");
printk(KERN_INFO "mtrr: no more MTRRs available\n");
error = i;
out:
up(&main_lock);
......@@ -412,8 +414,8 @@ mtrr_add(unsigned long base, unsigned long size, unsigned int type,
char increment)
{
if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
printk("mtrr: size and base must be multiples of 4 kiB\n");
printk("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
printk(KERN_WARNING "mtrr: size and base must be multiples of 4 kiB\n");
printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
return -EINVAL;
}
return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
......@@ -458,28 +460,28 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
}
}
if (reg < 0) {
printk("mtrr: no MTRR for %lx000,%lx000 found\n", base,
printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
size);
goto out;
}
}
if (reg >= max) {
printk("mtrr: register: %d too big\n", reg);
printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
goto out;
}
if (is_cpu(CYRIX) && !use_intel()) {
if ((reg == 3) && arr3_protected) {
printk("mtrr: ARR3 cannot be changed\n");
printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n");
goto out;
}
}
mtrr_if->get(reg, &lbase, &lsize, &ltype);
if (lsize < 1) {
printk("mtrr: MTRR %d not used\n", reg);
printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
goto out;
}
if (usage_table[reg] < 1) {
printk("mtrr: reg: %d has count=0\n", reg);
printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
goto out;
}
if (--usage_table[reg] < 1)
......@@ -508,8 +510,8 @@ int
mtrr_del(int reg, unsigned long base, unsigned long size)
{
if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
printk("mtrr: size and base must be multiples of 4 kiB\n");
printk("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
printk(KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
return -EINVAL;
}
return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
......@@ -677,7 +679,7 @@ static int __init mtrr_init(void)
break;
}
}
printk("mtrr: v%s\n",MTRR_VERSION);
printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);
if (mtrr_if) {
set_num_var_ranges();
......
arch/i386/pci/visws.c
View file @ dce5ee27
......@@ -17,7 +17,7 @@
int broken_hp_bios_irq9;
extern struct pci_ops pci_direct_conf1;
extern struct pci_raw_ops pci_direct_conf1;
static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
......@@ -101,8 +101,9 @@ static int __init pcibios_init(void)
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
pci_scan_bus(pci_bus0, &pci_direct_conf1, NULL);
pci_scan_bus(pci_bus1, &pci_direct_conf1, NULL);
raw_pci_ops = &pci_direct_conf1;
pci_scan_bus(pci_bus0, &pci_root_ops, NULL);
pci_scan_bus(pci_bus1, &pci_root_ops, NULL);
pci_fixup_irqs(visws_swizzle, visws_map_irq);
pcibios_resource_survey();
return 0;
......
arch/ia64/kernel/module.c
View file @ dce5ee27
......@@ -164,7 +164,7 @@ static int
apply_imm64 (struct module *mod, struct insn *insn, uint64_t val)
{
if (slot(insn) != 2) {
printk(KERN_ERR "%s: illegal slot number %d for IMM64\n",
printk(KERN_ERR "%s: invalid slot number %d for IMM64\n",
mod->name, slot(insn));
return 0;
}
......@@ -176,7 +176,7 @@ static int
apply_imm60 (struct module *mod, struct insn *insn, uint64_t val)
{
if (slot(insn) != 2) {
printk(KERN_ERR "%s: illegal slot number %d for IMM60\n",
printk(KERN_ERR "%s: invalid slot number %d for IMM60\n",
mod->name, slot(insn));
return 0;
}
......
arch/m68k/apollo/dn_ints.c
View file @ dce5ee27
......@@ -46,7 +46,7 @@ void dn_init_IRQ(void) {
int dn_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id) {
if((irq<0) || (irq>15)) {
printk("Trying to request illegal IRQ\n");
printk("Trying to request invalid IRQ\n");
return -ENXIO;
}
......@@ -72,7 +72,7 @@ int dn_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct
void dn_free_irq(unsigned int irq, void *dev_id) {
if((irq<0) || (irq>15)) {
printk("Trying to free illegal IRQ\n");
printk("Trying to free invalid IRQ\n");
return ;
}
......
arch/m68k/q40/q40ints.c
View file @ dce5ee27
......@@ -171,7 +171,7 @@ void q40_free_irq(unsigned int irq, void *dev_id)
{
case 1: case 2: case 8: case 9:
case 12: case 13:
printk("%s: ISA IRQ %d from %x illegal\n", __FUNCTION__, irq, (unsigned)dev_id);
printk("%s: ISA IRQ %d from %x invalid\n", __FUNCTION__, irq, (unsigned)dev_id);
return;
case 11: irq=10;
default:
......
arch/mips/mm/fault.c
View file @ dce5ee27
......@@ -162,7 +162,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
tsk->thread.cp0_badvaddr = address;
tsk->thread.error_code = write;
#if 0
printk("do_page_fault() #2: sending SIGSEGV to %s for illegal %s\n"
printk("do_page_fault() #2: sending SIGSEGV to %s for invalid %s\n"
"%08lx (epc == %08lx, ra == %08lx)\n",
tsk->comm,
write ? "write access to" : "read access from",
......
arch/mips/ramdisk/Makefile
View file @ dce5ee27
......@@ -2,7 +2,7 @@
# Makefile for a ramdisk image
#
O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)
O_FORMAT = $(shell $(OBJDUMP) -i | head -n 2 | grep elf32)
img = $(CONFIG_EMBEDDED_RAMDISK_IMAGE)
ramdisk.o: $(subst ",,$(img)) ld.script
echo "O_FORMAT: " $(O_FORMAT)
......
arch/ppc64/boot/Makefile
View file @ dce5ee27
......@@ -118,7 +118,7 @@ $(obj)/imagesize.c: vmlinux
ls -l vmlinux | \
awk '{printf "/* generated -- do not edit! */\n" \
"unsigned long vmlinux_filesize = %d;\n", $$5}' > $(obj)/imagesize.c
$(CROSS_COMPILE)nm -n vmlinux | tail -1 | \
$(CROSS_COMPILE)nm -n vmlinux | tail -n 1 | \
awk '{printf "unsigned long vmlinux_memsize = 0x%s;\n", substr($$1,8)}' \
>> $(obj)/imagesize.c
......
arch/sparc/kernel/process.c
View file @ dce5ee27
......@@ -590,16 +590,20 @@ int dump_fpu (struct pt_regs * regs, elf_fpregset_t * fpregs)
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
if (regs != NULL) {
regs->psr &= ~(PSR_EF);
current->flags &= ~(PF_USEDFPU);
}
}
#else
if (current == last_task_used_math) {
put_psr(get_psr() | PSR_EF);
fpsave(&current->thread.float_regs[0], &current->thread.fsr,
&current->thread.fpqueue[0], &current->thread.fpqdepth);
last_task_used_math = 0;
if (regs != NULL) {
regs->psr &= ~(PSR_EF);
last_task_used_math = 0;
}
}
#endif
memcpy(&fpregs->pr_fr.pr_regs[0],
......
arch/v850/Kconfig
View file @ dce5ee27
......@@ -48,20 +48,24 @@ menu "Processor type and features"
choice
prompt "Platform"
default GDB
config V850E_SIM
bool "GDB"
config RTE_CB_MA1
bool "RTE-V850E/MA1-CB"
config RTE_CB_NB85E
bool "RTE-V850E/NB85E-CB"
config V850E_SIM
bool "GDB"
config RTE_CB_ME2
bool "RTE-V850E/ME2-CB"
config V850E_AS85EP1
bool "AS85EP1"
config V850E2_SIM85E2C
bool "sim85e2c"
config V850E2_SIM85E2S
bool "sim85e2s"
config V850E2_FPGA85E2C
bool "NA85E2C-FPGA"
config V850E2_ANNA
bool "Anna"
config V850E_AS85EP1
bool "AS85EP1"
endchoice
......@@ -78,41 +82,32 @@ menu "Processor type and features"
bool
depends RTE_CB_MA1
default y
# Similarly for the RTE-V850E/MA1-CB - V850E/TEG
# Similarly for the RTE-V850E/NB85E-CB - V850E/TEG
config V850E_TEG
bool
depends RTE_CB_NB85E
default y
# NB85E processor core
config V850E_NB85E
# ... and the RTE-V850E/ME2-CB - V850E/ME2
config V850E_ME2
bool
depends V850E_MA1 || V850E_TEG
depends RTE_CB_ME2
default y
config V850E_MA1_HIGHRES_TIMER
bool "High resolution timer support"
depends V850E_MA1
#### sim85e2-specific config
#### V850E2 processor-specific config
# V850E2 processors
config V850E2
config V850E2_SIM85E2
bool
depends V850E2_SIM85E2C || V850E2_FPGA85E2C || V850E2_ANNA
depends V850E2_SIM85E2C || V850E2_SIM85E2S
default y
# Processors based on the NA85E2A core
config V850E2_NA85E2A
bool
depends V850E2_ANNA
default y
# Processors based on the NA85E2C core
config V850E2_NA85E2C
#### V850E2 processor-specific config
# V850E2 processors
config V850E2
bool
depends V850E2_SIM85E2C || V850E2_FPGA85E2C
depends V850E2_SIM85E2 || V850E2_FPGA85E2C || V850E2_ANNA
default y
......@@ -121,7 +116,7 @@ menu "Processor type and features"
# Boards in the RTE-x-CB series
config RTE_CB
bool
depends RTE_CB_MA1 || RTE_CB_NB85E
depends RTE_CB_MA1 || RTE_CB_NB85E || RTE_CB_ME2
default y
config RTE_CB_MULTI
......@@ -129,7 +124,7 @@ menu "Processor type and features"
# RTE_CB_NB85E can either have multi ROM support or not, but
# other platforms (currently only RTE_CB_MA1) require it.
prompt "Multi monitor ROM support" if RTE_CB_NB85E
depends RTE_CB
depends RTE_CB_MA1 || RTE_CB_NB85E
default y
config RTE_CB_MULTI_DBTRAP
......@@ -156,14 +151,42 @@ menu "Processor type and features"
# The only PCI bus we support is on the RTE-MOTHER-A board
config PCI
bool
default y if RTE_MB_A_PCI
default RTE_MB_A_PCI
#### Some feature-specific configs
# Everything except for the GDB simulator uses the same interrupt controller
config V850E_INTC
bool
default !V850E_SIM
# Everything except for the various simulators uses the "Timer D" unit
config V850E_TIMER_D
bool
default !V850E_SIM && !V850E2_SIM85E2
# Cache control used on some v850e1 processors
config V850E_CACHE
bool
default V850E_TEG || V850E_ME2
# Cache control used on v850e2 processors; I think this should
# actually apply to more, but currently only the SIM85E2S uses it
config V850E2_CACHE
bool
default V850E2_SIM85E2S
config NO_CACHE
bool
default !V850E_CACHE && !V850E2_CACHE
#### Misc config
config ROM_KERNEL
bool "Kernel in ROM"
depends V850E2_ANNA || (RTE_CB && !RTE_CB_MULTI)
depends V850E2_ANNA || V850E_AS85EP1 || RTE_CB_ME2
# Some platforms pre-zero memory, in which case the kernel doesn't need to
config ZERO_BSS
......@@ -177,9 +200,12 @@ menu "Processor type and features"
int
default 8 if V850E2_SIM85E2C || V850E2_FPGA85E2C
config V850E_HIGHRES_TIMER
bool "High resolution timer support"
depends V850E_TIMER_D
config TIME_BOOTUP
bool "Time bootup"
depends V850E_MA1_HIGHRES_TIMER
depends V850E_HIGHRES_TIMER
config RESET_GUARD
bool "Reset Guard"
......@@ -241,6 +267,7 @@ config KCORE_AOUT
default y
config KCORE_ELF
bool
default y
source "fs/Kconfig.binfmt"
......
arch/v850/kernel/Makefile
View file @ dce5ee27
......@@ -15,24 +15,26 @@ obj-y += intv.o entry.o process.o syscalls.o time.o semaphore.o setup.o \
signal.o irq.o mach.o ptrace.o bug.o
obj-$(CONFIG_MODULES) += module.o v850_ksyms.o
# chip-specific code
obj-$(CONFIG_V850E_NB85E) += nb85e_intc.o
obj-$(CONFIG_V850E_MA1) += ma.o nb85e_utils.o nb85e_timer_d.o
obj-$(CONFIG_V850E_TEG) += teg.o nb85e_utils.o nb85e_cache.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E2_ANNA) += anna.o nb85e_intc.o nb85e_utils.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E_AS85EP1) += as85ep1.o nb85e_intc.o nb85e_utils.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E_MA1) += ma.o
obj-$(CONFIG_V850E_ME2) += me2.o
obj-$(CONFIG_V850E_TEG) += teg.o
obj-$(CONFIG_V850E_AS85EP1) += as85ep1.o
obj-$(CONFIG_V850E2_ANNA) += anna.o
# platform-specific code
obj-$(CONFIG_V850E_SIM) += sim.o simcons.o
obj-$(CONFIG_V850E2_SIM85E2C) += sim85e2c.o nb85e_intc.o memcons.o
obj-$(CONFIG_V850E2_FPGA85E2C) += fpga85e2c.o nb85e_intc.o memcons.o
obj-$(CONFIG_V850E2_SIM85E2) += sim85e2.o memcons.o
obj-$(CONFIG_V850E2_FPGA85E2C) += fpga85e2c.o memcons.o
obj-$(CONFIG_RTE_CB) += rte_cb.o rte_cb_leds.o
obj-$(CONFIG_RTE_CB_MA1) += rte_ma1_cb.o
obj-$(CONFIG_RTE_CB_ME2) += rte_me2_cb.o
obj-$(CONFIG_RTE_CB_NB85E) += rte_nb85e_cb.o
obj-$(CONFIG_RTE_CB_MULTI) += rte_cb_multi.o
obj-$(CONFIG_RTE_MB_A_PCI) += rte_mb_a_pci.o
obj-$(CONFIG_RTE_GBUS_INT) += gbus_int.o
# feature-specific code
obj-$(CONFIG_V850E_MA1_HIGHRES_TIMER) += highres_timer.o
obj-$(CONFIG_V850E_INTC) += v850e_intc.o
obj-$(CONFIG_V850E_TIMER_D) += v850e_timer_d.o v850e_utils.o
obj-$(CONFIG_V850E_CACHE) += v850e_cache.o
obj-$(CONFIG_V850E2_CACHE) += v850e2_cache.o
obj-$(CONFIG_V850E_HIGHRES_TIMER) += highres_timer.o
obj-$(CONFIG_PROC_FS) += procfs.o
arch/v850/kernel/anna.c
View file @ dce5ee27
/*
* arch/v850/kernel/anna.c -- Anna V850E2 evaluation chip/board
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -21,8 +21,8 @@
#include <asm/machdep.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e_timer_d.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_timer_d.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -42,31 +42,33 @@ static void anna_led_tick (void);
void __init mach_early_init (void)
{
ANNA_ILBEN = 0;
ANNA_CSC(0) = 0x402F;
ANNA_CSC(1) = 0x4000;
ANNA_BPC = 0;
ANNA_BSC = 0xAAAA;
ANNA_BEC = 0;
ANNA_BHC = 0xFFFF; /* icache all memory, dcache all */
ANNA_BCT(0) = 0xB088;
ANNA_BCT(1) = 0x0008;
ANNA_DWC(0) = 0x0027;
ANNA_DWC(1) = 0;
ANNA_BCC = 0x0006;
ANNA_ASC = 0;
ANNA_LBS = 0x0089;
ANNA_SCR3 = 0x21A9;
ANNA_RFS3 = 0x8121;
nb85e_intc_disable_irqs ();
V850E2_CSC(0) = 0x402F;
V850E2_CSC(1) = 0x4000;
V850E2_BPC = 0;
V850E2_BSC = 0xAAAA;
V850E2_BEC = 0;
#if 0
V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */
#else
V850E2_BHC = 0; /* cache no memory */
#endif
V850E2_BCT(0) = 0xB088;
V850E2_BCT(1) = 0x0008;
V850E2_DWC(0) = 0x0027;
V850E2_DWC(1) = 0;
V850E2_BCC = 0x0006;
V850E2_ASC = 0;
V850E2_LBS = 0x0089;
V850E2_SCR(3) = 0x21A9;
V850E2_RFS(3) = 0x8121;
v850e_intc_disable_irqs ();
}
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (1);
#endif
ANNA_PORT_PM (LEDS_PORT) = 0; /* Make all LED pins output pins. */
mach_tick = anna_led_tick;
}
......@@ -95,12 +97,12 @@ void mach_gettimeofday (struct timespec *tv)
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "PIN", IRQ_INTP(0), IRQ_INTP_NUM, 1, 4 },
{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
......@@ -118,7 +120,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_restart (char *__unused)
......
arch/v850/kernel/as85ep1.c
View file @ dce5ee27
/*
* arch/v850/kernel/as85ep1.c -- AS85EP1 V850E evaluation chip/board
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -21,8 +21,8 @@
#include <asm/machdep.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e_timer_d.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_timer_d.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -90,20 +90,14 @@ void __init mach_early_init (void)
AS85EP1_IRAMM = 0x0; /* $BFbB"L?Na(BRAM$B$O!V(Bread-mode$B!W$K$J$j$^$9(B */
#endif /* !CONFIG_ROM_KERNEL */
nb85e_intc_disable_irqs ();
v850e_intc_disable_irqs ();
}
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (1);
#endif
AS85EP1_PORT_PMC (LEDS_PORT) = 0; /* Make the LEDs port an I/O port. */
AS85EP1_PORT_PM (LEDS_PORT) = 0; /* Make all the bits output pins. */
mach_tick = as85ep1_led_tick;
ROOT_DEV = MKDEV (BLKMEM_MAJOR, 0);
}
void __init mach_get_physical_ram (unsigned long *ram_start,
......@@ -137,21 +131,21 @@ void __init mach_reserve_bootmem ()
root_fs_image_end - root_fs_image_start);
}
void mach_gettimeofday (struct timeval *tv)
void mach_gettimeofday (struct timespec *tv)
{
tv->tv_sec = 0;
tv->tv_usec = 0;
tv->tv_nsec = 0;
}
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
......@@ -166,7 +160,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_restart (char *__unused)
......
arch/v850/kernel/fpga85e2c.c
View file @ dce5ee27
......@@ -2,8 +2,8 @@
* arch/v850/kernel/fpga85e2c.h -- Machine-dependent defs for
* FPGA implementation of V850E2/NA85E2C
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -46,7 +46,7 @@ void __init mach_early_init (void)
/* Set bus sizes: CS0 32-bit, CS1 16-bit, CS7 8-bit,
everything else 32-bit. */
BSC = 0x2AA6;
V850E2_BSC = 0x2AA6;
for (i = 2; i <= 6; i++)
CSDEV(i) = 0; /* 32 bit */
......@@ -134,7 +134,7 @@ void machine_power_off (void)
/* Interrupts */
struct nb85e_intc_irq_init irq_inits[] = {
struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "RPU", IRQ_RPU(0), IRQ_RPU_NUM, 1, 6 },
{ 0 }
......@@ -146,7 +146,7 @@ struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize interrupts. */
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
......
arch/v850/kernel/gbus_int.c
View file @ dce5ee27
......@@ -113,9 +113,7 @@ static irqreturn_t gbus_int_handle_irq (int irq, void *dev_id,
/* Only pay attention to enabled interrupts. */
status &= enable;
if (status) {
unsigned base_irq
= IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
irq = base_irq;
irq = IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
do {
/* There's an active interrupt in word
W, find out which one, and call its
......@@ -247,7 +245,7 @@ void __init gbus_int_init_irqs (void)
/* First initialize the shared gint interrupts. */
for (i = 0; i < NUM_USED_GINTS; i++) {
unsigned gint = used_gint[i].gint;
struct nb85e_intc_irq_init gint_irq_init[2];
struct v850e_intc_irq_init gint_irq_init[2];
/* We initialize one GINT interrupt at a time. */
gint_irq_init[0].name = "GINT";
......@@ -258,7 +256,7 @@ void __init gbus_int_init_irqs (void)
gint_irq_init[1].name = 0; /* Terminate the vector. */
nb85e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
v850e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
}
/* Then the GBUS interrupts. */
......
arch/v850/kernel/head.S
View file @ dce5ee27
/*
* arch/v850/kernel/head.S -- Lowest-level startup code
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -115,7 +115,14 @@ C_ENTRY(start):
jarl CSYM(memset), lp
#endif
// Start Linux kernel.
// What happens if the main kernel function returns (it shouldn't)
mov hilo(CSYM(machine_halt)), lp
jr CSYM(start_kernel)
// Start the linux kernel. We use an indirect jump to get extra
// range, because on some platforms this initial startup code
// (and the associated platform-specific code in mach_early_init)
// are located far away from the main kernel, e.g. so that they
// can initialize RAM first and copy the kernel or something.
mov hilo(CSYM(start_kernel)), r12
jmp [r12]
C_END(start)
arch/v850/kernel/highres_timer.c
View file @ dce5ee27
/*
* arch/v850/kernel/highres_timer.c -- High resolution timing routines
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -12,7 +12,7 @@
*/
#include <asm/system.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include <asm/highres_timer.h>
#define HIGHRES_TIMER_USEC_SHIFT 12
......@@ -42,7 +42,7 @@ void highres_timer_slow_tick_irq (void)
void highres_timer_reset (void)
{
NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT) = 0;
V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT) = 0;
HIGHRES_TIMER_SLOW_TICKS = 0;
}
......@@ -51,12 +51,12 @@ void highres_timer_start (void)
u32 fast_tick_rate;
/* Start hardware timer. */
nb85e_timer_d_configure (HIGHRES_TIMER_TIMER_D_UNIT,
v850e_timer_d_configure (HIGHRES_TIMER_TIMER_D_UNIT,
HIGHRES_TIMER_SLOW_TICK_RATE);
fast_tick_rate =
(NB85E_TIMER_D_BASE_FREQ
>> NB85E_TIMER_D_DIVLOG2 (HIGHRES_TIMER_TIMER_D_UNIT));
(V850E_TIMER_D_BASE_FREQ
>> V850E_TIMER_D_DIVLOG2 (HIGHRES_TIMER_TIMER_D_UNIT));
/* The obvious way of calculating microseconds from fast ticks
is to do:
......@@ -77,16 +77,16 @@ void highres_timer_start (void)
/* Enable the interrupt (which is hardwired to this use), and
give it the highest priority. */
NB85E_INTC_IC (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)) = 0;
V850E_INTC_IC (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)) = 0;
}
void highres_timer_stop (void)
{
/* Stop the timer. */
NB85E_TIMER_D_TMCD (HIGHRES_TIMER_TIMER_D_UNIT) =
NB85E_TIMER_D_TMCD_CAE;
V850E_TIMER_D_TMCD (HIGHRES_TIMER_TIMER_D_UNIT) =
V850E_TIMER_D_TMCD_CAE;
/* Disable its interrupt, just in case. */
nb85e_intc_disable_irq (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT));
v850e_intc_disable_irq (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT));
}
inline void highres_timer_read_ticks (u32 *slow_ticks, u32 *fast_ticks)
......@@ -95,9 +95,9 @@ inline void highres_timer_read_ticks (u32 *slow_ticks, u32 *fast_ticks)
u32 fast_ticks_1, fast_ticks_2, _slow_ticks;
local_irq_save (flags);
fast_ticks_1 = NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
fast_ticks_1 = V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
_slow_ticks = HIGHRES_TIMER_SLOW_TICKS;
fast_ticks_2 = NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
fast_ticks_2 = V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
local_irq_restore (flags);
if (fast_ticks_2 < fast_ticks_1)
......
arch/v850/kernel/intv.S
View file @ dce5ee27
......@@ -16,7 +16,7 @@
#include <asm/machdep.h>
#include <asm/entry.h>
#ifdef CONFIG_V850E_MA1_HIGHRES_TIMER
#ifdef CONFIG_V850E_HIGHRES_TIMER
#include <asm/highres_timer.h>
#endif
......@@ -59,7 +59,7 @@
.section .intv.mach, "ax"
.org 0x0
#if defined (CONFIG_V850E_MA1_HIGHRES_TIMER) && defined (IRQ_INTCMD)
#if defined (CONFIG_V850E_HIGHRES_TIMER) && defined (IRQ_INTCMD)
/* Interrupts before the highres timer interrupt. */
.rept IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)
......
arch/v850/kernel/ma.c
View file @ dce5ee27
......@@ -22,19 +22,19 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },
......@@ -51,7 +51,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize MA chip interrupts. */
void __init ma_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
......
arch/v850/kernel/me2.c 0 → 100644
View file @ dce5ee27
/*
* arch/v850/kernel/me2.c -- V850E/ME2 chip-specific support
*
* Copyright (C) 2003 NEC Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
{ "INTP", IRQ_INTP(0), IRQ_INTP_NUM, 1, 5 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 3 },
{ "UBTIRE", IRQ_INTUBTIRE(0), IRQ_INTUBTIRE_NUM, 5, 4 },
{ "UBTIR", IRQ_INTUBTIR(0), IRQ_INTUBTIR_NUM, 5, 4 },
{ "UBTIT", IRQ_INTUBTIT(0), IRQ_INTUBTIT_NUM, 5, 4 },
{ "UBTIF", IRQ_INTUBTIF(0), IRQ_INTUBTIF_NUM, 5, 4 },
{ "UBTITO", IRQ_INTUBTITO(0), IRQ_INTUBTITO_NUM, 5, 4 },
{ 0 }
};
#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)
static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize V850E/ME2 chip interrupts. */
void __init me2_init_irqs (void)
{
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
void me2_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
{
if (chan == 0) {
/* Specify that the relevent pins on the chip should do
serial I/O, not direct I/O. */
ME2_PORT1_PMC |= 0xC;
/* Specify that we're using the UART, not the CSI device. */
ME2_PORT1_PFC |= 0xC;
} else if (chan == 1) {
/* Specify that the relevent pins on the chip should do
serial I/O, not direct I/O. */
ME2_PORT2_PMC |= 0x6;
/* Specify that we're using the UART, not the CSI device. */
ME2_PORT2_PFC |= 0x6;
}
}
arch/v850/kernel/rte_cb.c
View file @ dce5ee27
......@@ -17,7 +17,7 @@
#include <linux/fs.h>
#include <asm/machdep.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -34,7 +34,7 @@ extern void multi_init (void);
void __init rte_cb_early_init (void)
{
nb85e_intc_disable_irqs ();
v850e_intc_disable_irqs ();
#ifdef CONFIG_RTE_CB_MULTI
multi_init ();
......@@ -43,6 +43,7 @@ void __init rte_cb_early_init (void)
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_RTE_MB_A_PCI
/* Probe for Mother-A, and print a message if we find it. */
*(volatile unsigned long *)MB_A_SRAM_ADDR = 0xDEADBEEF;
if (*(volatile unsigned long *)MB_A_SRAM_ADDR == 0xDEADBEEF) {
......@@ -52,23 +53,11 @@ void __init mach_setup (char **cmdline)
" NEC SolutionGear/Midas lab"
" RTE-MOTHER-A motherboard\n");
}
#if defined (CONFIG_V850E_NB85E_UART_CONSOLE) && !defined (CONFIG_TIME_BOOTUP)
nb85e_uart_cons_init (0);
#endif
#endif /* CONFIG_RTE_MB_A_PCI */
mach_tick = led_tick;
}
#ifdef CONFIG_TIME_BOOTUP
void initial_boot_done (void)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (0);
#endif
}
#endif
void machine_restart (char *__unused)
{
#ifdef CONFIG_RESET_GUARD
......@@ -194,6 +183,7 @@ static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
#endif /* CONFIG_RTE_GBUS_INT */
void __init rte_cb_init_irqs (void)
{
#ifdef CONFIG_RTE_GBUS_INT
......
arch/v850/kernel/rte_ma1_cb.c
View file @ dce5ee27
......@@ -20,7 +20,7 @@
#include <asm/page.h>
#include <asm/ma1.h>
#include <asm/rte_ma1_cb.h>
#include <asm/nb85e_timer_c.h>
#include <asm/v850e_timer_c.h>
#include "mach.h"
......@@ -89,14 +89,14 @@ void __init mach_init_irqs (void)
rte_cb_init_irqs ();
/* Use falling-edge-sensitivity for interrupts . */
NB85E_TIMER_C_SESC (0) &= ~0xC;
NB85E_TIMER_C_SESC (1) &= ~0xF;
V850E_TIMER_C_SESC (0) &= ~0xC;
V850E_TIMER_C_SESC (1) &= ~0xF;
/* INTP000-INTP011 are shared with `Timer C', so we have to set
up Timer C to pass them through as raw interrupts. */
for (tc = 0; tc < 2; tc++)
/* Turn on the timer. */
NB85E_TIMER_C_TMCC0 (tc) |= NB85E_TIMER_C_TMCC0_CAE;
V850E_TIMER_C_TMCC0 (tc) |= V850E_TIMER_C_TMCC0_CAE;
/* Make sure the relevant port0/port1 pins are assigned
interrupt duty. We used INTP001-INTP011 (don't screw with
......
arch/v850/kernel/rte_me2_cb.c 0 → 100644
View file @ dce5ee27
/*
* arch/v850/kernel/rte_me2_cb.c -- Midas labs RTE-V850E/ME2-CB board
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/fs.h>
#include <linux/major.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/me2.h>
#include <asm/rte_me2_cb.h>
#include <asm/machdep.h>
#include <asm/v850e_intc.h>
#include <asm/v850e_cache.h>
#include <asm/irq.h>
#include "mach.h"
extern unsigned long *_intv_start;
extern unsigned long *_intv_end;
/* LED access routines. */
extern unsigned read_leds (int pos, char *buf, int len);
extern unsigned write_leds (int pos, const char *buf, int len);
/* SDRAM are almost contiguous (with a small hole in between;
see mach_reserve_bootmem for details), so just use both as one big area. */
#define RAM_START SDRAM_ADDR
#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
void __init mach_get_physical_ram (unsigned long *ram_start,
unsigned long *ram_len)
{
*ram_start = RAM_START;
*ram_len = RAM_END - RAM_START;
}
void __init mach_reserve_bootmem ()
{
extern char _root_fs_image_start, _root_fs_image_end;
u32 root_fs_image_start = (u32)&_root_fs_image_start;
u32 root_fs_image_end = (u32)&_root_fs_image_end;
/* Reserve the memory used by the root filesystem image if it's
in RAM. */
if (root_fs_image_start >= RAM_START && root_fs_image_start < RAM_END)
reserve_bootmem (root_fs_image_start,
root_fs_image_end - root_fs_image_start);
}
void mach_gettimeofday (struct timespec *tv)
{
tv->tv_sec = 0;
tv->tv_nsec = 0;
}
/* Called before configuring an on-chip UART. */
void rte_me2_cb_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud)
{
/* The RTE-V850E/ME2-CB connects some general-purpose I/O
pins on the CPU to the RTS/CTS lines of UARTB channel 0's
serial connection.
I/O pins P21 and P22 are RTS and CTS respectively. */
if (chan == 0) {
/* Put P21 & P22 in I/O port mode. */
ME2_PORT2_PMC &= ~0x6;
/* Make P21 and output, and P22 an input. */
ME2_PORT2_PM = (ME2_PORT2_PM & ~0xC) | 0x4;
}
me2_uart_pre_configure (chan, cflags, baud);
}
void __init mach_init_irqs (void)
{
/* Initialize interrupts. */
me2_init_irqs ();
rte_me2_cb_init_irqs ();
}
#ifdef CONFIG_ROM_KERNEL
/* Initialization for kernel in ROM. */
static inline rom_kernel_init (void)
{
/* If the kernel is in ROM, we have to copy any initialized data
from ROM into RAM. */
extern unsigned long _data_load_start, _sdata, _edata;
register unsigned long *src = &_data_load_start;
register unsigned long *dst = &_sdata, *end = &_edata;
while (dst != end)
*dst++ = *src++;
}
#endif /* CONFIG_ROM_KERNEL */
static void install_interrupt_vectors (void)
{
unsigned long *p1, *p2;
ME2_IRAMM = 0x03; /* V850E/ME2 iRAM write mode */
/* vector copy to iRAM */
p1 = (unsigned long *)0; /* v85x vector start */
p2 = (unsigned long *)&_intv_start;
while (p2 < (unsigned long *)&_intv_end)
*p1++ = *p2++;
ME2_IRAMM = 0x00; /* V850E/ME2 iRAM read mode */
}
/* CompactFlash */
static void cf_power_on (void)
{
/* CF card detected? */
if (CB_CF_STS0 & 0x0030)
return;
CB_CF_REG0 = 0x0002; /* reest on */
mdelay (10);
CB_CF_REG0 = 0x0003; /* power on */
mdelay (10);
CB_CF_REG0 = 0x0001; /* reset off */
mdelay (10);
}
static void cf_power_off (void)
{
CB_CF_REG0 = 0x0003; /* power on */
mdelay (10);
CB_CF_REG0 = 0x0002; /* reest on */
mdelay (10);
}
void __init mach_early_init (void)
{
install_interrupt_vectors ();
/* CS1 SDRAM instruction cache enable */
v850e_cache_enable (0x04, 0x03, 0);
rte_cb_early_init ();
/* CompactFlash power on */
cf_power_on ();
#if defined (CONFIG_ROM_KERNEL)
rom_kernel_init ();
#endif
}
/* RTE-V850E/ME2-CB Programmable Interrupt Controller. */
static struct cb_pic_irq_init cb_pic_irq_inits[] = {
{ "CB_EXTTM0", IRQ_CB_EXTTM0, 1, 1, 6 },
{ "CB_EXTSIO", IRQ_CB_EXTSIO, 1, 1, 6 },
{ "CB_TOVER", IRQ_CB_TOVER, 1, 1, 6 },
{ "CB_GINT0", IRQ_CB_GINT0, 1, 1, 6 },
{ "CB_USB", IRQ_CB_USB, 1, 1, 6 },
{ "CB_LANC", IRQ_CB_LANC, 1, 1, 6 },
{ "CB_USB_VBUS_ON", IRQ_CB_USB_VBUS_ON, 1, 1, 6 },
{ "CB_USB_VBUS_OFF", IRQ_CB_USB_VBUS_OFF, 1, 1, 6 },
{ "CB_EXTTM1", IRQ_CB_EXTTM1, 1, 1, 6 },
{ "CB_EXTTM2", IRQ_CB_EXTTM2, 1, 1, 6 },
{ 0 }
};
#define NUM_CB_PIC_IRQ_INITS \
((sizeof cb_pic_irq_inits / sizeof cb_pic_irq_inits[0]) - 1)
static struct hw_interrupt_type cb_pic_hw_itypes[NUM_CB_PIC_IRQ_INITS];
static unsigned char cb_pic_active_irqs = 0;
void __init rte_me2_cb_init_irqs (void)
{
cb_pic_init_irq_types (cb_pic_irq_inits, cb_pic_hw_itypes);
/* Initalize on board PIC1 (not PIC0) enable */
CB_PIC_INT0M = 0x0000;
CB_PIC_INT1M = 0x0000;
CB_PIC_INTR = 0x0000;
CB_PIC_INTEN |= CB_PIC_INT1EN;
ME2_PORT2_PMC |= 0x08; /* INTP23/SCK1 mode */
ME2_PORT2_PFC &= ~0x08; /* INTP23 mode */
ME2_INTR(2) &= ~0x08; /* INTP23 falling-edge detect */
ME2_INTF(2) &= ~0x08; /* " */
rte_cb_init_irqs (); /* gbus &c */
}
/* Enable interrupt handling for interrupt IRQ. */
void cb_pic_enable_irq (unsigned irq)
{
CB_PIC_INT1M |= 1 << (irq - CB_PIC_BASE_IRQ);
}
void cb_pic_disable_irq (unsigned irq)
{
CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
}
void cb_pic_shutdown_irq (unsigned irq)
{
cb_pic_disable_irq (irq);
if (--cb_pic_active_irqs == 0)
free_irq (IRQ_CB_PIC, 0);
CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
}
static void cb_pic_handle_irq (int irq, void *dev_id, struct pt_regs *regs)
{
unsigned status = CB_PIC_INTR;
unsigned enable = CB_PIC_INT1M;
/* Only pay attention to enabled interrupts. */
status &= enable;
CB_PIC_INTEN &= ~CB_PIC_INT1EN;
if (status) {
unsigned mask = 1;
irq = CB_PIC_BASE_IRQ;
do {
/* There's an active interrupt, find out which one,
and call its handler. */
while (! (status & mask)) {
irq++;
mask <<= 1;
}
status &= ~mask;
CB_PIC_INTR = mask;
/* Recursively call handle_irq to handle it. */
handle_irq (irq, regs);
} while (status);
}
CB_PIC_INTEN |= CB_PIC_INT1EN;
}
static void irq_nop (unsigned irq) { }
static unsigned cb_pic_startup_irq (unsigned irq)
{
int rval;
if (cb_pic_active_irqs == 0) {
rval = request_irq (IRQ_CB_PIC, cb_pic_handle_irq,
SA_INTERRUPT, "cb_pic_handler", 0);
if (rval != 0)
return rval;
}
cb_pic_active_irqs++;
cb_pic_enable_irq (irq);
return 0;
}
/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
INITS (which is terminated by an entry with the name field == 0). */
void __init cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
struct hw_interrupt_type *hw_irq_types)
{
struct cb_pic_irq_init *init;
for (init = inits; init->name; init++) {
struct hw_interrupt_type *hwit = hw_irq_types++;
hwit->typename = init->name;
hwit->startup = cb_pic_startup_irq;
hwit->shutdown = cb_pic_shutdown_irq;
hwit->enable = cb_pic_enable_irq;
hwit->disable = cb_pic_disable_irq;
hwit->ack = irq_nop;
hwit->end = irq_nop;
/* Initialize kernel IRQ infrastructure for this interrupt. */
init_irq_handlers(init->base, init->num, init->interval, hwit);
}
}
arch/v850/kernel/rte_nb85e_cb.c
View file @ dce5ee27
......@@ -21,7 +21,7 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e.h>
#include <asm/v850e.h>
#include <asm/rte_nb85e_cb.h>
#include "mach.h"
......@@ -41,7 +41,7 @@ void __init mach_early_init (void)
Unfortunately, the dcache seems to be buggy, so we only use the
icache for now. */
nb85e_cache_enable (0x0040 /* BHC */, 0x0000 /* DCC */);
v850e_cache_enable (0x0040 /*BHC*/, 0x0003 /*ICC*/, 0x0000 /*DCC*/);
rte_cb_early_init ();
}
......
arch/v850/kernel/sim85e2c.c → arch/v850/kernel/sim85e2.c
View file @ dce5ee27
/*
* arch/v850/kernel/sim85e2c.c -- Machine-specific stuff for
* arch/v850/kernel/sim85e2.c -- Machine-specific stuff for
* V850E2 RTL simulator
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -26,17 +26,47 @@
#include "mach.h"
/* There are 4 possible areas we can use:
IRAM (1MB) is fast for instruction fetches, but slow for data
DRAM (1020KB) is fast for data, but slow for instructions
ERAM is cached, so should be fast for both insns and data
SDRAM is external DRAM, similar to ERAM
*/
#define INIT_MEMC_FOR_SDRAM
#define USE_SDRAM_AREA
#define KERNEL_IN_SDRAM_AREA
#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WT
/*#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WB_ALLOC*/
#ifdef USE_SDRAM_AREA
#define RAM_START SDRAM_ADDR
#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
#else
/* When we use DRAM, we need to account for the fact that the end of it is
used for R0_RAM. */
#define RAM_START DRAM_ADDR
#define RAM_END R0_RAM_ADDR
#endif
extern void memcons_setup (void);
void __init mach_early_init (void)
#ifdef KERNEL_IN_SDRAM_AREA
#define EARLY_INIT_SECTION_ATTR __attribute__ ((section (".early.text")))
#else
#define EARLY_INIT_SECTION_ATTR __init
#endif
void EARLY_INIT_SECTION_ATTR mach_early_init (void)
{
extern int panic_timeout;
/* Don't stop the simulator at `halt' instructions. */
NOTHAL = 1;
/* The sim85e2c simulator tracks `undefined' values, so to make
/* The sim85e2 simulator tracks `undefined' values, so to make
debugging easier, we begin by zeroing out all otherwise
undefined registers. This is not strictly necessary.
......@@ -67,10 +97,41 @@ void __init mach_early_init (void)
asm volatile ("ldsr r0, 16; ldsr r0, 17; ldsr r0, 18; ldsr r0, 19");
asm volatile ("ldsr r0, 20");
#ifdef INIT_MEMC_FOR_SDRAM
/* Settings for SDRAM controller. */
V850E2_VSWC = 0x0042;
V850E2_BSC = 0x9286;
V850E2_BCT(0) = 0xb000; /* was: 0 */
V850E2_BCT(1) = 0x000b;
V850E2_ASC = 0;
V850E2_LBS = 0xa9aa; /* was: 0xaaaa */
V850E2_LBC(0) = 0;
V850E2_LBC(1) = 0; /* was: 0x3 */
V850E2_BCC = 0;
V850E2_RFS(4) = 0x800a; /* was: 0xf109 */
V850E2_SCR(4) = 0x2091; /* was: 0x20a1 */
V850E2_RFS(3) = 0x800c;
V850E2_SCR(3) = 0x20a1;
V850E2_DWC(0) = 0;
V850E2_DWC(1) = 0;
#endif
#if 0
#ifdef CONFIG_V850E2_SIM85E2S
/* Turn on the caches. */
NA85E2C_CACHE_BTSC
|= (NA85E2C_CACHE_BTSC_ICM | NA85E2C_CACHE_BTSC_DCM0);
NA85E2C_BUSM_BHC = 0xFFFF;
V850E2_CACHE_BTSC = V850E2_CACHE_BTSC_ICM | DCACHE_MODE;
V850E2_BHC = 0x1010;
#elif CONFIG_V850E2_SIM85E2C
V850E2_CACHE_BTSC |= (V850E2_CACHE_BTSC_ICM | V850E2_CACHE_BTSC_DCM0);
V850E2_BUSM_BHC = 0xFFFF;
#endif
#else
V850E2_BHC = 0;
#endif
/* Don't stop the simulator at `halt' instructions. */
SIM85E2_NOTHAL = 1;
/* Ensure that the simulator halts on a panic, instead of going
into an infinite loop inside the panic function. */
......@@ -84,18 +145,23 @@ void __init mach_setup (char **cmdline)
void mach_get_physical_ram (unsigned long *ram_start, unsigned long *ram_len)
{
/* There are 3 possible areas we can use:
IRAM (1MB) is fast for instruction fetches, but slow for data
DRAM (1020KB) is fast for data, but slow for instructions
ERAM is cached, so should be fast for both insns and data,
_but_ currently only supports write-through caching, so
writes are slow.
Since there's really no area that's good for general kernel
use, we use DRAM -- it won't be good for user programs
(which will be loaded into kernel allocated memory), but
currently we're more concerned with testing the kernel. */
*ram_start = DRAM_ADDR;
*ram_len = R0_RAM_ADDR - DRAM_ADDR;
*ram_start = RAM_START;
*ram_len = RAM_END - RAM_START;
}
void __init mach_reserve_bootmem ()
{
extern char _root_fs_image_start, _root_fs_image_end;
u32 root_fs_image_start = (u32)&_root_fs_image_start;
u32 root_fs_image_end = (u32)&_root_fs_image_end;
/* Reserve the memory used by the root filesystem image if it's
in RAM. */
if (root_fs_image_end > root_fs_image_start
&& root_fs_image_start >= RAM_START
&& root_fs_image_start < RAM_END)
reserve_bootmem (root_fs_image_start,
root_fs_image_end - root_fs_image_start);
}
void __init mach_sched_init (struct irqaction *timer_action)
......@@ -114,7 +180,7 @@ void mach_gettimeofday (struct timespec *tv)
/* Interrupts */
struct nb85e_intc_irq_init irq_inits[] = {
struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ 0 }
};
......@@ -123,14 +189,14 @@ struct hw_interrupt_type hw_itypes[1];
/* Initialize interrupts. */
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_halt (void) __attribute__ ((noreturn));
void machine_halt (void)
{
SIMFIN = 0; /* Halt immediately. */
SIM85E2_SIMFIN = 0; /* Halt immediately. */
for (;;) {}
}
......
arch/v850/kernel/teg.c
View file @ dce5ee27
......@@ -22,7 +22,7 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
......@@ -31,12 +31,12 @@ void __init mach_sched_init (struct irqaction *timer_action)
/* Select timer interrupt instead of external pin. */
TEG_ISS |= 0x1;
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 1, 3 },
......@@ -51,7 +51,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize MA chip interrupts. */
void __init teg_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
......
arch/v850/kernel/v850e2_cache.c 0 → 100644
View file @ dce5ee27
/*
* arch/v850/kernel/v850e2_cache.c -- Cache control for V850E2 cache
* memories
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/mm.h>
#include <asm/v850e2_cache.h>
/* Cache operations we can do. The encoding corresponds directly to the
value we need to write into the COPR register. */
enum cache_op {
OP_SYNC_IF_DIRTY = V850E2_CACHE_COPR_CFC(0), /* 000 */
OP_SYNC_IF_VALID = V850E2_CACHE_COPR_CFC(1), /* 001 */
OP_SYNC_IF_VALID_AND_CLEAR = V850E2_CACHE_COPR_CFC(3), /* 011 */
OP_WAY_CLEAR = V850E2_CACHE_COPR_CFC(4), /* 100 */
OP_FILL = V850E2_CACHE_COPR_CFC(5), /* 101 */
OP_CLEAR = V850E2_CACHE_COPR_CFC(6), /* 110 */
OP_CREATE_DIRTY = V850E2_CACHE_COPR_CFC(7) /* 111 */
};
/* Which cache to use. This encoding also corresponds directly to the
value we need to write into the COPR register. */
enum cache {
ICACHE = 0,
DCACHE = V850E2_CACHE_COPR_LBSL
};
/* Returns ADDR rounded down to the beginning of its cache-line. */
#define CACHE_LINE_ADDR(addr) \
((addr) & ~(V850E2_CACHE_LINE_SIZE - 1))
/* Returns END_ADDR rounded up to the `limit' of its cache-line. */
#define CACHE_LINE_END_ADDR(end_addr) \
CACHE_LINE_ADDR(end_addr + (V850E2_CACHE_LINE_SIZE - 1))
/* Low-level cache ops. */
/* Apply cache-op OP to all entries in CACHE. */
static inline void cache_op_all (enum cache_op op, enum cache cache)
{
int cmd = op | cache | V850E2_CACHE_COPR_WSLE | V850E2_CACHE_COPR_STRT;
if (op != OP_WAY_CLEAR) {
/* The WAY_CLEAR operation does the whole way, but other
ops take begin-index and count params; we just indicate
the entire cache. */
V850E2_CACHE_CADL = 0;
V850E2_CACHE_CADH = 0;
V850E2_CACHE_CCNT = V850E2_CACHE_WAY_SIZE - 1;
}
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(0); /* way 0 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(1); /* way 1 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(2); /* way 2 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(3); /* way 3 */
}
/* Apply cache-op OP to all entries in CACHE covering addresses ADDR
through ADDR+LEN. */
static inline void cache_op_range (enum cache_op op, u32 addr, u32 len,
enum cache cache)
{
u32 start = CACHE_LINE_ADDR (addr);
u32 end = CACHE_LINE_END_ADDR (addr + len);
u32 num_lines = (end - start) >> V850E2_CACHE_LINE_SIZE_BITS;
V850E2_CACHE_CADL = start & 0xFFFF;
V850E2_CACHE_CADH = start >> 16;
V850E2_CACHE_CCNT = num_lines - 1;
V850E2_CACHE_COPR = op | cache | V850E2_CACHE_COPR_STRT;
}
/* High-level ops. */
static void cache_exec_after_store_all (void)
{
cache_op_all (OP_SYNC_IF_DIRTY, DCACHE);
cache_op_all (OP_WAY_CLEAR, ICACHE);
}
static void cache_exec_after_store_range (u32 start, u32 len)
{
cache_op_range (OP_SYNC_IF_DIRTY, start, len, DCACHE);
cache_op_range (OP_CLEAR, start, len, ICACHE);
}
/* Exported functions. */
void flush_icache (void)
{
cache_exec_after_store_all ();
}
void flush_icache_range (unsigned long start, unsigned long end)
{
cache_exec_after_store_range (start, end - start);
}
void flush_icache_page (struct vm_area_struct *vma, struct page *page)
{
cache_exec_after_store_range (page_to_virt (page), PAGE_SIZE);
}
void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len)
{
cache_exec_after_store_range (addr, len);
}
void flush_cache_sigtramp (unsigned long addr)
{
/* For the exact size, see signal.c, but 16 bytes should be enough. */
cache_exec_after_store_range (addr, 16);
}
arch/v850/kernel/nb85e_cache.c → arch/v850/kernel/v850e_cache.c
View file @ dce5ee27
/*
* arch/v850/kernel/nb85e_cache.c -- Cache control for NB85E_CACHE212 and
* NB85E_CACHE213 cache memories
* arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
......@@ -12,19 +11,31 @@
* Written by Miles Bader <miles@gnu.org>
*/
/* This file implements cache control for the rather simple cache used on
some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
CPU. V850E2 processors have their own (better) cache
implementation. */
#include <asm/entry.h>
#include <asm/nb85e_cache.h>
#include <asm/v850e_cache.h>
#define WAIT_UNTIL_CLEAR(value) while (value) {}
/* Set caching params via the BHC and DCC registers. */
void nb85e_cache_enable (u16 bhc, u16 dcc)
void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
{
unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
register u16 bhc_val asm ("r6") = bhc;
/* Read the instruction cache control register (ICC) and confirm
that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
V850E_CACHE_ICC = icc;
#ifdef V850E_CACHE_DCC
/* Configure data-cache. */
NB85E_CACHE_DCC = dcc;
V850E_CACHE_DCC = dcc;
#endif /* V850E_CACHE_DCC */
/* Configure caching for various memory regions by writing the BHC
register. The documentation says that an instruction _cannot_
......@@ -32,9 +43,12 @@ void nb85e_cache_enable (u16 bhc, u16 dcc)
instruction itself exists; to work around this, we store
appropriate instructions into the on-chip RAM area (which is never
cached), and briefly jump there to do the work. */
r0_ram[0] = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
r0_ram[1] = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
r0_ram[2] = 0x5640006b; /* jmp [r11] */
#ifdef V850E_CACHE_WRITE_IBS
*r0_ram++ = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
#endif
*r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
*r0_ram = 0x5640006b; /* jmp [r11] */
asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
:: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
}
......@@ -43,11 +57,11 @@ static void clear_icache (void)
{
/* 1. Read the instruction cache control register (ICC) and confirm
that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
/* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
cleared. Bit 13 of the ICC register is always cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x1000);
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
/* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
when clearing way 0 and way 1 at the same time:
......@@ -55,13 +69,17 @@ static void clear_icache (void)
(b) Read the TCLR0 and TCLR1 bits to confirm that these bits
are cleared.
(c) Perform (a) and (b) above again. */
NB85E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
V850E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
#ifdef V850E_CACHE_REPEAT_ICC_WRITE
/* Do it again. */
NB85E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
V850E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
#endif
}
#ifdef V850E_CACHE_DCC
/* Flush or clear (or both) the data cache, depending on the value of FLAGS;
the procedure is the same for both, just the control bits used differ (and
both may be performed simultaneously). */
......@@ -69,47 +87,54 @@ static void dcache_op (unsigned short flags)
{
/* 1. Read the data cache control register (DCC) and confirm that bits
0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_DCC & 0x33);
WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
/* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
depending on the way for which tags are to be cleared. */
NB85E_CACHE_DCC &= ~0xC000;
V850E_CACHE_DCC &= ~0xC000;
/* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
the way for which tags are to be cleared.
...
Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
on the way to be data flushed. */
NB85E_CACHE_DCC |= flags;
V850E_CACHE_DCC |= flags;
/* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
on the way for which tags were cleared [flushed] and confirm
that that bit is cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_DCC & flags);
WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
}
#endif /* V850E_CACHE_DCC */
/* Flushes the contents of the dcache to memory. */
static inline void flush_dcache (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if in write-back mode. */
if (NB85E_CACHE_DCC & 0x0400)
if (V850E_CACHE_DCC & 0x0400)
dcache_op (0x30);
#endif /* V850E_CACHE_DCC */
}
/* Flushes the contents of the dcache to memory, and then clears it. */
static inline void clear_dcache (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if the dcache is enabled. */
if (NB85E_CACHE_DCC & 0x0C00)
if (V850E_CACHE_DCC & 0x0C00)
dcache_op (0x33);
#endif /* V850E_CACHE_DCC */
}
/* Clears the dcache without flushing to memory first. */
static inline void clear_dcache_no_flush (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if the dcache is enabled. */
if (NB85E_CACHE_DCC & 0x0C00)
if (V850E_CACHE_DCC & 0x0C00)
dcache_op (0x3);
#endif /* V850E_CACHE_DCC */
}
static inline void cache_exec_after_store (void)
......@@ -121,58 +146,28 @@ static inline void cache_exec_after_store (void)
/* Exported functions. */
void inline nb85e_cache_flush_all (void)
{
clear_icache ();
clear_dcache ();
}
void nb85e_cache_flush_mm (struct mm_struct *mm)
{
/* nothing */
}
void nb85e_cache_flush_range (struct mm_struct *mm,
unsigned long start, unsigned long end)
{
/* nothing */
}
void nb85e_cache_flush_page (struct vm_area_struct *vma,
unsigned long page_addr)
{
/* nothing */
}
void nb85e_cache_flush_dcache_page (struct page *page)
{
/* nothing */
}
void nb85e_cache_flush_icache (void)
void flush_icache (void)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_range (unsigned long start, unsigned long end)
void flush_icache_range (unsigned long start, unsigned long end)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_page (struct vm_area_struct *vma,
struct page *page)
void flush_icache_page (struct vm_area_struct *vma, struct page *page)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_user_range (struct vm_area_struct *vma,
struct page *page,
void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
unsigned long adr, int len)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_sigtramp (unsigned long addr)
void flush_cache_sigtramp (unsigned long addr)
{
cache_exec_after_store ();
}
arch/v850/kernel/nb85e_intc.c → arch/v850/kernel/v850e_intc.c
View file @ dce5ee27
/*
* arch/v850/kernel/nb85e_intc.c -- NB85E cpu core interrupt controller (INTC)
* arch/v850/kernel/v850e_intc.c -- V850E interrupt controller (INTC)
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
......@@ -15,18 +15,18 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/nb85e_intc.h>
#include <asm/v850e_intc.h>
static void irq_nop (unsigned irq) { }
static unsigned nb85e_intc_irq_startup (unsigned irq)
static unsigned v850e_intc_irq_startup (unsigned irq)
{
nb85e_intc_clear_pending_irq (irq);
nb85e_intc_enable_irq (irq);
v850e_intc_clear_pending_irq (irq);
v850e_intc_enable_irq (irq);
return 0;
}
static void nb85e_intc_end_irq (unsigned irq)
static void v850e_intc_end_irq (unsigned irq)
{
unsigned long psw, temp;
......@@ -64,22 +64,22 @@ static void nb85e_intc_end_irq (unsigned irq)
/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
INITS (which is terminated by an entry with the name field == 0). */
void __init nb85e_intc_init_irq_types (struct nb85e_intc_irq_init *inits,
void __init v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
struct hw_interrupt_type *hw_irq_types)
{
struct nb85e_intc_irq_init *init;
struct v850e_intc_irq_init *init;
for (init = inits; init->name; init++) {
unsigned i;
struct hw_interrupt_type *hwit = hw_irq_types++;
hwit->typename = init->name;
hwit->startup = nb85e_intc_irq_startup;
hwit->shutdown = nb85e_intc_disable_irq;
hwit->enable = nb85e_intc_enable_irq;
hwit->disable = nb85e_intc_disable_irq;
hwit->startup = v850e_intc_irq_startup;
hwit->shutdown = v850e_intc_disable_irq;
hwit->enable = v850e_intc_enable_irq;
hwit->disable = v850e_intc_disable_irq;
hwit->ack = irq_nop;
hwit->end = nb85e_intc_end_irq;
hwit->end = v850e_intc_end_irq;
/* Initialize kernel IRQ infrastructure for this interrupt. */
init_irq_handlers(init->base, init->num, init->interval, hwit);
......@@ -92,13 +92,13 @@ void __init nb85e_intc_init_irq_types (struct nb85e_intc_irq_init *inits,
interrupts are initially disabled), then
assume whoever enabled it has set things up
properly, and avoid messing with it. */
if (! nb85e_intc_irq_enabled (irq))
if (! v850e_intc_irq_enabled (irq))
/* This write also (1) disables the
interrupt, and (2) clears any pending
interrupts. */
NB85E_INTC_IC (irq)
= (NB85E_INTC_IC_PR (init->priority)
| NB85E_INTC_IC_MK);
V850E_INTC_IC (irq)
= (V850E_INTC_IC_PR (init->priority)
| V850E_INTC_IC_MK);
}
}
}
arch/v850/kernel/nb85e_timer_d.c → arch/v850/kernel/v850e_timer_d.c
View file @ dce5ee27
/*
* include/asm-v850/nb85e_timer_d.c -- `Timer D' component often used
* with the NB85E cpu core
* include/asm-v850/v850e_timer_d.c -- `Timer D' component often used
* with V850E CPUs
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -14,41 +14,41 @@
#include <linux/kernel.h>
#include <asm/nb85e_utils.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_utils.h>
#include <asm/v850e_timer_d.h>
/* Start interval timer TIMER (0-3). The timer will issue the
corresponding INTCMD interrupt RATE times per second.
This function does not enable the interrupt. */
void nb85e_timer_d_configure (unsigned timer, unsigned rate)
void v850e_timer_d_configure (unsigned timer, unsigned rate)
{
unsigned divlog2, count;
/* Calculate params for timer. */
if (! calc_counter_params (
NB85E_TIMER_D_BASE_FREQ, rate,
NB85E_TIMER_D_TMCD_CS_MIN, NB85E_TIMER_D_TMCD_CS_MAX, 16,
V850E_TIMER_D_BASE_FREQ, rate,
V850E_TIMER_D_TMCD_CS_MIN, V850E_TIMER_D_TMCD_CS_MAX, 16,
&divlog2, &count))
printk (KERN_WARNING
"Cannot find interval timer %d setting suitable"
" for rate of %dHz.\n"
"Using rate of %dHz instead.\n",
timer, rate,
(NB85E_TIMER_D_BASE_FREQ >> divlog2) >> 16);
(V850E_TIMER_D_BASE_FREQ >> divlog2) >> 16);
/* Do the actual hardware timer initialization: */
/* Enable timer. */
NB85E_TIMER_D_TMCD(timer) = NB85E_TIMER_D_TMCD_CAE;
V850E_TIMER_D_TMCD(timer) = V850E_TIMER_D_TMCD_CAE;
/* Set clock divider. */
NB85E_TIMER_D_TMCD(timer)
= NB85E_TIMER_D_TMCD_CAE
| NB85E_TIMER_D_TMCD_CS(divlog2);
V850E_TIMER_D_TMCD(timer)
= V850E_TIMER_D_TMCD_CAE
| V850E_TIMER_D_TMCD_CS(divlog2);
/* Set timer compare register. */
NB85E_TIMER_D_CMD(timer) = count;
V850E_TIMER_D_CMD(timer) = count;
/* Start counting. */
NB85E_TIMER_D_TMCD(timer)
= NB85E_TIMER_D_TMCD_CAE
| NB85E_TIMER_D_TMCD_CS(divlog2)
| NB85E_TIMER_D_TMCD_CE;
V850E_TIMER_D_TMCD(timer)
= V850E_TIMER_D_TMCD_CAE
| V850E_TIMER_D_TMCD_CS(divlog2)
| V850E_TIMER_D_TMCD_CE;
}
arch/v850/kernel/nb85e_utils.c → arch/v850/kernel/v850e_utils.c
View file @ dce5ee27
/*
* include/asm-v850/nb85e_utils.h -- Utility functions associated with
* the NB85E cpu core
* include/asm-v850/v850e_utils.h -- Utility functions associated with
* V850E CPUs
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -12,10 +12,7 @@
* Written by Miles Bader <miles@gnu.org>
*/
/* Note: these functions are often associated with the N85E cpu core,
but not always, which is why they're not in `nb85e.c'. */
#include <asm/nb85e_utils.h>
#include <asm/v850e_utils.h>
/* Calculate counter clock-divider and count values to attain the
desired frequency RATE from the base frequency BASE_FREQ. The
......
arch/v850/rte_me2_cb.ld 0 → 100644
View file @ dce5ee27
/* Linker script for the Midas labs RTE-V850E/ME2-CB evaluation board
(CONFIG_RTE_CB_ME2), with kernel in SDRAM. */
MEMORY {
/* 128Kbyte of IRAM */
IRAM : ORIGIN = 0x00000000, LENGTH = 0x00020000
/* 32MB of SDRAM. */
SDRAM : ORIGIN = 0x00800000, LENGTH = 0x02000000
}
#define KRAM SDRAM
SECTIONS {
.text : {
__kram_start = . ;
TEXT_CONTENTS
INTV_CONTENTS /* copy to iRAM (0x0-0x620) */
} > KRAM
.data : {
DATA_CONTENTS
BSS_CONTENTS
RAMK_INIT_CONTENTS
__kram_end = . ;
BOOTMAP_CONTENTS
} > KRAM
.root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
}
arch/v850/sim85e2c.ld → arch/v850/sim85e2.ld
View file @ dce5ee27
......@@ -19,26 +19,26 @@ MEMORY {
/* `external ram' (CS1 area), comes after IRAM.
This should match ERAM_ADDR in "include/asm-v580/sim85e2c.h". */
ERAM : ORIGIN = 0x00100000, LENGTH = 0x07f00000
/* Dynamic RAM; uses memory controller. */
/* SDRAM : ORIGIN = 0x10000000, LENGTH = 0x01000000 */
SDRAM : ORIGIN = 0x10000000, LENGTH = 0x00200000/*use 2MB*/
}
SECTIONS {
.iram : {
INTV_CONTENTS
TEXT_CONTENTS
RAMK_INIT_CONTENTS
*arch/v850/kernel/head.o
*(.early.text)
} > IRAM
.data : {
__kram_start = . ;
DATA_CONTENTS
BSS_CONTENTS
ROOT_FS_CONTENTS
/* We stick console output into a buffer here. */
.dram : {
_memcons_output = . ;
. = . + 0x8000 ;
_memcons_output_end = . ;
__kram_end = . ;
BOOTMAP_CONTENTS
} > DRAM AT> DRAM_LOAD
} > DRAM
.sdram : {
/* We stick console output into a buffer here. */
RAMK_KRAM_CONTENTS
ROOT_FS_CONTENTS
} > SDRAM
}
arch/v850/vmlinux.lds.S
View file @ dce5ee27
......@@ -206,8 +206,8 @@ _jiffies = _jiffies_64 ;
# include "sim.ld"
#endif
#ifdef CONFIG_V850E2_SIM85E2C
# include "sim85e2c.ld"
#ifdef CONFIG_V850E2_SIM85E2
# include "sim85e2.ld"
#endif
#ifdef CONFIG_V850E2_FPGA85E2C
......@@ -247,3 +247,8 @@ _jiffies = _jiffies_64 ;
# include "rte_nb85e_cb.ld"
# endif
#endif
#ifdef CONFIG_RTE_CB_ME2
# include "rte_me2_cb.ld"
#endif
drivers/block/Kconfig
View file @ dce5ee27
......@@ -264,6 +264,7 @@ config BLK_DEV_LOOP
config BLK_DEV_CRYPTOLOOP
tristate "Cryptoloop Support"
select CRYPTO
depends on BLK_DEV_LOOP
---help---
Say Y here if you want to be able to use the ciphers that are
......@@ -339,7 +340,7 @@ config BLK_DEV_INITRD
config LBD
bool "Support for Large Block Devices"
depends on X86
depends on X86 || MIPS32 || PPC32 || ARCH_S390_31 || SUPERH
help
Say Y here if you want to attach large (bigger than 2TB) discs to
your machine, or if you want to have a raid or loopback device
......
drivers/block/as-iosched.c
View file @ dce5ee27
......@@ -833,10 +833,11 @@ static void as_update_iohist(struct as_io_context *aic, struct request *rq)
+ 2*1024*64);
aic->seek_samples += 256;
aic->seek_total += 256*seek_dist;
aic->seek_total += (u64)256*seek_dist;
if (aic->seek_samples) {
aic->seek_mean = aic->seek_total + 128;
sector_div(aic->seek_mean, aic->seek_samples);
u64 total = aic->seek_total + (aic->seek_samples>>1);
do_div(total, aic->seek_samples);
aic->seek_mean = (sector_t)total;
}
aic->seek_samples = (aic->seek_samples>>1)
+ (aic->seek_samples>>2);
......@@ -1305,6 +1306,15 @@ static void as_add_request(struct as_data *ad, struct as_rq *arq)
as_update_arq(ad, arq); /* keep state machine up to date */
}
/*
* FIXME: HACK for AS requeue problems
*/
static void as_requeue_request(request_queue_t *q, struct request *rq)
{
elv_completed_request(q, rq);
__elv_add_request(q, rq, 0, 0);
}
static void
as_insert_request(request_queue_t *q, struct request *rq,
struct list_head *insert_here)
......@@ -1820,6 +1830,7 @@ elevator_t iosched_as = {
.elevator_next_req_fn = as_next_request,
.elevator_add_req_fn = as_insert_request,
.elevator_remove_req_fn = as_remove_request,
.elevator_requeue_req_fn = as_requeue_request,
.elevator_queue_empty_fn = as_queue_empty,
.elevator_completed_req_fn = as_completed_request,
.elevator_former_req_fn = as_former_request,
......
drivers/block/cciss_scsi.c
View file @ dce5ee27
......@@ -712,7 +712,8 @@ cciss_scsi_detect(int ctlr)
sh->hostdata[0] = (unsigned long) hba[ctlr];
sh->irq = hba[ctlr]->intr;
sh->unique_id = sh->irq;
scsi_add_host(sh, &hba[ctlr]->pdev->dev);
scsi_add_host(sh, &hba[ctlr]->pdev->dev); /* XXX handle failure */
scsi_scan_host(sh);
return 1;
}
......
drivers/block/elevator.c
View file @ dce5ee27
......@@ -213,6 +213,18 @@ void elv_merge_requests(request_queue_t *q, struct request *rq,
e->elevator_merge_req_fn(q, rq, next);
}
void elv_requeue_request(request_queue_t *q, struct request *rq)
{
/*
* if iosched has an explicit requeue hook, then use that. otherwise
* just put the request at the front of the queue
*/
if (q->elevator.elevator_requeue_req_fn)
q->elevator.elevator_requeue_req_fn(q, rq);
else
__elv_add_request(q, rq, 0, 0);
}
void __elv_add_request(request_queue_t *q, struct request *rq, int at_end,
int plug)
{
......@@ -416,6 +428,7 @@ EXPORT_SYMBOL(elevator_noop);
EXPORT_SYMBOL(elv_add_request);
EXPORT_SYMBOL(__elv_add_request);
EXPORT_SYMBOL(elv_requeue_request);
EXPORT_SYMBOL(elv_next_request);
EXPORT_SYMBOL(elv_remove_request);
EXPORT_SYMBOL(elv_queue_empty);
......
drivers/block/ioctl.c
View file @ dce5ee27
......@@ -166,13 +166,11 @@ int blkdev_ioctl(struct inode *inode, struct file *file, unsigned cmd,
return -EINVAL;
if (get_user(n, (int *) arg))
return -EFAULT;
if (n > PAGE_SIZE || n < 512 || (n & (n - 1)))
return -EINVAL;
if (bd_claim(bdev, &holder) < 0)
return -EBUSY;
set_blocksize(bdev, n);
ret = set_blocksize(bdev, n);
bd_release(bdev);
return 0;
return ret;
case BLKPG:
return blkpg_ioctl(bdev, (struct blkpg_ioctl_arg *) arg);
case BLKRRPART:
......
drivers/block/ll_rw_blk.c
View file @ dce5ee27
......@@ -1494,6 +1494,23 @@ struct request *blk_get_request(request_queue_t *q, int rw, int gfp_mask)
return rq;
}
/**
* blk_requeue_request - put a request back on queue
* @q: request queue where request should be inserted
* @rq: request to be inserted
*
* Description:
* Drivers often keep queueing requests until the hardware cannot accept
* more, when that condition happens we need to put the request back
* on the queue. Must be called with queue lock held.
*/
void blk_requeue_request(request_queue_t *q, struct request *rq)
{
if (blk_rq_tagged(rq))
blk_queue_end_tag(q, rq);
elv_requeue_request(q, rq);
}
/**
* blk_insert_request - insert a special request in to a request queue
......@@ -2730,6 +2747,7 @@ EXPORT_SYMBOL(blk_hw_contig_segment);
EXPORT_SYMBOL(blk_get_request);
EXPORT_SYMBOL(blk_put_request);
EXPORT_SYMBOL(blk_insert_request);
EXPORT_SYMBOL(blk_requeue_request);
EXPORT_SYMBOL(blk_queue_prep_rq);
EXPORT_SYMBOL(blk_queue_merge_bvec);
......
drivers/block/nbd.c
View file @ dce5ee27
......@@ -258,7 +258,8 @@ void nbd_send_req(struct nbd_device *lo, struct request *req)
dprintk(DBG_TX, "%s: request %p: sending control (%s@%llu,%luB)\n",
lo->disk->disk_name, req,
nbdcmd_to_ascii(nbd_cmd(req)),
req->sector << 9, req->nr_sectors << 9);
(unsigned long long)req->sector << 9,
req->nr_sectors << 9);
result = sock_xmit(sock, 1, &request, sizeof(request),
(nbd_cmd(req) == NBD_CMD_WRITE)? MSG_MORE: 0);
if (result <= 0) {
......
drivers/char/agp/i460-agp.c
View file @ dce5ee27
......@@ -608,7 +608,7 @@ static struct pci_driver agp_intel_i460_pci_driver = {
.name = "agpgart-intel-i460",
.id_table = agp_intel_i460_pci_table,
.probe = agp_intel_i460_probe,
.remove = agp_intel_i460_remove,
.remove = __devexit_p(agp_intel_i460_remove),
};
static int __init agp_intel_i460_init(void)
......
drivers/char/ftape/lowlevel/fdc-io.c
View file @ dce5ee27
......@@ -66,6 +66,7 @@ int ft_mach2 = CONFIG_FT_MACH2;
/* Local vars.
*/
static spinlock_t fdc_io_lock;
static unsigned int fdc_calibr_count;
static unsigned int fdc_calibr_time;
static int fdc_status;
......@@ -89,14 +90,13 @@ void fdc_catch_stray_interrupts(int count)
{
unsigned long flags;
save_flags(flags);
cli();
spin_lock_irqsave(&fdc_io_lock, flags);
if (count == 0) {
ft_expected_stray_interrupts = 0;
} else {
ft_expected_stray_interrupts += count;
}
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
}
/* Wait during a timeout period for a given FDC status.
......@@ -194,8 +194,7 @@ int fdc_command(const __u8 * cmd_data, int cmd_len)
TRACE_FUN(ft_t_any);
fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
save_flags(flags);
cli();
spin_lock_irqsave(&fdc_io_lock, flags);
if (!in_interrupt())
/* Yes, I know, too much comments inside this function
* ...
......@@ -242,12 +241,11 @@ int fdc_command(const __u8 * cmd_data, int cmd_len)
}
fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
save_flags(flags);
cli();
spin_lock_irqsave(&fdc_io_lock, flags);
}
fdc_status = inb(fdc.msr);
if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_IN_READY) {
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
TRACE_ABORT(-EBUSY, ft_t_err, "fdc not ready");
}
fdc_mode = *cmd_data; /* used by isr */
......@@ -289,7 +287,7 @@ int fdc_command(const __u8 * cmd_data, int cmd_len)
last_time = ftape_timestamp();
}
#endif
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
TRACE_EXIT result;
}
......@@ -305,15 +303,14 @@ int fdc_result(__u8 * res_data, int res_len)
int retry = 0;
TRACE_FUN(ft_t_any);
save_flags(flags);
cli();
spin_lock_irqsave(&fdc_io_lock, flags);
fdc_status = inb(fdc.msr);
if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_OUT_READY) {
TRACE(ft_t_err, "fdc not ready");
result = -EBUSY;
} else while (count) {
if (!(fdc_status & FDC_BUSY)) {
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
TRACE_ABORT(-EIO, ft_t_err, "premature end of result phase");
}
result = fdc_read(res_data);
......@@ -336,7 +333,7 @@ int fdc_result(__u8 * res_data, int res_len)
++res_data;
}
}
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
fdc_usec_wait(FT_RQM_DELAY); /* allow FDC to negate BSY */
TRACE_EXIT result;
}
......@@ -609,8 +606,7 @@ void fdc_reset(void)
unsigned long flags;
TRACE_FUN(ft_t_any);
save_flags(flags);
cli();
spin_lock_irqsave(&fdc_io_lock, flags);
fdc_dor_reset(1); /* keep unit selected */
......@@ -629,7 +625,7 @@ void fdc_reset(void)
*/
fdc_update_dsr(); /* restore data rate and precomp */
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
/*
* Wait for first polling cycle to complete
......@@ -928,8 +924,7 @@ int fdc_setup_formatting(buffer_struct * buff)
*/
TRACE(ft_t_fdc_dma,
"phys. addr. = %lx", virt_to_bus((void*) buff->ptr));
save_flags(flags);
cli(); /* could be called from ISR ! */
spin_lock_irqsave(&fdc_io_lock, flags);
fdc_setup_dma(DMA_MODE_WRITE, buff->ptr, FT_SECTORS_PER_SEGMENT * 4);
/* Issue FDC command to start reading/writing.
*/
......@@ -937,7 +932,7 @@ int fdc_setup_formatting(buffer_struct * buff)
out[4] = buff->gap3;
TRACE_CATCH(fdc_setup_error = fdc_command(out, sizeof(out)),
restore_flags(flags); fdc_mode = fdc_idle);
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
TRACE_EXIT 0;
}
......@@ -977,11 +972,10 @@ int fdc_setup_read_write(buffer_struct * buff, __u8 operation)
break;
default:
TRACE_ABORT(-EIO,
ft_t_bug, "bug: illegal operation parameter");
ft_t_bug, "bug: invalid operation parameter");
}
TRACE(ft_t_fdc_dma, "phys. addr. = %lx",virt_to_bus((void*)buff->ptr));
save_flags(flags);
cli(); /* could be called from ISR ! */
spin_lock_irqsave(&fdc_io_lock, flags);
if (operation != FDC_VERIFY) {
fdc_setup_dma(dma_mode, buff->ptr,
FT_SECTOR_SIZE * buff->sector_count);
......@@ -999,7 +993,7 @@ int fdc_setup_read_write(buffer_struct * buff, __u8 operation)
out[8] = 0xff; /* No limit to transfer size. */
TRACE(ft_t_fdc_dma, "C: 0x%02x, H: 0x%02x, R: 0x%02x, cnt: 0x%02x",
out[2], out[3], out[4], out[6] - out[4] + 1);
restore_flags(flags);
spin_unlock_irqrestore(&fdc_io_lock, flags);
TRACE_CATCH(fdc_setup_error = fdc_command(out, 9),fdc_mode = fdc_idle);
TRACE_EXIT 0;
}
......
drivers/char/ftape/lowlevel/ftape-calibr.c
View file @ dce5ee27
......@@ -49,6 +49,8 @@
static unsigned long ps_per_cycle = 0;
#endif
static spinlock_t calibr_lock;
/*
* Note: On Intel PCs, the clock ticks at 100 Hz (HZ==100) which is
* too slow for certain timeouts (and that clock doesn't even tick
......@@ -75,13 +77,12 @@ unsigned int ftape_timestamp(void)
__u16 lo;
__u16 hi;
save_flags(flags);
cli();
spin_lock_irqsave(&calibr_lock, flags);
outb_p(0x00, 0x43); /* latch the count ASAP */
lo = inb_p(0x40); /* read the latched count */
lo |= inb(0x40) << 8;
hi = jiffies;
restore_flags(flags);
spin_unlock_irqrestore(&calibr_lock, flags);
return ((hi + 1) * (unsigned int) LATCH) - lo; /* downcounter ! */
#endif
}
......@@ -94,12 +95,11 @@ static unsigned int short_ftape_timestamp(void)
unsigned int count;
unsigned long flags;
save_flags(flags);
cli();
spin_lock_irqsave(&calibr_lock, flags);
outb_p(0x00, 0x43); /* latch the count ASAP */
count = inb_p(0x40); /* read the latched count */
count |= inb(0x40) << 8;
restore_flags(flags);
spin_unlock_irqrestore(&calibr_lock, flags);
return (LATCH - count); /* normal: downcounter */
#endif
}
......@@ -150,14 +150,13 @@ static void time_inb(void)
int status;
TRACE_FUN(ft_t_any);
save_flags(flags);
cli();
spin_lock_irqsave(&calibr_lock, flags);
t0 = short_ftape_timestamp();
for (i = 0; i < 1000; ++i) {
status = inb(fdc.msr);
}
t1 = short_ftape_timestamp();
restore_flags(flags);
spin_unlock_irqrestore(&calibr_lock, flags);
TRACE(ft_t_info, "inb() duration: %d nsec", ftape_timediff(t0, t1));
TRACE_EXIT;
}
......@@ -241,8 +240,7 @@ void ftape_calibrate(char *name,
*calibr_count =
*calibr_time = count; /* set TC to 1 */
save_flags(flags);
cli();
spin_lock_irqsave(&calibr_lock, flags);
fun(0); /* dummy, get code into cache */
t0 = short_ftape_timestamp();
fun(0); /* overhead + one test */
......@@ -252,7 +250,7 @@ void ftape_calibrate(char *name,
fun(count); /* overhead + count tests */
t1 = short_ftape_timestamp();
multiple = diff(t0, t1);
restore_flags(flags);
spin_unlock_irqrestore(&calibr_lock, flags);
time = ftape_timediff(0, multiple - once);
tc = (1000 * time) / (count - 1);
TRACE(ft_t_any, "once:%3d us,%6d times:%6d us, TC:%5d ns",
......
drivers/char/ftape/lowlevel/ftape-format.c
View file @ dce5ee27
......@@ -44,6 +44,8 @@
#define FT_FMT_SEGS_PER_BUF (FT_BUFF_SIZE/(4*FT_SECTORS_PER_SEGMENT))
#endif
static spinlock_t ftape_format_lock;
/*
* first segment of the new buffer
*/
......@@ -129,9 +131,9 @@ int ftape_format_track(const unsigned int track, const __u8 gap3)
head->status = formatting;
TRACE_CATCH(ftape_seek_head_to_track(track),);
TRACE_CATCH(ftape_command(QIC_LOGICAL_FORWARD),);
save_flags(flags); cli();
spin_lock_irqsave(&ftape_format_lock, flags);
TRACE_CATCH(fdc_setup_formatting(head), restore_flags(flags));
restore_flags(flags);
spin_unlock_irqrestore(&ftape_format_lock, flags);
TRACE_EXIT 0;
}
......
drivers/char/ftape/zftape/zftape-init.c
View file @ dce5ee27
......@@ -118,7 +118,7 @@ static int zft_open(struct inode *ino, struct file *filep)
>
FTAPE_SEL_D) {
clear_bit(0,&busy_flag);
TRACE_ABORT(-ENXIO, ft_t_err, "failed: illegal unit nr");
TRACE_ABORT(-ENXIO, ft_t_err, "failed: invalid unit nr");
}
orig_sigmask = current->blocked;
sigfillset(&current->blocked);
......
drivers/char/ip2.c
View file @ dce5ee27
......@@ -38,16 +38,14 @@ static int irq[IP2_MAX_BOARDS] = { -1, -1, -1, -1 };
static int poll_only = 0;
# if LINUX_VERSION_CODE >= KERNEL_VERSION(2,1,0)
MODULE_AUTHOR("Doug McNash");
MODULE_DESCRIPTION("Computone IntelliPort Plus Driver");
MODULE_PARM(irq,"1-"__MODULE_STRING(IP2_MAX_BOARDS) "i");
MODULE_PARM_DESC(irq,"Interrupts for IntelliPort Cards");
MODULE_PARM(io,"1-"__MODULE_STRING(IP2_MAX_BOARDS) "i");
MODULE_PARM_DESC(io,"I/O ports for IntelliPort Cards");
MODULE_PARM(poll_only,"1i");
MODULE_PARM_DESC(poll_only,"Do not use card interrupts");
# endif /* LINUX_VERSION */
MODULE_AUTHOR("Doug McNash");
MODULE_DESCRIPTION("Computone IntelliPort Plus Driver");
MODULE_PARM(irq,"1-"__MODULE_STRING(IP2_MAX_BOARDS) "i");
MODULE_PARM_DESC(irq,"Interrupts for IntelliPort Cards");
MODULE_PARM(io,"1-"__MODULE_STRING(IP2_MAX_BOARDS) "i");
MODULE_PARM_DESC(io,"I/O ports for IntelliPort Cards");
MODULE_PARM(poll_only,"1i");
MODULE_PARM_DESC(poll_only,"Do not use card interrupts");
//======================================================================
......
drivers/char/ip2/i2lib.c
View file @ dce5ee27
......@@ -1089,7 +1089,7 @@ i2Output(i2ChanStrPtr pCh, const char *pSource, int count, int user )
// Move the data
if ( user ) {
COPY_FROM_USER(rc, (char*)(DATA_OF(pInsert)), pSource,
rc = copy_from_user((char*)(DATA_OF(pInsert)), pSource,
amountToMove );
} else {
memcpy( (char*)(DATA_OF(pInsert)), pSource, amountToMove );
......
drivers/char/ip2/i2os.h
View file @ dce5ee27
......@@ -19,8 +19,6 @@
#ifndef I2OS_H /* To prevent multiple includes */
#define I2OS_H 1
#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
//-------------------------------------------------
// Required Includes
//-------------------------------------------------
......@@ -46,22 +44,6 @@
// Interrupt control
//--------------------------------------------
#if LINUX_VERSION_CODE < 0x00020100
typedef int spinlock_t;
#define spin_lock_init()
#define spin_lock(a)
#define spin_unlock(a)
#define spin_lock_irqsave(a,b) {save_flags((b));cli();}
#define spin_unlock_irqrestore(a,b) {restore_flags((b));}
#define write_lock_irqsave(a,b) spin_lock_irqsave(a,b)
#define write_unlock_irqrestore(a,b) spin_unlock_irqrestore(a,b)
#define read_lock_irqsave(a,b) spin_lock_irqsave(a,b)
#define read_unlock_irqrestore(a,b) spin_unlock_irqrestore(a,b)
#endif
//#define SAVE_AND_DISABLE_INTS(a,b) spin_lock_irqsave(a,b)
//#define RESTORE_INTS(a,b) spin_unlock_irqrestore(a,b)
#define LOCK_INIT(a) rwlock_init(a)
#define SAVE_AND_DISABLE_INTS(a,b) { \
......
drivers/char/ip2main.c
View file @ dce5ee27
This diff is collapsed.
drivers/char/watchdog/acquirewdt.c
View file @ dce5ee27
......@@ -143,7 +143,7 @@ static int acq_open(struct inode *inode, struct file *file)
return -EBUSY;
}
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
/* Activate */
acq_is_open=1;
......
drivers/char/watchdog/i810-tco.c
View file @ dce5ee27
......@@ -25,7 +25,8 @@
* 82801AA & 82801AB chip : document number 290655-003, 290677-004,
* 82801BA & 82801BAM chip : document number 290687-002, 298242-005,
* 82801CA & 82801CAM chip : document number 290716-001, 290718-001,
* 82801DB & 82801E chip : document number 290744-001, 273599-001
* 82801DB & 82801E chip : document number 290744-001, 273599-001,
* 82801EB & 82801ER chip : document number 252516-001
*
* 20000710 Nils Faerber
* Initial Version 0.01
......@@ -42,7 +43,9 @@
* clean up ioctls (WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS and
* WDIOC_SETOPTIONS), made i810tco_getdevice __init,
* removed boot_status, removed tco_timer_read,
* added support for 82801DB and 82801E chipset, general cleanup.
* added support for 82801DB and 82801E chipset,
* added support for 82801EB and 8280ER chipset,
* general cleanup.
*/
#include <linux/module.h>
......@@ -307,6 +310,7 @@ static struct pci_device_id i810tco_pci_tbl[] __initdata = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, },
};
MODULE_DEVICE_TABLE (pci, i810tco_pci_tbl);
......
drivers/char/watchdog/i810-tco.h
View file @ dce5ee27
/*
* i810-tco 0.05: TCO timer driver for i8xx chipsets
* i810-tco: TCO timer driver for i8xx chipsets
*
* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights Reserved.
* http://www.kernelconcepts.de
......
drivers/char/watchdog/ib700wdt.c
View file @ dce5ee27
......@@ -230,7 +230,7 @@ ibwdt_open(struct inode *inode, struct file *file)
return -EBUSY;
}
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
/* Activate */
ibwdt_is_open = 1;
......
drivers/char/watchdog/indydog.c
View file @ dce5ee27
......@@ -54,7 +54,7 @@ static int indydog_open(struct inode *inode, struct file *file)
return -EBUSY;
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
/*
* Activate timer
......
drivers/char/watchdog/machzwd.c
View file @ dce5ee27
......@@ -392,7 +392,7 @@ static int zf_open(struct inode *inode, struct file *file)
}
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
zf_is_open = 1;
......
drivers/char/watchdog/pcwd.c
View file @ dce5ee27
......@@ -431,7 +431,7 @@ static int pcwd_open(struct inode *ino, struct file *filep)
atomic_inc( &open_allowed );
return -EBUSY;
}
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
/* Enable the port */
if (revision == PCWD_REVISION_C) {
spin_lock(&io_lock);
......
drivers/char/watchdog/sbc60xxwdt.c
View file @ dce5ee27
......@@ -207,9 +207,8 @@ static int fop_open(struct inode * inode, struct file * file)
/* Just in case we're already talking to someone... */
if(wdt_is_open)
return -EBUSY;
if (nowayout) {
MOD_INC_USE_COUNT;
}
if (nowayout)
__module_get(THIS_MODULE);
/* Good, fire up the show */
wdt_is_open = 1;
wdt_startup();
......
drivers/char/watchdog/sc520_wdt.c
View file @ dce5ee27
......@@ -231,7 +231,7 @@ static int fop_open(struct inode * inode, struct file * file)
/* Good, fire up the show */
wdt_startup();
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
return 0;
default:
......
drivers/char/watchdog/shwdt.c
View file @ dce5ee27
......@@ -175,7 +175,7 @@ static int sh_wdt_open(struct inode *inode, struct file *file)
if (test_and_set_bit(0, &shwdt_is_open))
return -EBUSY;
if (nowayout)
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
sh_wdt_start();
......
drivers/char/watchdog/softdog.c
View file @ dce5ee27
......@@ -104,9 +104,8 @@ static int softdog_open(struct inode *inode, struct file *file)
{
if(test_and_set_bit(0, &timer_alive))
return -EBUSY;
if (nowayout) {
MOD_INC_USE_COUNT;
}
if (nowayout)
__module_get(THIS_MODULE);
/*
* Activate timer
*/
......
drivers/char/watchdog/wdt977.c
View file @ dce5ee27
......@@ -99,7 +99,7 @@ static int wdt977_open(struct inode *inode, struct file *file)
if (nowayout)
{
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
/* do not permit disabling the watchdog by writing 0 to reg. 0xF2 */
if (!timeoutM) timeoutM = DEFAULT_TIMEOUT;
......
drivers/char/watchdog/wdt_pci.c
View file @ dce5ee27
......@@ -367,7 +367,7 @@ static int wdtpci_open(struct inode *inode, struct file *file)
return -EBUSY;
if (nowayout) {
MOD_INC_USE_COUNT;
__module_get(THIS_MODULE);
}
/*
* Activate
......
drivers/ide/Kconfig
View file @ dce5ee27
......@@ -521,7 +521,7 @@ config BLK_DEV_ALI15X3
If you say Y here, you also need to say Y to "Use DMA by default
when available", above. Please read the comments at the top of
<file:drivers/ide/alim15x3.c>.
<file:drivers/ide/pci/alim15x3.c>.
If unsure, say N.
......@@ -608,7 +608,7 @@ config HPT34X_AUTODMA
depends on BLK_DEV_HPT34X && IDEDMA_PCI_WIP
help
This is a dangerous thing to attempt currently! Please read the
comments at the top of <file:drivers/ide/hpt34x.c>. If you say Y
comments at the top of <file:drivers/ide/pci/hpt34x.c>. If you say Y
here, then say Y to "Use DMA by default when available" as well.
If unsure, say N.
......@@ -670,14 +670,14 @@ config BLK_DEV_NS87415
This driver adds detection and support for the NS87415 chip
(used in SPARC64, among others).
Please read the comments at the top of <file:drivers/ide/ns87415.c>.
Please read the comments at the top of <file:drivers/ide/pci/ns87415.c>.
config BLK_DEV_OPTI621
tristate "OPTi 82C621 chipset enhanced support (EXPERIMENTAL)"
depends on PCI && BLK_DEV_IDEPCI && EXPERIMENTAL
help
This is a driver for the OPTi 82C621 EIDE controller.
Please read the comments at the top of <file:drivers/ide/opti621.c>.
Please read the comments at the top of <file:drivers/ide/pci/opti621.c>.
config BLK_DEV_PDC202XX_OLD
tristate "PROMISE PDC202{46|62|65|67} support"
......@@ -696,7 +696,7 @@ config PDC202XX_BURST
when the PDC20265 BIOS has been disabled (for faster boot up).
Please read the comments at the top of
<file:drivers/ide/pdc202xx.c>.
<file:drivers/ide/pci/pdc202xx_old.c>.
If unsure, say N.
......@@ -754,7 +754,7 @@ config BLK_DEV_SIS5513
If you say Y here, you need to say Y to "Use DMA by default when
available" as well.
Please read the comments at the top of <file:drivers/ide/sis5513.c>.
Please read the comments at the top of <file:drivers/ide/pci/sis5513.c>.
config BLK_DEV_SLC90E66
tristate "SLC90E66 chipset support"
......@@ -770,7 +770,7 @@ config BLK_DEV_SLC90E66
available" as well.
Please read the comments at the top of
drivers/ide/slc90e66.c.
drivers/ide/pci/slc90e66.c.
config BLK_DEV_TRM290
tristate "Tekram TRM290 chipset support"
......@@ -779,7 +779,7 @@ config BLK_DEV_TRM290
This driver adds support for bus master DMA transfers
using the Tekram TRM290 PCI IDE chip. Volunteers are
needed for further tweaking and development.
Please read the comments at the top of <file:drivers/ide/trm290.c>.
Please read the comments at the top of <file:drivers/ide/pci/trm290.c>.
config BLK_DEV_VIA82CXXX
tristate "VIA82CXXX chipset support"
......@@ -1010,7 +1010,7 @@ config BLK_DEV_ALI14XX
boot parameter. It enables support for the secondary IDE interface
of the ALI M1439/1443/1445/1487/1489 chipsets, and permits faster
I/O speeds to be set as well. See the files
<file:Documentation/ide.txt> and <file:drivers/ide/ali14xx.c> for
<file:Documentation/ide.txt> and <file:drivers/ide/legacy/ali14xx.c> for
more info.
config BLK_DEV_DTC2278
......@@ -1021,7 +1021,7 @@ config BLK_DEV_DTC2278
boot parameter. It enables support for the secondary IDE interface
of the DTC-2278 card, and permits faster I/O speeds to be set as
well. See the <file:Documentation/ide.txt> and
<file:drivers/ide/dtc2278.c> files for more info.
<file:drivers/ide/legacy/dtc2278.c> files for more info.
config BLK_DEV_HT6560B
tristate "Holtek HT6560B support"
......@@ -1031,7 +1031,7 @@ config BLK_DEV_HT6560B
boot parameter. It enables support for the secondary IDE interface
of the Holtek card, and permits faster I/O speeds to be set as well.
See the <file:Documentation/ide.txt> and
<file:drivers/ide/ht6560b.c> files for more info.
<file:drivers/ide/legacy/ht6560b.c> files for more info.
config BLK_DEV_PDC4030
tristate "PROMISE DC4030 support (EXPERIMENTAL)"
......@@ -1044,7 +1044,7 @@ config BLK_DEV_PDC4030
supported (and probably never will be since I don't think the cards
support them). This driver is enabled at runtime using the "ide0=dc4030"
or "ide1=dc4030" kernel boot parameter. See the
<file:drivers/ide/pdc4030.c> file for more info.
<file:drivers/ide/legacy/pdc4030.c> file for more info.
config BLK_DEV_QD65XX
tristate "QDI QD65xx support"
......@@ -1052,7 +1052,7 @@ config BLK_DEV_QD65XX
help
This driver is enabled at runtime using the "ide0=qd65xx" kernel
boot parameter. It permits faster I/O speeds to be set. See the
<file:Documentation/ide.txt> and <file:drivers/ide/qd65xx.c> for
<file:Documentation/ide.txt> and <file:drivers/ide/legacy/qd65xx.c> for
more info.
config BLK_DEV_UMC8672
......@@ -1063,7 +1063,7 @@ config BLK_DEV_UMC8672
boot parameter. It enables support for the secondary IDE interface
of the UMC-8672, and permits faster I/O speeds to be set as well.
See the files <file:Documentation/ide.txt> and
<file:drivers/ide/umc8672.c> for more info.
<file:drivers/ide/legacy/umc8672.c> for more info.
config BLK_DEV_HD_ONLY
bool "Old hard disk (MFM/RLL/IDE) driver"
......@@ -1132,7 +1132,7 @@ config BLK_DEV_PDC202XX
available" as well.
Please read the comments at the top of
<file:drivers/ide/pdc202xx.c>.
<file:drivers/ide/pdc202xx_old.c>.
If unsure, say N.
......
drivers/md/Kconfig
View file @ dce5ee27
......@@ -145,5 +145,12 @@ config BLK_DEV_DM
If unsure, say N.
config DM_IOCTL_V4
bool "ioctl interface version 4"
depends on BLK_DEV_DM
---help---
Recent tools use a new version of the ioctl interface, only
select this option if you intend using such tools.
endmenu
drivers/md/dm-ioctl-v1.c 0 → 100644
View file @ dce5ee27
This diff is collapsed.
drivers/md/dm-ioctl-v4.c 0 → 100644
View file @ dce5ee27
This diff is collapsed.
drivers/md/dm-ioctl.c
View file @ dce5ee27
This diff is collapsed.
drivers/md/dm-table.c
View file @ dce5ee27
......@@ -48,11 +48,9 @@ struct dm_table {
*/
struct io_restrictions limits;
/*
* A waitqueue for processes waiting for something
* interesting to happen to this table.
*/
wait_queue_head_t eventq;
/* events get handed up using this callback */
void (*event_fn)(void *);
void *event_context;
};
/*
......@@ -222,7 +220,6 @@ int dm_table_create(struct dm_table **result, int mode)
return -ENOMEM;
}
init_waitqueue_head(&t->eventq);
t->mode = mode;
*result = t;
return 0;
......@@ -243,9 +240,6 @@ void table_destroy(struct dm_table *t)
{
unsigned int i;
/* destroying the table counts as an event */
dm_table_event(t);
/* free the indexes (see dm_table_complete) */
if (t->depth >= 2)
vfree(t->index[t->depth - 2]);
......@@ -694,9 +688,22 @@ int dm_table_complete(struct dm_table *t)
return r;
}
static spinlock_t _event_lock = SPIN_LOCK_UNLOCKED;
void dm_table_event_callback(struct dm_table *t,
void (*fn)(void *), void *context)
{
spin_lock_irq(&_event_lock);
t->event_fn = fn;
t->event_context = context;
spin_unlock_irq(&_event_lock);
}
void dm_table_event(struct dm_table *t)
{
wake_up_interruptible(&t->eventq);
spin_lock(&_event_lock);
if (t->event_fn)
t->event_fn(t->event_context);
spin_unlock(&_event_lock);
}
sector_t dm_table_get_size(struct dm_table *t)
......@@ -761,11 +768,6 @@ int dm_table_get_mode(struct dm_table *t)
return t->mode;
}
void dm_table_add_wait_queue(struct dm_table *t, wait_queue_t *wq)
{
add_wait_queue(&t->eventq, wq);
}
void dm_table_suspend_targets(struct dm_table *t)
{
int i;
......
drivers/md/dm.c
View file @ dce5ee27
......@@ -62,6 +62,12 @@ struct mapped_device {
* io objects are allocated from here.
*/
mempool_t *io_pool;
/*
* Event handling.
*/
uint32_t event_nr;
wait_queue_head_t eventq;
};
#define MIN_IOS 256
......@@ -509,6 +515,11 @@ static int dm_request(request_queue_t *q, struct bio *bio)
down_read(&md->lock);
}
if (!md->map) {
bio_io_error(bio, bio->bi_size);
return 0;
}
__split_bio(md, bio);
up_read(&md->lock);
return 0;
......@@ -618,6 +629,8 @@ static struct mapped_device *alloc_dev(unsigned int minor, int persistent)
atomic_set(&md->pending, 0);
init_waitqueue_head(&md->wait);
init_waitqueue_head(&md->eventq);
return md;
}
......@@ -633,6 +646,16 @@ static void free_dev(struct mapped_device *md)
/*
* Bind a table to the device.
*/
static void event_callback(void *context)
{
struct mapped_device *md = (struct mapped_device *) context;
down_write(&md->lock);
md->event_nr++;
wake_up_interruptible(&md->eventq);
up_write(&md->lock);
}
static int __bind(struct mapped_device *md, struct dm_table *t)
{
request_queue_t *q = &md->queue;
......@@ -644,6 +667,8 @@ static int __bind(struct mapped_device *md, struct dm_table *t)
if (size == 0)
return 0;
dm_table_event_callback(md->map, event_callback, md);
dm_table_get(t);
dm_table_set_restrictions(t, q);
return 0;
......@@ -651,6 +676,10 @@ static int __bind(struct mapped_device *md, struct dm_table *t)
static void __unbind(struct mapped_device *md)
{
if (!md->map)
return;
dm_table_event_callback(md->map, NULL, NULL);
dm_table_put(md->map);
md->map = NULL;
set_capacity(md->disk, 0);
......@@ -660,35 +689,26 @@ static void __unbind(struct mapped_device *md)
* Constructor for a new device.
*/
static int create_aux(unsigned int minor, int persistent,
struct dm_table *table, struct mapped_device **result)
struct mapped_device **result)
{
int r;
struct mapped_device *md;
md = alloc_dev(minor, persistent);
if (!md)
return -ENXIO;
r = __bind(md, table);
if (r) {
free_dev(md);
return r;
}
dm_table_resume_targets(md->map);
*result = md;
return 0;
}
int dm_create(struct dm_table *table, struct mapped_device **result)
int dm_create(struct mapped_device **result)
{
return create_aux(0, 0, table, result);
return create_aux(0, 0, result);
}
int dm_create_with_minor(unsigned int minor,
struct dm_table *table, struct mapped_device **result)
int dm_create_with_minor(unsigned int minor, struct mapped_device **result)
{
return create_aux(minor, 1, table, result);
return create_aux(minor, 1, result);
}
void dm_get(struct mapped_device *md)
......@@ -699,7 +719,7 @@ void dm_get(struct mapped_device *md)
void dm_put(struct mapped_device *md)
{
if (atomic_dec_and_test(&md->holders)) {
if (!test_bit(DMF_SUSPENDED, &md->flags))
if (!test_bit(DMF_SUSPENDED, &md->flags) && md->map)
dm_table_suspend_targets(md->map);
__unbind(md);
free_dev(md);
......@@ -789,6 +809,7 @@ int dm_suspend(struct mapped_device *md)
down_write(&md->lock);
remove_wait_queue(&md->wait, &wait);
set_bit(DMF_SUSPENDED, &md->flags);
if (md->map)
dm_table_suspend_targets(md->map);
up_write(&md->lock);
......@@ -800,7 +821,8 @@ int dm_resume(struct mapped_device *md)
struct deferred_io *def;
down_write(&md->lock);
if (!test_bit(DMF_SUSPENDED, &md->flags) ||
if (!md->map ||
!test_bit(DMF_SUSPENDED, &md->flags) ||
!dm_table_get_size(md->map)) {
up_write(&md->lock);
return -EINVAL;
......@@ -819,6 +841,42 @@ int dm_resume(struct mapped_device *md)
return 0;
}
/*-----------------------------------------------------------------
* Event notification.
*---------------------------------------------------------------*/
uint32_t dm_get_event_nr(struct mapped_device *md)
{
uint32_t r;
down_read(&md->lock);
r = md->event_nr;
up_read(&md->lock);
return r;
}
int dm_add_wait_queue(struct mapped_device *md, wait_queue_t *wq,
uint32_t event_nr)
{
down_write(&md->lock);
if (event_nr != md->event_nr) {
up_write(&md->lock);
return 1;
}
add_wait_queue(&md->eventq, wq);
up_write(&md->lock);
return 0;
}
void dm_remove_wait_queue(struct mapped_device *md, wait_queue_t *wq)
{
down_write(&md->lock);
remove_wait_queue(&md->eventq, wq);
up_write(&md->lock);
}
/*
* The gendisk is only valid as long as you have a reference
* count on 'md'.
......@@ -834,6 +892,7 @@ struct dm_table *dm_get_table(struct mapped_device *md)
down_read(&md->lock);
t = md->map;
if (t)
dm_table_get(t);
up_read(&md->lock);
......
drivers/md/dm.h
View file @ dce5ee27
......@@ -51,9 +51,8 @@ struct mapped_device;
* Functions for manipulating a struct mapped_device.
* Drop the reference with dm_put when you finish with the object.
*---------------------------------------------------------------*/
int dm_create(struct dm_table *table, struct mapped_device **md);
int dm_create_with_minor(unsigned int minor, struct dm_table *table,
struct mapped_device **md);
int dm_create(struct mapped_device **md);
int dm_create_with_minor(unsigned int minor, struct mapped_device **md);
/*
* Reference counting for md.
......@@ -78,6 +77,14 @@ int dm_swap_table(struct mapped_device *md, struct dm_table *t);
*/
struct dm_table *dm_get_table(struct mapped_device *md);
/*
* Event functions.
*/
uint32_t dm_get_event_nr(struct mapped_device *md);
int dm_add_wait_queue(struct mapped_device *md, wait_queue_t *wq,
uint32_t event_nr);
void dm_remove_wait_queue(struct mapped_device *md, wait_queue_t *wq);
/*
* Info functions.
*/
......@@ -96,6 +103,8 @@ void dm_table_put(struct dm_table *t);
int dm_table_add_target(struct dm_table *t, const char *type,
sector_t start, sector_t len, char *params);
int dm_table_complete(struct dm_table *t);
void dm_table_event_callback(struct dm_table *t,
void (*fn)(void *), void *context);
void dm_table_event(struct dm_table *t);
sector_t dm_table_get_size(struct dm_table *t);
struct dm_target *dm_table_get_target(struct dm_table *t, unsigned int index);
......@@ -104,7 +113,6 @@ void dm_table_set_restrictions(struct dm_table *t, struct request_queue *q);
unsigned int dm_table_get_num_targets(struct dm_table *t);
struct list_head *dm_table_get_devices(struct dm_table *t);
int dm_table_get_mode(struct dm_table *t);
void dm_table_add_wait_queue(struct dm_table *t, wait_queue_t *wq);
void dm_table_suspend_targets(struct dm_table *t);
void dm_table_resume_targets(struct dm_table *t);
......
drivers/net/Kconfig
View file @ dce5ee27
......@@ -1153,7 +1153,7 @@ config ZNET
config SEEQ8005
tristate "SEEQ8005 support (EXPERIMENTAL)"
depends on NET_ISA && OBSOLETE && EXPERIMENTAL
depends on NET_ISA && EXPERIMENTAL
help
This is a driver for the SEEQ 8005 network (Ethernet) card. If this
is for you, read the Ethernet-HOWTO, available from
......
drivers/net/ni65.c
View file @ dce5ee27
This diff is collapsed.
drivers/net/ni65.h
View file @ dce5ee27
......@@ -86,8 +86,7 @@
#define XMIT_UFLO 0x4000 /* Underflow (late memory) */
#define XMIT_BUFF 0x8000 /* Buffering error (no ENP) */
struct init_block
{
struct init_block {
unsigned short mode;
unsigned char eaddr[6];
unsigned char filter[8];
......@@ -97,13 +96,10 @@ struct init_block
u32 trp; /* transmit ring pointer (align 8) */
};
struct rmd /* Receive Message Descriptor */
{
union
{
struct rmd { /* Receive Message Descriptor */
union {
volatile u32 buffer;
struct
{
struct {
volatile unsigned char dummy[3];
volatile unsigned char status;
} s;
......@@ -112,13 +108,10 @@ struct rmd /* Receive Message Descriptor */
volatile unsigned short mlen;
};
struct tmd
{
union
{
struct tmd {
union {
volatile u32 buffer;
struct
{
struct {
volatile unsigned char dummy[3];
volatile unsigned char status;
} s;
......@@ -126,5 +119,3 @@ struct tmd
volatile unsigned short blen;
volatile unsigned short status2;
};
drivers/net/pcmcia/Kconfig
View file @ dce5ee27
......@@ -113,7 +113,7 @@ config PCMCIA_XIRC2PS
If unsure, say N.
config PCMCIA_AXNET
tristate "broken NS8390-cards support"
tristate "Asix AX88190 PCMCIA support"
depends on NET_PCMCIA && PCMCIA
---help---
Say Y here if you intend to attach an Asix AX88190-based PCMCIA
......
drivers/net/seeq8005.c
View file @ dce5ee27
......@@ -700,7 +700,8 @@ static void hardware_send_packet(struct net_device * dev, char *buf, int length)
* wait_for_buffer
*
* This routine waits for the SEEQ chip to assert that the FIFO is ready
* by checking for a window interrupt, and then clearing it
* by checking for a window interrupt, and then clearing it. This has to
* occur in the interrupt handler!
*/
inline void wait_for_buffer(struct net_device * dev)
{
......@@ -710,7 +711,7 @@ inline void wait_for_buffer(struct net_device * dev)
tmp = jiffies + HZ;
while ( ( ((status=inw(SEEQ_STATUS)) & SEEQSTAT_WINDOW_INT) != SEEQSTAT_WINDOW_INT) && time_before(jiffies, tmp))
mb();
cpu_relax();
if ( (status & SEEQSTAT_WINDOW_INT) == SEEQSTAT_WINDOW_INT)
outw( SEEQCMD_WINDOW_INT_ACK | (status & SEEQCMD_INT_MASK), SEEQ_CMD);
......
drivers/parport/parport_pc.c
View file @ dce5ee27
......@@ -94,7 +94,8 @@ static struct superio_struct { /* For Super-IO chips autodetection */
} superios[NR_SUPERIOS] __devinitdata = { {0,},};
static int user_specified __devinitdata = 0;
#if defined(CONFIG_PARPORT_PC_FIFO) || defined(CONFIG_PARPORT_PC_SUPERIO)
#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
(defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
static int verbose_probing;
#endif
static int registered_parport;
......@@ -3116,7 +3117,8 @@ MODULE_PARM_DESC(irq, "IRQ line");
MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
MODULE_PARM_DESC(dma, "DMA channel");
MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
#if defined(CONFIG_PARPORT_PC_FIFO) || defined(CONFIG_PARPORT_PC_SUPERIO)
#if defined(CONFIG_PARPORT_PC_SUPERIO) || \
(defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
MODULE_PARM(verbose_probing, "i");
#endif
......
drivers/pcmcia/ricoh.h
View file @ dce5ee27
......@@ -116,6 +116,8 @@
#define RL5C4XX_CMD_SHIFT 4
#define RL5C4XX_HOLD_MASK 0x1c00
#define RL5C4XX_HOLD_SHIFT 10
#define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
#define RL5C4XX_ZV_ENABLE 0x08
#ifdef __YENTA_H
......@@ -125,10 +127,41 @@
#define rl_mem(socket) ((socket)->private[3])
#define rl_config(socket) ((socket)->private[4])
static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
{
u8 reg;
struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
if (onoff)
/* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
reg |= RL5C4XX_ZV_ENABLE;
else
reg &= ~RL5C4XX_ZV_ENABLE;
config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
}
static void ricoh_set_zv(struct pcmcia_socket *sock)
{
struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
{
switch(socket->dev->device)
{
/* There may be more .. */
case PCI_DEVICE_ID_RICOH_RL5C478:
sock->zoom_video = ricoh_zoom_video;
break;
}
}
}
static int ricoh_init(struct pcmcia_socket *sock)
{
struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
yenta_init(sock);
ricoh_set_zv(sock);
config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
......
drivers/pcmcia/ti113x.h
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