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Commit de99befd authored by Ragavendra Nagraj's avatar Ragavendra Nagraj Committed by Greg Kroah-Hartman
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staging: sm750fb: Fixed no space and indent warns 

This patch fixes the no spaces and indent warnings identified by the
checkpath.pl script for the entire ddk750_chip.c file by using
appropriate tab spaces and indents accordingly.
Signed-off-by: default avatarRagavendra Nagraj <ragavendra.bn@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6a9df430
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Showing with 230 additions and 230 deletions
drivers/staging/sm750fb/ddk750_chip.c
View file @ de99befd
...@@ -20,22 +20,22 @@ logical_chip_type_t getChipType(void) ...@@ -20,22 +20,22 @@ logical_chip_type_t getChipType(void)
physicalID = devId750;//either 0x718 or 0x750 physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750; physicalRev = revId750;
if (physicalID == 0x718) if (physicalID == 0x718)
{ {
chip = SM718; chip = SM718;
} }
else if (physicalID == 0x750) else if (physicalID == 0x750)
{ {
chip = SM750; chip = SM750;
/* SM750 and SM750LE are different in their revision ID only. */ /* SM750 and SM750LE are different in their revision ID only. */
if (physicalRev == SM750LE_REVISION_ID){ if (physicalRev == SM750LE_REVISION_ID){
chip = SM750LE; chip = SM750LE;
} }
} }
else else
{ {
chip = SM_UNKNOWN; chip = SM_UNKNOWN;
} }
return chip; return chip;
} }
...@@ -43,63 +43,63 @@ logical_chip_type_t getChipType(void) ...@@ -43,63 +43,63 @@ logical_chip_type_t getChipType(void)
inline unsigned int twoToPowerOfx(unsigned long x) inline unsigned int twoToPowerOfx(unsigned long x)
{ {
unsigned long i; unsigned long i;
unsigned long result = 1; unsigned long result = 1;
for (i=1; i<=x; i++) for (i=1; i<=x; i++)
result *= 2; result *= 2;
return result; return result;
} }
inline unsigned int calcPLL(pll_value_t *pPLL) inline unsigned int calcPLL(pll_value_t *pPLL)
{ {
return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) / twoToPowerOfx(pPLL->POD)); return (pPLL->inputFreq * pPLL->M / pPLL->N / twoToPowerOfx(pPLL->OD) / twoToPowerOfx(pPLL->POD));
} }
unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL) unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
{ {
unsigned int ulPllReg = 0; unsigned int ulPllReg = 0;
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; pPLL->inputFreq = DEFAULT_INPUT_CLOCK;
pPLL->clockType = clockType; pPLL->clockType = clockType;
switch (clockType) switch (clockType)
{ {
case MXCLK_PLL: case MXCLK_PLL:
ulPllReg = PEEK32(MXCLK_PLL_CTRL); ulPllReg = PEEK32(MXCLK_PLL_CTRL);
break; break;
case PRIMARY_PLL: case PRIMARY_PLL:
ulPllReg = PEEK32(PANEL_PLL_CTRL); ulPllReg = PEEK32(PANEL_PLL_CTRL);
break; break;
case SECONDARY_PLL: case SECONDARY_PLL:
ulPllReg = PEEK32(CRT_PLL_CTRL); ulPllReg = PEEK32(CRT_PLL_CTRL);
break; break;
case VGA0_PLL: case VGA0_PLL:
ulPllReg = PEEK32(VGA_PLL0_CTRL); ulPllReg = PEEK32(VGA_PLL0_CTRL);
break; break;
case VGA1_PLL: case VGA1_PLL:
ulPllReg = PEEK32(VGA_PLL1_CTRL); ulPllReg = PEEK32(VGA_PLL1_CTRL);
break; break;
} }
pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M); pPLL->M = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, M);
pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N); pPLL->N = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, N);
pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD); pPLL->OD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, OD);
pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD); pPLL->POD = FIELD_GET(ulPllReg, PANEL_PLL_CTRL, POD);
return calcPLL(pPLL); return calcPLL(pPLL);
} }
unsigned int getChipClock(void) unsigned int getChipClock(void)
{ {
pll_value_t pll; pll_value_t pll;
#if 1 #if 1
if(getChipType() == SM750LE) if(getChipType() == SM750LE)
return MHz(130); return MHz(130);
#endif #endif
return getPllValue(MXCLK_PLL, &pll); return getPllValue(MXCLK_PLL, &pll);
} }
...@@ -110,75 +110,75 @@ unsigned int getChipClock(void) ...@@ -110,75 +110,75 @@ unsigned int getChipClock(void)
*/ */
void setChipClock(unsigned int frequency) void setChipClock(unsigned int frequency)
{ {
pll_value_t pll; pll_value_t pll;
unsigned int ulActualMxClk; unsigned int ulActualMxClk;
#if 1 #if 1
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
return; return;
#endif #endif
if (frequency != 0) if (frequency != 0)
{ {
/* /*
* Set up PLL, a structure to hold the value to be set in clocks. * Set up PLL, a structure to hold the value to be set in clocks.
*/ */
pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
pll.clockType = MXCLK_PLL; pll.clockType = MXCLK_PLL;
/* /*
* Call calcPllValue() to fill up the other fields for PLL structure. * Call calcPllValue() to fill up the other fields for PLL structure.
* Sometime, the chip cannot set up the exact clock required by User. * Sometime, the chip cannot set up the exact clock required by User.
* Return value from calcPllValue() gives the actual possible clock. * Return value from calcPllValue() gives the actual possible clock.
*/ */
ulActualMxClk = calcPllValue(frequency, &pll); ulActualMxClk = calcPllValue(frequency, &pll);
/* Master Clock Control: MXCLK_PLL */ /* Master Clock Control: MXCLK_PLL */
POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll)); POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll));
} }
} }
void setMemoryClock(unsigned int frequency) void setMemoryClock(unsigned int frequency)
{ {
unsigned int ulReg, divisor; unsigned int ulReg, divisor;
#if 1 #if 1
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
return; return;
#endif #endif
if (frequency != 0) if (frequency != 0)
{ {
/* Set the frequency to the maximum frequency that the DDR Memory can take /* Set the frequency to the maximum frequency that the DDR Memory can take
which is 336MHz. */ which is 336MHz. */
if (frequency > MHz(336)) if (frequency > MHz(336))
frequency = MHz(336); frequency = MHz(336);
/* Calculate the divisor */ /* Calculate the divisor */
divisor = (unsigned int) roundedDiv(getChipClock(), frequency); divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
/* Set the corresponding divisor in the register. */ /* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE); ulReg = PEEK32(CURRENT_GATE);
switch(divisor) switch(divisor)
{ {
default: default:
case 1: case 1:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1); ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
break; break;
case 2: case 2:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2); ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2);
break; break;
case 3: case 3:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3); ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3);
break; break;
case 4: case 4:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4); ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4);
break; break;
} }
setCurrentGate(ulReg); setCurrentGate(ulReg);
} }
} }
...@@ -192,43 +192,43 @@ void setMemoryClock(unsigned int frequency) ...@@ -192,43 +192,43 @@ void setMemoryClock(unsigned int frequency)
*/ */
void setMasterClock(unsigned int frequency) void setMasterClock(unsigned int frequency)
{ {
unsigned int ulReg, divisor; unsigned int ulReg, divisor;
#if 1 #if 1
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
return; return;
#endif #endif
if (frequency != 0) if (frequency != 0)
{ {
/* Set the frequency to the maximum frequency that the SM750 engine can /* Set the frequency to the maximum frequency that the SM750 engine can
run, which is about 190 MHz. */ run, which is about 190 MHz. */
if (frequency > MHz(190)) if (frequency > MHz(190))
frequency = MHz(190); frequency = MHz(190);
/* Calculate the divisor */ /* Calculate the divisor */
divisor = (unsigned int) roundedDiv(getChipClock(), frequency); divisor = (unsigned int) roundedDiv(getChipClock(), frequency);
/* Set the corresponding divisor in the register. */ /* Set the corresponding divisor in the register. */
ulReg = PEEK32(CURRENT_GATE); ulReg = PEEK32(CURRENT_GATE);
switch(divisor) switch(divisor)
{ {
default: default:
case 3: case 3:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3); ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
break; break;
case 4: case 4:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4); ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
break; break;
case 6: case 6:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6); ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
break; break;
case 8: case 8:
ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8); ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
break; break;
} }
setCurrentGate(ulReg); setCurrentGate(ulReg);
} }
} }
...@@ -249,11 +249,11 @@ unsigned int ddk750_getVMSize(void) ...@@ -249,11 +249,11 @@ unsigned int ddk750_getVMSize(void)
/* get frame buffer size from GPIO */ /* get frame buffer size from GPIO */
reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE); reg = FIELD_GET(PEEK32(MISC_CTRL),MISC_CTRL,LOCALMEM_SIZE);
switch(reg){ switch(reg){
case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_8M: data = MB(8); break; /* 8 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_16M: data = MB(16); break; /* 16 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_32M: data = MB(32); break; /* 32 Mega byte */
case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_64M: data = MB(64); break; /* 64 Mega byte */
default: data = 0;break; default: data = 0;break;
} }
return data; return data;
...@@ -391,10 +391,10 @@ int ddk750_initHw(initchip_param_t * pInitParam) ...@@ -391,10 +391,10 @@ int ddk750_initHw(initchip_param_t * pInitParam)
unsigned int absDiff(unsigned int a, unsigned int b) unsigned int absDiff(unsigned int a, unsigned int b)
{ {
if ( a > b ) if ( a > b )
return(a - b); return(a - b);
else else
return(b - a); return(b - a);
} }
#endif #endif
...@@ -435,7 +435,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) ...@@ -435,7 +435,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
{3,0,3,8}, {3,0,3,8},
}; };
/* as sm750 register definition, N located in 2,15 and M located in 1,255 */ /* as sm750 register definition, N located in 2,15 and M located in 1,255 */
int N,M,X,d; int N,M,X,d;
int xcnt; int xcnt;
int miniDiff; int miniDiff;
...@@ -446,11 +446,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) ...@@ -446,11 +446,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
#if 1 #if 1
if (getChipType() == SM750LE) if (getChipType() == SM750LE)
{ {
/* SM750LE don't have prgrammable PLL and M/N values to work on. /* SM750LE don't have prgrammable PLL and M/N values to work on.
Just return the requested clock. */ Just return the requested clock. */
return request_orig; return request_orig;
} }
#endif #endif
ret = 0; ret = 0;
...@@ -487,7 +487,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) ...@@ -487,7 +487,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
{ {
unsigned int diff; unsigned int diff;
tmpClock = pll->inputFreq *M / N / X; tmpClock = pll->inputFreq *M / N / X;
diff = absDiff(tmpClock,request_orig); diff = absDiff(tmpClock,request_orig);
if(diff < miniDiff) if(diff < miniDiff)
{ {
pll->M = M; pll->M = M;
...@@ -510,104 +510,104 @@ unsigned int ulRequestClk, /* Required pixel clock in Hz unit */ ...@@ -510,104 +510,104 @@ unsigned int ulRequestClk, /* Required pixel clock in Hz unit */
pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
) )
{ {
unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower; unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;
unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */ unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */
unsigned int ret; unsigned int ret;
/* Init PLL structure to know states */ /* Init PLL structure to know states */
pPLL->M = 0; pPLL->M = 0;
pPLL->N = 0; pPLL->N = 0;
pPLL->OD = 0; pPLL->OD = 0;
pPLL->POD = 0; pPLL->POD = 0;
/* Sanity check: None at the moment */ /* Sanity check: None at the moment */
/* Convert everything in Khz range in order to avoid calculation overflow */ /* Convert everything in Khz range in order to avoid calculation overflow */
pPLL->inputFreq /= 1000; pPLL->inputFreq /= 1000;
ulRequestClk /= 1000; ulRequestClk /= 1000;
#ifndef VALIDATION_CHIP #ifndef VALIDATION_CHIP
/* The maximum of post divider is 8. */ /* The maximum of post divider is 8. */
for (POD=0; POD<=3; POD++) for (POD=0; POD<=3; POD++)
#endif #endif
{ {
#ifndef VALIDATION_CHIP #ifndef VALIDATION_CHIP
/* MXCLK_PLL does not have post divider. */ /* MXCLK_PLL does not have post divider. */
if ((POD > 0) && (pPLL->clockType == MXCLK_PLL)) if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))
break; break;
#endif #endif
/* Work out 2 to the power of POD */ /* Work out 2 to the power of POD */
podPower = twoToPowerOfx(POD); podPower = twoToPowerOfx(POD);
/* OD has only 2 bits [15:14] and its value must between 0 to 3 */ /* OD has only 2 bits [15:14] and its value must between 0 to 3 */
for (OD=0; OD<=3; OD++) for (OD=0; OD<=3; OD++)
{ {
/* Work out 2 to the power of OD */ /* Work out 2 to the power of OD */
odPower = twoToPowerOfx(OD); odPower = twoToPowerOfx(OD);
#ifdef VALIDATION_CHIP #ifdef VALIDATION_CHIP
if (odPower > 4) if (odPower > 4)
podPower = 4; podPower = 4;
else else
podPower = odPower; podPower = odPower;
#endif #endif
/* N has 4 bits [11:8] and its value must between 2 and 15. /* N has 4 bits [11:8] and its value must between 2 and 15.
The N == 1 will behave differently --> Result is not correct. */ The N == 1 will behave differently --> Result is not correct. */
for (N=2; N<=15; N++) for (N=2; N<=15; N++)
{ {
/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD) /* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
In the following steps, we try to work out a best M value given the others are known. In the following steps, we try to work out a best M value given the others are known.
To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy. To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
*/ */
M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq; M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;
M = roundedDiv(M, 1000); M = roundedDiv(M, 1000);
/* M field has only 8 bits, reject value bigger than 8 bits */ /* M field has only 8 bits, reject value bigger than 8 bits */
if (M < 256) if (M < 256)
{ {
/* Calculate the actual clock for a given M & N */ /* Calculate the actual clock for a given M & N */
pllClk = pPLL->inputFreq * M / N / odPower / podPower; pllClk = pPLL->inputFreq * M / N / odPower / podPower;
/* How much are we different from the requirement */ /* How much are we different from the requirement */
diff = absDiff(pllClk, ulRequestClk); diff = absDiff(pllClk, ulRequestClk);
if (diff < bestDiff) if (diff < bestDiff)
{ {
bestDiff = diff; bestDiff = diff;
/* Store M and N values */ /* Store M and N values */
pPLL->M = M; pPLL->M = M;
pPLL->N = N; pPLL->N = N;
pPLL->OD = OD; pPLL->OD = OD;
#ifdef VALIDATION_CHIP #ifdef VALIDATION_CHIP
if (OD > 2) if (OD > 2)
POD = 2; POD = 2;
else else
POD = OD; POD = OD;
#endif #endif
pPLL->POD = POD; pPLL->POD = POD;
} }
} }
} }
} }
} }
/* Restore input frequency from Khz to hz unit */ /* Restore input frequency from Khz to hz unit */
// pPLL->inputFreq *= 1000; // pPLL->inputFreq *= 1000;
ulRequestClk *= 1000; ulRequestClk *= 1000;
pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */ pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
/* Output debug information */ /* Output debug information */
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk)); //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk));
//DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD)); //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD));
/* Return actual frequency that the PLL can set */ /* Return actual frequency that the PLL can set */
ret = calcPLL(pPLL); ret = calcPLL(pPLL);
return ret; return ret;
} }
...@@ -616,22 +616,22 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ ...@@ -616,22 +616,22 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
unsigned int formatPllReg(pll_value_t *pPLL) unsigned int formatPllReg(pll_value_t *pPLL)
{ {
unsigned int ulPllReg = 0; unsigned int ulPllReg = 0;
/* Note that all PLL's have the same format. Here, we just use Panel PLL parameter /* Note that all PLL's have the same format. Here, we just use Panel PLL parameter
to work out the bit fields in the register. to work out the bit fields in the register.
On returning a 32 bit number, the value can be applied to any PLL in the calling function. On returning a 32 bit number, the value can be applied to any PLL in the calling function.
*/ */
ulPllReg = ulPllReg =
FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF) FIELD_SET( 0, PANEL_PLL_CTRL, BYPASS, OFF)
| FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON) | FIELD_SET( 0, PANEL_PLL_CTRL, POWER, ON)
| FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC) | FIELD_SET( 0, PANEL_PLL_CTRL, INPUT, OSC)
#ifndef VALIDATION_CHIP #ifndef VALIDATION_CHIP
| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD) | FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
#endif #endif
| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD) | FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N) | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M); | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
return ulPllReg; return ulPllReg;
} }
......
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