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Commit def37267 authored by David Woodhouse's avatar David Woodhouse
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PPC: Make Motorola CPM2 I/O core support more generic. 

It's used on more than one CPU.
parent adf791bd
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Showing with 1272 additions and 678 deletions
arch/ppc/8260_io/Kconfig
View file @ def37267
#
# MPC8260 Communication options
# CPM2 Communication options
#
menu "MPC8260 CPM Options"
depends on 8260
menu "CPM2 Options"
depends on CPM2
config SCC_CONSOLE
bool "Enable SCC Console"
......@@ -24,19 +24,19 @@ config FCC1_ENET
bool "Ethernet on FCC1"
depends on FEC_ENET
help
Use MPC8260 fast Ethernet controller 1 to drive Ethernet (default).
Use CPM2 fast Ethernet controller 1 to drive Ethernet (default).
config FCC2_ENET
bool "Ethernet on FCC2"
depends on FEC_ENET
help
Use MPC8260 fast Ethernet controller 2 to drive Ethernet.
Use CPM2 fast Ethernet controller 2 to drive Ethernet.
config FCC3_ENET
bool "Ethernet on FCC3"
depends on FEC_ENET
help
Use MPC8260 fast Ethernet controller 3 to drive Ethernet.
Use CPM2 fast Ethernet controller 3 to drive Ethernet.
config USE_MDIO
bool "Use MDIO for PHY configuration"
......
arch/ppc/8260_io/Makefile
View file @ def37267
#
# Makefile for the linux MPC8xx ppc-specific parts of comm processor
# Makefile for the linux ppc-specific parts of comm processor (v2)
#
obj-y := commproc.o uart.o
......
arch/ppc/8260_io/commproc.c
View file @ def37267
......@@ -26,29 +26,26 @@
#include <asm/mpc8260.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/immap_8260.h>
#include <asm/cpm_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/cpm2.h>
static uint dp_alloc_base; /* Starting offset in DP ram */
static uint dp_alloc_top; /* Max offset + 1 */
static uint host_buffer; /* One page of host buffer */
static uint host_end; /* end + 1 */
cpm8260_t *cpmp; /* Pointer to comm processor space */
cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
immap_t *immr;
cpm2_map_t *cpm2_immr;
void
m8260_cpm_reset(void)
cpm2_reset(void)
{
volatile immap_t *imp;
volatile cpm8260_t *commproc;
uint vpgaddr;
uint vpgaddr;
immr = imp = (volatile immap_t *)IMAP_ADDR;
commproc = &imp->im_cpm;
cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
/* Reclaim the DP memory for our use.
*/
......@@ -65,7 +62,7 @@ m8260_cpm_reset(void)
/* Tell everyone where the comm processor resides.
*/
cpmp = (cpm8260_t *)commproc;
cpmp = &cpm2_immr->im_cpm;
}
/* Allocate some memory from the dual ported ram.
......@@ -73,7 +70,7 @@ m8260_cpm_reset(void)
* if they ask.
*/
uint
m8260_cpm_dpalloc(uint size, uint align)
cpm2_dpalloc(uint size, uint align)
{
uint retloc;
uint align_mask, off;
......@@ -100,7 +97,7 @@ m8260_cpm_dpalloc(uint size, uint align)
* UART "fifos" and the like.
*/
uint
m8260_cpm_hostalloc(uint size, uint align)
cpm2_hostalloc(uint size, uint align)
{
uint retloc;
uint align_mask, off;
......@@ -140,17 +137,17 @@ m8260_cpm_hostalloc(uint size, uint align)
* oversampled clock.
*/
void
m8260_cpm_setbrg(uint brg, uint rate)
cpm2_setbrg(uint brg, uint rate)
{
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
bp = (uint *)&cpm2_immr->im_brgc1;
}
else {
bp = (uint *)&immr->im_brgc5;
bp = (uint *)&cpm2_immr->im_brgc5;
brg -= 4;
}
bp += brg;
......@@ -161,15 +158,15 @@ m8260_cpm_setbrg(uint brg, uint rate)
* clocks.
*/
void
m8260_cpm_fastbrg(uint brg, uint rate, int div16)
cpm2_fastbrg(uint brg, uint rate, int div16)
{
volatile uint *bp;
if (brg < 4) {
bp = (uint *)&immr->im_brgc1;
bp = (uint *)&cpm2_immr->im_brgc1;
}
else {
bp = (uint *)&immr->im_brgc5;
bp = (uint *)&cpm2_immr->im_brgc5;
brg -= 4;
}
bp += brg;
......
arch/ppc/8260_io/enet.c
View file @ def37267
......@@ -40,12 +40,12 @@
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/pgtable.h>
#include <asm/mpc8260.h>
#include <asm/bitops.h>
#include <asm/uaccess.h>
#include <asm/cpm_8260.h>
#include <asm/cpm2.h>
#include <asm/irq.h>
/*
......@@ -376,7 +376,7 @@ scc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
}
if (must_restart) {
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
/* Some transmit errors cause the transmitter to shut
* down. We now issue a restart transmit. Since the
......@@ -552,10 +552,10 @@ static void set_multicast_list(struct net_device *dev)
/* Log any net taps. */
printk("%s: Promiscuous mode enabled.\n", dev->name);
cep->sccp->scc_pmsr |= SCC_PSMR_PRO;
cep->sccp->scc_psmr |= SCC_PSMR_PRO;
} else {
cep->sccp->scc_pmsr &= ~SCC_PSMR_PRO;
cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
if (dev->flags & IFF_ALLMULTI) {
/* Catch all multicast addresses, so set the
......@@ -617,15 +617,15 @@ static int __init scc_enet_init(void)
unsigned long mem_addr;
bd_t *bd;
volatile cbd_t *bdp;
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
volatile scc_t *sccp;
volatile scc_enet_t *ep;
volatile immap_t *immap;
volatile iop8260_t *io;
volatile cpm2_map_t *immap;
volatile iop_cpm2_t *io;
cp = cpmp; /* Get pointer to Communication Processor */
immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */
io = &immap->im_ioport;
bd = (bd_t *)__res;
......@@ -680,11 +680,11 @@ static int __init scc_enet_init(void)
* These are relative offsets in the DP ram address space.
* Initialize base addresses for the buffer descriptors.
*/
i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
ep->sen_genscc.scc_rbase = i;
cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
ep->sen_genscc.scc_tbase = i;
cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
......@@ -820,7 +820,7 @@ static int __init scc_enet_init(void)
/* Set processing mode. Use Ethernet CRC, catch broadcast, and
* start frame search 22 bit times after RENA.
*/
sccp->scc_pmsr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
/* It is now OK to enable the Ethernet transmitter.
* Unfortunately, there are board implementation differences here.
......
arch/ppc/8260_io/fcc_enet.c
View file @ def37267
......@@ -35,13 +35,13 @@
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/pgtable.h>
#include <asm/mpc8260.h>
#include <asm/irq.h>
#include <asm/bitops.h>
#include <asm/uaccess.h>
#include <asm/cpm_8260.h>
#include <asm/cpm2.h>
/* The transmitter timeout
*/
......@@ -331,12 +331,12 @@ struct fcc_enet_private {
};
static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
volatile immap_t *immap);
volatile cpm2_map_t *immap);
static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
static void init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
volatile immap_t *immap);
static void init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
volatile cpm2_map_t *immap);
static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
volatile immap_t *immap);
volatile cpm2_map_t *immap);
#ifdef CONFIG_USE_MDIO
static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
......@@ -586,7 +586,7 @@ fcc_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
}
if (must_restart) {
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
/* Some transmit errors cause the transmitter to shut
* down. We now issue a restart transmit. Since the
......@@ -1361,10 +1361,10 @@ static int __init fec_enet_init(void)
struct fcc_enet_private *cep;
fcc_info_t *fip;
int i, np, err;
volatile immap_t *immap;
volatile iop8260_t *io;
volatile cpm2_map_t *immap;
volatile iop_cpm2_t *io;
immap = (immap_t *)IMAP_ADDR; /* and to internal registers */
immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */
io = &immap->im_ioport;
np = sizeof(fcc_ports) / sizeof(fcc_info_t);
......@@ -1431,7 +1431,7 @@ module_init(fec_enet_init);
*/
static void __init
init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
volatile immap_t *immap)
volatile cpm2_map_t *immap)
{
volatile fcc_enet_t *ep;
volatile fcc_t *fccp;
......@@ -1454,8 +1454,8 @@ init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
/* Initialize the I/O pins for the FCC Ethernet.
*/
static void __init
init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
volatile immap_t *immap)
init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
volatile cpm2_map_t *immap)
{
/* FCC1 pins are on port A/C. FCC2/3 are port B/C.
......@@ -1513,7 +1513,7 @@ init_fcc_ioports(fcc_info_t *fip, volatile iop8260_t *io,
static void __init
init_fcc_param(fcc_info_t *fip, struct net_device *dev,
volatile immap_t *immap)
volatile cpm2_map_t *immap)
{
unsigned char *eap;
unsigned long mem_addr;
......@@ -1522,7 +1522,7 @@ init_fcc_param(fcc_info_t *fip, struct net_device *dev,
struct fcc_enet_private *cep;
volatile fcc_enet_t *ep;
volatile cbd_t *bdp;
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
cep = (struct fcc_enet_private *)(dev->priv);
ep = cep->ep;
......@@ -1544,17 +1544,17 @@ init_fcc_param(fcc_info_t *fip, struct net_device *dev,
* work with the data cache enabled, so I allocate from the
* main memory instead.
*/
i = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
i = cpm2_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
ep->fen_genfcc.fcc_rbase = (uint)&immap->im_dprambase[i];
cep->rx_bd_base = (cbd_t *)&immap->im_dprambase[i];
i = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
i = cpm2_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
ep->fen_genfcc.fcc_tbase = (uint)&immap->im_dprambase[i];
cep->tx_bd_base = (cbd_t *)&immap->im_dprambase[i];
#else
cep->rx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
cep->rx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
cep->tx_bd_base = (cbd_t *)m8260_cpm_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
cep->tx_bd_base = (cbd_t *)cpm2_hostalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
#endif
......@@ -1817,10 +1817,10 @@ mii_send_receive(fcc_info_t *fip, uint cmd)
{
uint retval;
int read_op, i, off;
volatile immap_t *immap;
volatile iop8260_t *io;
volatile cpm2_map_t *immap;
volatile iop_cpm2_t *io;
immap = (immap_t *)IMAP_ADDR;
immap = (cpm2_map_t *)CPM_MAP_ADDR;
io = &immap->im_ioport;
io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
......
arch/ppc/8260_io/uart.c
View file @ def37267
......@@ -44,9 +44,9 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include <asm/cpm_8260.h>
#include <asm/cpm2.h>
#include <asm/irq.h>
#ifdef CONFIG_MAGIC_SYSRQ
......@@ -161,7 +161,7 @@ static struct serial_state rs_table[] = {
#ifndef CONFIG_SCC1_ENET
{ 0, 0, PROFF_SCC1, SIU_INT_SCC1, 0, SCC_NUM_BASE}, /* SCC1 ttyS2 */
#endif
#ifndef CONFIG_SCC2_ENET
#if !defined(CONFIG_SBC82xx) && !defined(CONFIG_SCC2_ENET)
{ 0, 0, PROFF_SCC2, SIU_INT_SCC2, 0, SCC_NUM_BASE + 1}, /* SCC2 ttyS3 */
#endif
};
......@@ -283,11 +283,11 @@ static void rs_8xx_stop(struct tty_struct *tty)
save_flags(flags); cli();
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
smcp->smc_smcm &= ~SMCM_TX;
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_sccm &= ~UART_SCCM_TX;
}
restore_flags(flags);
......@@ -306,11 +306,11 @@ static void rs_8xx_start(struct tty_struct *tty)
save_flags(flags); cli();
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
smcp->smc_smcm |= SMCM_TX;
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_sccm |= UART_SCCM_TX;
}
restore_flags(flags);
......@@ -635,7 +635,7 @@ static irqreturn_t rs_8xx_interrupt(int irq, void * dev_id, struct pt_regs * reg
info = (ser_info_t *)dev_id;
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
events = smcp->smc_smce;
if (events & SMCM_BRKE)
receive_break(info, regs);
......@@ -646,7 +646,7 @@ static irqreturn_t rs_8xx_interrupt(int irq, void * dev_id, struct pt_regs * reg
smcp->smc_smce = events;
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
events = sccp->scc_scce;
if (events & SMCM_BRKE)
receive_break(info, regs);
......@@ -775,7 +775,7 @@ static int startup(ser_info_t *info)
change_speed(info);
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
/* Enable interrupts and I/O.
*/
......@@ -790,7 +790,7 @@ static int startup(ser_info_t *info)
* of the last character before we decide no more characters
* are coming.
*/
up = (smc_uart_t *)&immr->im_dprambase[state->port];
up = (smc_uart_t *)&cpm2_immr->im_dprambase[state->port];
#if 0
up->smc_mrblr = 1; /* receive buffer length */
up->smc_maxidl = 0; /* wait forever for next char */
......@@ -801,8 +801,8 @@ static int startup(ser_info_t *info)
up->smc_brkcr = 1; /* number of break chars */
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
scup = (scc_uart_t *)&immr->im_dprambase[state->port];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
scup = (scc_uart_t *)&cpm2_immr->im_dprambase[state->port];
#if 0
scup->scc_genscc.scc_mrblr = 1; /* receive buffer length */
scup->scc_maxidl = 0; /* wait forever for next char */
......@@ -849,7 +849,7 @@ static void shutdown(ser_info_t * info)
save_flags(flags); cli(); /* Disable interrupts */
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
/* Disable interrupts and I/O.
*/
......@@ -863,7 +863,7 @@ static void shutdown(ser_info_t * info)
smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
#ifdef CONFIG_SERIAL_CONSOLE
if (idx != CONFIG_SERIAL_CONSOLE_PORT)
......@@ -916,17 +916,17 @@ static void change_speed(ser_info_t *info)
if (cflag & CSTOPB) {
cval |= SMCMR_SL; /* Two stops */
scval |= SCU_PMSR_SL;
scval |= SCU_PSMR_SL;
bits++;
}
if (cflag & PARENB) {
cval |= SMCMR_PEN;
scval |= SCU_PMSR_PEN;
scval |= SCU_PSMR_PEN;
bits++;
}
if (!(cflag & PARODD)) {
cval |= SMCMR_PM_EVEN;
scval |= (SCU_PMSR_REVP | SCU_PMSR_TEVP);
scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
}
/* Determine divisor based on baud rate */
......@@ -997,7 +997,7 @@ static void change_speed(ser_info_t *info)
*/
bits++;
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
/* Set the mode register. We want to keep a copy of the
* enables, because we want to put them back if they were
......@@ -1008,11 +1008,11 @@ static void change_speed(ser_info_t *info)
smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN));
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_pmsr = (sbits << 12) | scval;
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_psmr = (sbits << 12) | scval;
}
m8260_cpm_setbrg(info->state->smc_scc_num, baud_rate);
cpm2_setbrg(info->state->smc_scc_num, baud_rate);
restore_flags(flags);
}
......@@ -1359,7 +1359,7 @@ static int set_modem_info(ser_info_t *info, unsigned int cmd,
*/
static void begin_break(ser_info_t *info)
{
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
uint page, sblock;
int num;
......@@ -1403,7 +1403,7 @@ static void begin_break(ser_info_t *info)
static void end_break(ser_info_t *info)
{
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
uint page, sblock;
int num;
......@@ -1732,12 +1732,12 @@ static void rs_8xx_close(struct tty_struct *tty, struct file * filp)
info->read_status_mask &= ~BD_SC_EMPTY;
if (info->flags & ASYNC_INITIALIZED) {
if ((idx = info->state->smc_scc_num) < SCC_NUM_BASE) {
smcp = &immr->im_smc[idx];
smcp = &cpm2_immr->im_smc[idx];
smcp->smc_smcm &= ~SMCM_RX;
smcp->smc_smcmr &= ~SMCMR_REN;
}
else {
sccp = &immr->im_scc[idx - SCC_IDX_BASE];
sccp = &cpm2_immr->im_scc[idx - SCC_IDX_BASE];
sccp->scc_sccm &= ~UART_SCCM_RX;
sccp->scc_gsmrl &= ~SCC_GSMRL_ENR;
}
......@@ -2195,11 +2195,11 @@ static void my_console_write(int idx, const char *s,
else {
/* Pointer to UART in parameter ram.
*/
up = (smc_uart_t *)&immr->im_dprambase[ser->port];
up = (smc_uart_t *)&cpm2_immr->im_dprambase[ser->port];
/* Get the address of the host memory buffer.
*/
bdp = bdbase = (cbd_t *)&immr->im_dprambase[up->smc_tbase];
bdp = bdbase = (cbd_t *)&cpm2_immr->im_dprambase[up->smc_tbase];
}
/*
......@@ -2224,7 +2224,7 @@ static void my_console_write(int idx, const char *s,
* If the buffer address is in the CPM DPRAM, don't
* convert it.
*/
if ((uint)(bdp->cbd_bufaddr) > (uint)IMAP_ADDR)
if ((uint)(bdp->cbd_bufaddr) > (uint)CPM_MAP_ADDR)
cp = (u_char *)(bdp->cbd_bufaddr);
else
cp = __va(bdp->cbd_bufaddr);
......@@ -2311,7 +2311,7 @@ static int my_console_wait_key(int idx, int xmon, char *obuf)
/* Pointer to UART in parameter ram.
*/
up = (smc_uart_t *)&immr->im_dprambase[ser->port];
up = (smc_uart_t *)&cpm2_immr->im_dprambase[ser->port];
/* Get the address of the host memory buffer.
* If the port has been initialized for general use, we must
......@@ -2320,7 +2320,7 @@ static int my_console_wait_key(int idx, int xmon, char *obuf)
if ((info = (ser_info_t *)ser->info))
bdp = info->rx_cur;
else
bdp = (cbd_t *)&immr->im_dprambase[up->smc_rbase];
bdp = (cbd_t *)&cpm2_immr->im_dprambase[up->smc_rbase];
/*
* We need to gracefully shut down the receiver, disable
......@@ -2339,7 +2339,7 @@ static int my_console_wait_key(int idx, int xmon, char *obuf)
/* If the buffer address is in the CPM DPRAM, don't
* convert it.
*/
if ((uint)(bdp->cbd_bufaddr) > (uint)IMAP_ADDR)
if ((uint)(bdp->cbd_bufaddr) > (uint)CPM_MAP_ADDR)
cp = (u_char *)(bdp->cbd_bufaddr);
else
cp = __va(bdp->cbd_bufaddr);
......@@ -2402,7 +2402,7 @@ void kgdb_interruptible(int yes)
{
volatile smc_t *smcp;
smcp = &immr->im_smc[KGDB_SER_IDX];
smcp = &cpm2_immr->im_smc[KGDB_SER_IDX];
if (yes == 1)
smcp->smc_smcm |= SMCM_RX;
......@@ -2422,29 +2422,29 @@ void kgdb_map_scc(void)
* the kernel, and grab a memory location in the CPM that will
* work until the driver is really initialized.
*/
immr = (immap_t *)IMAP_ADDR;
cpm2_immr = (cpm2_map_t *)CPM_MAP_ADDR;
/* Right now, assume we are using SMCs.
*/
#ifdef USE_KGDB_SMC2
*(ushort *)(&immr->im_dprambase[PROFF_SMC2_BASE]) = serbase = PROFF_SMC2;
*(ushort *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = serbase = PROFF_SMC2;
#else
*(ushort *)(&immr->im_dprambase[PROFF_SMC1_BASE]) = serbase = PROFF_SMC1;
*(ushort *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = serbase = PROFF_SMC1;
#endif
up = (smc_uart_t *)&immr->im_dprambase[serbase];
up = (smc_uart_t *)&cpm2_immr->im_dprambase[serbase];
/* Allocate space for an input FIFO, plus a few bytes for output.
* Allocate bytes to maintain word alignment.
*/
mem_addr = (uint)(&immr->im_dprambase[0x1000]);
mem_addr = (uint)(&cpm2_immr->im_dprambase[0x1000]);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
bdp = (cbd_t *)&immr->im_dprambase[up->smc_rbase];
bdp = (cbd_t *)&cpm2_immr->im_dprambase[up->smc_rbase];
bdp->cbd_bufaddr = mem_addr;
bdp = (cbd_t *)&immr->im_dprambase[up->smc_tbase];
bdp = (cbd_t *)&cpm2_immr->im_dprambase[up->smc_tbase];
bdp->cbd_bufaddr = mem_addr+RX_BUF_SIZE;
up->smc_mrblr = RX_BUF_SIZE; /* receive buffer length */
......@@ -2507,13 +2507,13 @@ static int __init rs_8xx_init(void)
int i, j, idx;
uint page, sblock;
volatile cbd_t *bdp;
volatile cpm8260_t *cp;
volatile cpm_cpm2_t *cp;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile scc_t *scp;
volatile scc_uart_t *sup;
volatile immap_t *immap;
volatile iop8260_t *io;
volatile cpm2_map_t *immap;
volatile iop_cpm2_t *io;
serial_driver = alloc_tty_driver(NR_PORTS);
if (!serial_driver)
......@@ -2539,7 +2539,7 @@ static int __init rs_8xx_init(void)
if (tty_register_driver(serial_driver))
panic("Couldn't register serial driver\n");
immap = immr;
immap = cpm2_immr;
cp = &immap->im_cpm;
io = &immap->im_ioport;
......@@ -2657,11 +2657,11 @@ static int __init rs_8xx_init(void)
* descriptors from dual port ram, and a character
* buffer area from host mem.
*/
dp_addr = m8260_cpm_dpalloc(sizeof(cbd_t) * RX_NUM_FIFO, 8);
dp_addr = cpm2_dpalloc(sizeof(cbd_t) * RX_NUM_FIFO, 8);
/* Allocate space for FIFOs in the host memory.
*/
mem_addr = m8260_cpm_hostalloc(RX_NUM_FIFO * RX_BUF_SIZE, 1);
mem_addr = cpm2_hostalloc(RX_NUM_FIFO * RX_BUF_SIZE, 1);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
......@@ -2691,11 +2691,11 @@ static int __init rs_8xx_init(void)
sup->scc_genscc.scc_rbase = dp_addr;
}
dp_addr = m8260_cpm_dpalloc(sizeof(cbd_t) * TX_NUM_FIFO, 8);
dp_addr = cpm2_dpalloc(sizeof(cbd_t) * TX_NUM_FIFO, 8);
/* Allocate space for FIFOs in the host memory.
*/
mem_addr = m8260_cpm_hostalloc(TX_NUM_FIFO * TX_BUF_SIZE, 1);
mem_addr = cpm2_hostalloc(TX_NUM_FIFO * TX_BUF_SIZE, 1);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
......@@ -2834,7 +2834,7 @@ static int __init rs_8xx_init(void)
scp->scc_sccm = 0;
scp->scc_scce = 0xffff;
scp->scc_dsr = 0x7e7e;
scp->scc_pmsr = 0x3000;
scp->scc_psmr = 0x3000;
}
/* Install interrupt handler.
......@@ -2843,7 +2843,7 @@ static int __init rs_8xx_init(void)
/* Set up the baud rate generator.
*/
m8260_cpm_setbrg(state->smc_scc_num,
cpm2_setbrg(state->smc_scc_num,
baud_table[baud_idx]);
/* If the port is the console, enable Rx and Tx.
......@@ -2870,8 +2870,8 @@ static int __init serial_console_setup(struct console *co, char *options)
struct serial_state *ser;
uint mem_addr, dp_addr, bidx;
volatile cbd_t *bdp;
volatile cpm8260_t *cp;
volatile immap_t *immap;
volatile cpm_cpm2_t *cp;
volatile cpm2_map_t *immap;
#ifndef SCC_CONSOLE
volatile smc_t *sp;
volatile smc_uart_t *up;
......@@ -2880,7 +2880,7 @@ static int __init serial_console_setup(struct console *co, char *options)
volatile scc_t *scp;
volatile scc_uart_t *sup;
#endif
volatile iop8260_t *io;
volatile iop_cpm2_t *io;
bd_t *bd;
bd = (bd_t *)__res;
......@@ -2894,7 +2894,7 @@ static int __init serial_console_setup(struct console *co, char *options)
ser = rs_table + co->index;
immap = immr;
immap = cpm2_immr;
cp = &immap->im_cpm;
io = &immap->im_ioport;
......@@ -2944,11 +2944,11 @@ static int __init serial_console_setup(struct console *co, char *options)
/* Allocate space for two buffer descriptors in the DP ram.
*/
dp_addr = m8260_cpm_dpalloc(sizeof(cbd_t) * 2, 8);
dp_addr = cpm2_dpalloc(sizeof(cbd_t) * 2, 8);
/* Allocate space for two 2 byte FIFOs in the host memory.
*/
mem_addr = m8260_cpm_hostalloc(4, 1);
mem_addr = cpm2_hostalloc(4, 1);
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
......@@ -3014,7 +3014,7 @@ static int __init serial_console_setup(struct console *co, char *options)
scp->scc_sccm = 0;
scp->scc_scce = 0xffff;
scp->scc_dsr = 0x7e7e;
scp->scc_pmsr = 0x3000;
scp->scc_psmr = 0x3000;
/* Wire BRG1 to SCC1. The serial init will take care of
* others.
......@@ -3023,7 +3023,7 @@ static int __init serial_console_setup(struct console *co, char *options)
/* Set up the baud rate generator.
*/
m8260_cpm_setbrg(ser->smc_scc_num, bd->bi_baudrate);
cpm2_setbrg(ser->smc_scc_num, bd->bi_baudrate);
scp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#else
......@@ -3050,7 +3050,7 @@ static int __init serial_console_setup(struct console *co, char *options)
/* Set up the baud rate generator.
*/
m8260_cpm_setbrg(ser->smc_scc_num, bd->bi_baudrate);
cpm2_setbrg(ser->smc_scc_num, bd->bi_baudrate);
/* And finally, enable Rx and Tx.
*/
......
arch/ppc/Kconfig
View file @ def37267
......@@ -582,14 +582,23 @@ config EMBEDDEDBOOT
default y
config 8260
bool "MPC8260 CPM Support" if WILLOW
bool "CPM2 Support" if WILLOW
depends on 6xx
default y if TQM8260 || RPXSUPER || EST8260 || SBS8260 || SBC82xx
help
The MPC8260 CPM (Communications Processor Module) is a typical
embedded CPU made by Motorola. Selecting this option means that
you wish to build a kernel for a machine with specifically an 8260
for a CPU.
The MPC8260 is a typical embedded CPU made by Motorola. Selecting
this option means that you wish to build a kernel for a machine with
an 8260 class CPU.
config CPM2
bool
depends on 8260
default y
help
The CPM2 (Communications Processor Module) is a coprocessor on
embedded CPUs made by Motorola. Selecting this option means that
you wish to build a kernel for a machine with a CPM2 coprocessor
on it (826x, 827x, 8560).
config PPC_CHRP
bool
......@@ -672,11 +681,11 @@ config SPRUCE_BAUD_33M
config PC_KEYBOARD
bool "PC PS/2 style Keyboard"
depends on 4xx || 8260
depends on 4xx || CPM2
config SERIAL_CONSOLE
bool
depends on 8xx || 8260
depends on 8xx || CPM2
default y
config SERIAL_CONSOLE_BAUD
......@@ -957,7 +966,7 @@ config ISA
config GENERIC_ISA_DMA
bool
depends on POWER3 || POWER4 || 6xx && !8260
depends on POWER3 || POWER4 || 6xx && !CPM2
default y
config EISA
......@@ -974,10 +983,10 @@ config MCA
bool
config PCI
bool "PCI support" if 40x || 8260
default y if !40x && !8260 && !8xx && !APUS
default PCI_PERMEDIA if !4xx && !8260 && !8xx && APUS
default PCI_QSPAN if !4xx && !8260 && 8xx
bool "PCI support" if 40x || CPM2
default y if !40x && !CPM2 && !8xx && !APUS
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
default PCI_QSPAN if !4xx && !CPM2 && 8xx
help
Find out whether your system includes a PCI bus. PCI is the name of
a bus system, i.e. the way the CPU talks to the other stuff inside
......@@ -990,7 +999,7 @@ config PCI_DOMAINS
config PCI_QSPAN
bool "QSpan PCI"
depends on !4xx && !8260 && 8xx
depends on !4xx && !CPM2 && 8xx
help
Say Y here if you have a system based on a Motorola 8xx-series
embedded processor with a QSPAN PCI interface, otherwise say N.
......@@ -1229,7 +1238,7 @@ endchoice
config KGDB_CONSOLE
bool "Enable serial console thru kgdb port"
depends on KGDB && 8xx || 8260
depends on KGDB && 8xx || CPM2
help
If you enable this, all serial console messages will be sent
over the gdb stub.
......
arch/ppc/Makefile
View file @ def37267
......@@ -42,7 +42,7 @@ core-$(CONFIG_XMON) += arch/ppc/xmon/
core-$(CONFIG_APUS) += arch/ppc/amiga/
drivers-$(CONFIG_8xx) += arch/ppc/8xx_io/
drivers-$(CONFIG_4xx) += arch/ppc/4xx_io/
drivers-$(CONFIG_8260) += arch/ppc/8260_io/
drivers-$(CONFIG_CPM2) += arch/ppc/8260_io/
BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm
......
arch/ppc/boot/simple/embed_config.c
View file @ def37267
......@@ -16,7 +16,7 @@
#endif
#ifdef CONFIG_8260
#include <asm/mpc8260.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#endif
#ifdef CONFIG_40x
#include <asm/io.h>
......@@ -415,9 +415,9 @@ clk_8260(bd_t *bd)
{
uint scmr, vco_out, clkin;
uint plldf, pllmf, corecnf;
volatile immap_t *ip;
volatile cpm2_map_t *ip;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
scmr = ip->im_clkrst.car_scmr;
/* The clkin is always bus frequency.
......@@ -457,9 +457,9 @@ clk_8280(bd_t *bd)
{
uint scmr, main_clk, clkin;
uint pllmf, corecnf;
volatile immap_t *ip;
volatile cpm2_map_t *ip;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
scmr = ip->im_clkrst.car_scmr;
/* The clkin is always bus frequency.
......
arch/ppc/boot/simple/m8260_tty.c
View file @ def37267
......@@ -3,7 +3,8 @@
*/
#include <linux/types.h>
#include <asm/mpc8260.h>
#include <asm/cpm_8260.h>
#include <asm/cpm2.h>
#include <asm/immap_cpm2.h>
uint no_print;
extern char *params[];
......@@ -29,12 +30,12 @@ serial_init(int ignored, bd_t *bd)
volatile scc_uart_t *sup;
#endif
volatile cbd_t *tbdf, *rbdf;
volatile immap_t *ip;
volatile iop8260_t *io;
volatile cpm8260_t *cp;
volatile cpm2_map_t *ip;
volatile iop_cpm2_t *io;
volatile cpm_cpm2_t *cp;
uint dpaddr, memaddr;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
cp = &ip->im_cpm;
io = &ip->im_ioport;
......@@ -223,10 +224,10 @@ serial_readbuf(u_char *cbuf)
volatile char *buf;
volatile smc_uart_t *up;
volatile scc_uart_t *sup;
volatile immap_t *ip;
volatile cpm2_map_t *ip;
int i, nc;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
#ifdef SCC_CONSOLE
sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
......@@ -255,10 +256,10 @@ serial_putc(void *ignored, const char c)
volatile char *buf;
volatile smc_uart_t *up;
volatile scc_uart_t *sup;
volatile immap_t *ip;
volatile cpm2_map_t *ip;
extern bd_t *board_info;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
#ifdef SCC_CONSOLE
sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
tbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_tbase];
......@@ -298,9 +299,9 @@ serial_tstc(void *ignored)
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile scc_uart_t *sup;
volatile immap_t *ip;
volatile cpm2_map_t *ip;
ip = (immap_t *)IMAP_ADDR;
ip = (cpm2_map_t *)CPM_MAP_ADDR;
#ifdef SCC_CONSOLE
sup = (scc_uart_t *)&ip->im_dprambase[PROFF_SCC1 + ((SCC_CONSOLE-1) << 8)];
rbdf = (cbd_t *)&ip->im_dprambase[sup->scc_genscc.scc_rbase];
......
arch/ppc/platforms/est8260.h
View file @ def37267
......@@ -6,7 +6,7 @@
#ifndef __EST8260_PLATFORM
#define __EST8260_PLATFORM
#define IMAP_ADDR ((uint)0xf0000000)
#define CPM_MAP_ADDR ((uint)0xf0000000)
#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
......
arch/ppc/platforms/rpxsuper.h
View file @ def37267
......@@ -32,7 +32,7 @@ extern bd_t m8xx_board_info;
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
*/
#define IMAP_ADDR ((uint)0xf0000000)
#define CPM_MAP_ADDR ((uint)0xf0000000)
#define RPX_CSR_ADDR ((uint)0xfa000000)
#define RPX_CSR_SIZE ((uint)(512 * 1024))
#define RPX_NVRTC_ADDR ((uint)0xfa080000)
......
arch/ppc/platforms/sbc82xx.c
View file @ def37267
......@@ -23,7 +23,7 @@
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/todc.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
static void (*callback_setup_arch)(void);
......@@ -67,7 +67,7 @@ TODC_ALLOC();
#ifdef CONFIG_GEN_RTC
static void sbc82xx_time_init(void)
{
volatile memctl8260_t *mc = &immr->im_memctl;
volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
/* Set up CS11 for RTC chip */
......
arch/ppc/platforms/sbc82xx.h
View file @ def37267
......@@ -9,7 +9,6 @@
#include <asm/ppcboot.h>
#define IMAP_ADDR 0xf0000000
#define CPM_MAP_ADDR 0xf0000000
#define SBC82xx_TODC_NVRAM_ADDR 0x80000000
......
arch/ppc/platforms/sbs8260.h
View file @ def37267
......@@ -5,7 +5,7 @@
* the configuration SCMR and the Power-On-Reset word.
*/
#define IMAP_ADDR ((uint)0xfe000000)
#define CPM_MAP_ADDR ((uint)0xfe000000)
/* A Board Information structure that is given to a program when
......
arch/ppc/platforms/tqm8260.h
View file @ def37267
......@@ -11,7 +11,7 @@
#include <asm/ppcboot.h>
#define IMAP_ADDR ((uint)0xFFF00000)
#define CPM_MAP_ADDR ((uint)0xFFF00000)
#define PHY_INTERRUPT 25
#define BOOTROM_RESTART_ADDR ((uint)0x40000104)
......
arch/ppc/platforms/tqm8260_setup.c
View file @ def37267
......@@ -17,7 +17,7 @@
#include <linux/config.h>
#include <linux/seq_file.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include <asm/machdep.h>
......@@ -44,8 +44,8 @@ tqm8260_show_cpuinfo(struct seq_file *m)
static int
tqm8260_set_rtc_time(unsigned long time)
{
((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt = time;
((immap_t *)IMAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time;
((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
return(0);
}
......@@ -53,7 +53,7 @@ tqm8260_set_rtc_time(unsigned long time)
static unsigned long
tqm8260_get_rtc_time(void)
{
return ((immap_t *)IMAP_ADDR)->im_sit.sit_tmcnt;
return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt;
}
static void __init
......
arch/ppc/syslib/Makefile
View file @ def37267
......@@ -66,7 +66,7 @@ obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o pci_auto.o todc_time.o
obj-$(CONFIG_SBC82xx) += todc_time.o
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o ppc8260_pic.o
obj-$(CONFIG_8260) += m8260_setup.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o
obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o
......
arch/ppc/syslib/ppc8260_pic.c → arch/ppc/syslib/cpm2_pic.c
View file @ def37267
......@@ -3,11 +3,11 @@
#include <linux/sched.h>
#include <linux/signal.h>
#include <asm/irq.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include "ppc8260_pic.h"
#include "cpm2_pic.h"
/* The 8260 internal interrupt controller. It is usually
/* The CPM2 internal interrupt controller. It is usually
* the only interrupt controller.
* There are two 32-bit registers (high/low) for up to 64
* possible interrupts.
......@@ -40,7 +40,7 @@ static u_char irq_to_siubit[] = {
7, 6, 5, 4, 3, 2, 1, 0
};
static void m8260_mask_irq(unsigned int irq_nr)
static void cpm2_mask_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
......@@ -48,12 +48,12 @@ static void m8260_mask_irq(unsigned int irq_nr)
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(immr->im_intctl.ic_simrh);
simr = &(cpm2_immr->im_intctl.ic_simrh);
ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
}
static void m8260_unmask_irq(unsigned int irq_nr)
static void cpm2_unmask_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
......@@ -61,12 +61,12 @@ static void m8260_unmask_irq(unsigned int irq_nr)
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(immr->im_intctl.ic_simrh);
simr = &(cpm2_immr->im_intctl.ic_simrh);
ppc_cached_irq_mask[word] |= (1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
}
static void m8260_mask_and_ack(unsigned int irq_nr)
static void cpm2_mask_and_ack(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr, *sipnr;
......@@ -74,14 +74,14 @@ static void m8260_mask_and_ack(unsigned int irq_nr)
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(immr->im_intctl.ic_simrh);
sipnr = &(immr->im_intctl.ic_sipnrh);
simr = &(cpm2_immr->im_intctl.ic_simrh);
sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
sipnr[word] = 1 << (31 - bit);
}
static void m8260_end_irq(unsigned int irq_nr)
static void cpm2_end_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
......@@ -92,33 +92,33 @@ static void m8260_end_irq(unsigned int irq_nr)
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(immr->im_intctl.ic_simrh);
simr = &(cpm2_immr->im_intctl.ic_simrh);
ppc_cached_irq_mask[word] |= (1 << (31 - bit));
simr[word] = ppc_cached_irq_mask[word];
}
}
struct hw_interrupt_type ppc8260_pic = {
" 8260 SIU ",
struct hw_interrupt_type cpm2_pic = {
" CPM2 SIU ",
NULL,
NULL,
m8260_unmask_irq,
m8260_mask_irq,
m8260_mask_and_ack,
m8260_end_irq,
cpm2_unmask_irq,
cpm2_mask_irq,
cpm2_mask_and_ack,
cpm2_end_irq,
0
};
int
m8260_get_irq(struct pt_regs *regs)
cpm2_get_irq(struct pt_regs *regs)
{
int irq;
unsigned long bits;
/* For MPC8260, read the SIVEC register and shift the bits down
/* For CPM2, read the SIVEC register and shift the bits down
* to get the irq number. */
bits = immr->im_intctl.ic_sivec;
bits = cpm2_immr->im_intctl.ic_sivec;
irq = bits >> 26;
if (irq == 0)
......
arch/ppc/syslib/cpm2_pic.h 0 → 100644
View file @ def37267
#ifndef _PPC_KERNEL_CPM2_H
#define _PPC_KERNEL_CPM2_H
#include <linux/irq.h>
extern struct hw_interrupt_type cpm2_pic;
void cpm2_pic_init(void);
void cpm2_do_IRQ(struct pt_regs *regs,
int cpu);
int cpm2_get_irq(struct pt_regs *regs);
#endif /* _PPC_KERNEL_CPM2_H */
arch/ppc/syslib/m8260_setup.c
View file @ def37267
......@@ -39,12 +39,12 @@
#include <asm/pgtable.h>
#include <asm/ide.h>
#include <asm/mpc8260.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
#include <asm/machdep.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include "ppc8260_pic.h"
#include "cpm2_pic.h"
static int m8260_set_rtc_time(unsigned long time);
static unsigned long m8260_get_rtc_time(void);
......@@ -52,14 +52,14 @@ static void m8260_calibrate_decr(void);
unsigned char __res[sizeof(bd_t)];
extern void m8260_cpm_reset(void);
extern void cpm2_reset(void);
static void __init
m8260_setup_arch(void)
{
/* Reset the Communication Processor Module.
*/
m8260_cpm_reset();
cpm2_reset();
}
/* The decrementer counts at the system (internal) clock frequency
......@@ -142,9 +142,9 @@ m8260_show_percpuinfo(struct seq_file *m, int i)
bp = (bd_t *)__res;
seq_printf(m, "core clock\t: %d MHz\n"
"CPM clock\t: %d MHz\n"
"bus clock\t: %d MHz\n",
seq_printf(m, "core clock\t: %ld MHz\n"
"CPM clock\t: %ld MHz\n"
"bus clock\t: %ld MHz\n",
bp->bi_intfreq / 1000000,
bp->bi_cpmfreq / 1000000,
bp->bi_busfreq / 1000000);
......@@ -164,15 +164,15 @@ m8260_init_IRQ(void)
void cpm_interrupt_init(void);
for ( i = 0 ; i < NR_SIU_INTS ; i++ )
irq_desc[i].handler = &ppc8260_pic;
irq_desc[i].handler = &cpm2_pic;
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
*/
immr->im_intctl.ic_sicr = 0;
immr->im_intctl.ic_siprr = 0x05309770;
immr->im_intctl.ic_scprrh = 0x05309770;
immr->im_intctl.ic_scprrl = 0x05309770;
cpm2_immr->im_intctl.ic_sicr = 0;
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
}
/*
......@@ -200,7 +200,7 @@ m8260_map_io(void)
uint addr;
/* Map IMMR region to a 256MB BAT */
addr = (immr != NULL) ? (uint)immr : IMAP_ADDR;
addr = (cpm2_immr != NULL) ? (uint)cpm2_immr : CPM_MAP_ADDR;
io_block_mapping(addr, addr, 0x10000000, _PAGE_IO);
/* Map I/O region to a 256MB BAT */
......@@ -244,7 +244,7 @@ m8260_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.show_percpuinfo = m8260_show_percpuinfo;
ppc_md.irq_canonicalize = NULL;
ppc_md.init_IRQ = m8260_init_IRQ;
ppc_md.get_irq = m8260_get_irq;
ppc_md.get_irq = cpm2_get_irq;
ppc_md.init = NULL;
ppc_md.restart = m8260_restart;
......
arch/ppc/syslib/ppc8260_pic.h deleted 100644 → 0
View file @ adf791bd
#ifndef _PPC_KERNEL_PPC8260_H
#define _PPC_KERNEL_PPC8260_H
#include <linux/irq.h>
extern struct hw_interrupt_type ppc8260_pic;
void m8260_pic_init(void);
void m8260_do_IRQ(struct pt_regs *regs,
int cpu);
int m8260_get_irq(struct pt_regs *regs);
#endif /* _PPC_KERNEL_PPC8260_H */
drivers/mtd/maps/wr_sbc82xx_flash.c
View file @ def37267
......@@ -20,7 +20,7 @@
#include <linux/config.h>
#include <linux/mtd/partitions.h>
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
static struct mtd_info *sbcmtd[3];
static struct mtd_partition *sbcmtd_parts[3];
......@@ -59,7 +59,7 @@ static const char *part_probes[] __initdata = {"cmdlinepart", "RedBoot", NULL};
int __init init_sbc82xx_flash(void)
{
volatile memctl8260_t *mc = &immr->im_memctl;
volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
int bigflash;
int i;
......
include/asm-ppc/cpm_8260.h → include/asm-ppc/cpm2.h
View file @ def37267
/*
* MPC8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
* Communication Processor Module v2.
*
* This file contains structures and information for the communication
* processor channels found in the dual port RAM or parameter RAM.
* All CPM control and status is available through the MPC8260 internal
* memory map. See immap.h for details.
* All CPM control and status is available through the CPM2 internal
* memory map. See immap_cpm2.h for details.
*/
#ifdef __KERNEL__
#ifndef __CPM_82XX__
#define __CPM_82XX__
#ifndef __CPM2__
#define __CPM2__
#include <asm/immap_8260.h>
#include <asm/immap_cpm2.h>
/* CPM Command register.
*/
......@@ -72,6 +71,8 @@
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_START_IDMA ((ushort)0x0009)
#define CPM_CR_STOP_IDMA ((ushort)0x000b)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
......@@ -83,9 +84,14 @@
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#ifdef CONFIG_8272
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#else
#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
#endif
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
......@@ -97,11 +103,11 @@
/* Export the base address of the communication processor registers
* and dual port ram.
*/
extern cpm8260_t *cpmp; /* Pointer to comm processor */
uint m8260_cpm_dpalloc(uint size, uint align);
uint m8260_cpm_hostalloc(uint size, uint align);
void m8260_cpm_setbrg(uint brg, uint rate);
void m8260_cpm_fastbrg(uint brg, uint rate, int div16);
extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
uint cpm2_dpalloc(uint size, uint align);
uint cpm2_hostalloc(uint size, uint align);
void cpm2_setbrg(uint brg, uint rate);
void cpm2_fastbrg(uint brg, uint rate, int div16);
/* Buffer descriptors used by many of the CPM protocols.
*/
......@@ -504,21 +510,21 @@ typedef struct scc_uart {
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PMSR when used as a UART.
/* The SCC PSMR when used as a UART.
*/
#define SCU_PMSR_FLC ((ushort)0x8000)
#define SCU_PMSR_SL ((ushort)0x4000)
#define SCU_PMSR_CL ((ushort)0x3000)
#define SCU_PMSR_UM ((ushort)0x0c00)
#define SCU_PMSR_FRZ ((ushort)0x0200)
#define SCU_PMSR_RZS ((ushort)0x0100)
#define SCU_PMSR_SYN ((ushort)0x0080)
#define SCU_PMSR_DRT ((ushort)0x0040)
#define SCU_PMSR_PEN ((ushort)0x0010)
#define SCU_PMSR_RPM ((ushort)0x000c)
#define SCU_PMSR_REVP ((ushort)0x0008)
#define SCU_PMSR_TPM ((ushort)0x0003)
#define SCU_PMSR_TEVP ((ushort)0x0003)
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
......@@ -612,7 +618,7 @@ typedef struct fcc_enet {
ushort fen_paddrm;
ushort fen_paddrl;
ushort fen_ibdcount; /* Internal BD counter */
ushort fen_idbstart; /* Internal BD start pointer */
ushort fen_ibdstart; /* Internal BD start pointer */
ushort fen_ibdend; /* Internal BD end pointer */
ushort fen_txlen; /* Internal Tx frame length counter */
uint fen_ibdbase[8]; /* Internal use */
......@@ -696,7 +702,336 @@ typedef struct iic {
uint iic_txtmp; /* Internal */
} iic_t;
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res; /* Tx temp. */
uint spi_res1[4]; /* SDMA temp. */
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
#define SPI_EB ((u_char)0x10) /* big endian byte order */
#define BD_IIC_START ((ushort)0x0400)
#endif /* __CPM_82XX__ */
/* IDMA parameter RAM
*/
typedef struct idma {
ushort ibase; /* IDMA buffer descriptor table base address */
ushort dcm; /* DMA channel mode */
ushort ibdptr; /* IDMA current buffer descriptor pointer */
ushort dpr_buf; /* IDMA transfer buffer base address */
ushort buf_inv; /* internal buffer inventory */
ushort ss_max; /* steady-state maximum transfer size */
ushort dpr_in_ptr; /* write pointer inside the internal buffer */
ushort sts; /* source transfer size */
ushort dpr_out_ptr; /* read pointer inside the internal buffer */
ushort seob; /* source end of burst */
ushort deob; /* destination end of burst */
ushort dts; /* destination transfer size */
ushort ret_add; /* return address when working in ERM=1 mode */
ushort res0; /* reserved */
uint bd_cnt; /* internal byte count */
uint s_ptr; /* source internal data pointer */
uint d_ptr; /* destination internal data pointer */
uint istate; /* internal state */
u_char res1[20]; /* pad to 64-byte length */
} idma_t;
/* DMA channel mode bit fields
*/
#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
/* IDMA Buffer Descriptors
*/
typedef struct idma_bd {
uint flags;
uint len; /* data length */
uint src; /* source data buffer pointer */
uint dst; /* destination data buffer pointer */
} idma_bd_t;
/* IDMA buffer descriptor flag bit fields
*/
#define IDMA_BD_V ((uint)0x80000000) /* valid */
#define IDMA_BD_W ((uint)0x20000000) /* wrap */
#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
#define IDMA_BD_L ((uint)0x08000000) /* last */
#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
/* per-channel IDMA registers
*/
typedef struct im_idma {
u_char idsr; /* IDMAn event status register */
u_char res0[3];
u_char idmr; /* IDMAn event mask register */
u_char res1[3];
} im_idma_t;
/* IDMA event register bit fields
*/
#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
/* RISC Controller Configuration Register (RCCR) bit fields
*/
#define RCCR_TIME ((uint)0x80000000) /* timer enable */
#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
/*-----------------------------------------------------------------------
* CMXFCR - CMX FCC Clock Route Register
*/
#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
/*-----------------------------------------------------------------------
* CMXSCR - CMX SCC Clock Route Register
*/
#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
#endif /* __CPM2__ */
#endif /* __KERNEL__ */
include/asm-ppc/immap_8260.h deleted 100644 → 0
View file @ adf791bd
/*
* MPC8260 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* The Internal Memory Map of the 8260. I don't know how generic
* this will be, as I don't have any knowledge of the subsequent
* parts at this time. I copied this from the 8xx_immap.h.
*/
#ifdef __KERNEL__
#ifndef __IMMAP_82XX__
#define __IMMAP_82XX__
/* System configuration registers.
*/
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
char res1[6];
ushort sc_swsr;
char res2[20];
uint sc_bcr;
u_char sc_ppc_acr;
char res3[3];
uint sc_ppc_alrh;
uint sc_ppc_alrl;
u_char sc_lcl_acr;
char res4[3];
uint sc_lcl_alrh;
uint sc_lcl_alrl;
uint sc_tescr1;
uint sc_tescr2;
uint sc_ltescr1;
uint sc_ltescr2;
uint sc_pdtea;
u_char sc_pdtem;
char res5[3];
uint sc_ldtea;
u_char sc_ldtem;
char res6[163];
} sysconf8260_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
uint memc_br0;
uint memc_or0;
uint memc_br1;
uint memc_or1;
uint memc_br2;
uint memc_or2;
uint memc_br3;
uint memc_or3;
uint memc_br4;
uint memc_or4;
uint memc_br5;
uint memc_or5;
uint memc_br6;
uint memc_or6;
uint memc_br7;
uint memc_or7;
uint memc_br8;
uint memc_or8;
uint memc_br9;
uint memc_or9;
uint memc_br10;
uint memc_or10;
uint memc_br11;
uint memc_or11;
char res1[8];
uint memc_mar;
char res2[4];
uint memc_mamr;
uint memc_mbmr;
uint memc_mcmr;
char res3[8];
ushort memc_mptpr;
char res4[2];
uint memc_mdr;
char res5[4];
uint memc_psdmr;
uint memc_lsdmr;
u_char memc_purt;
char res6[3];
u_char memc_psrt;
char res7[3];
u_char memc_lurt;
char res8[3];
u_char memc_lsrt;
char res9[3];
uint memc_immr;
char res10[84];
} memctl8260_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
char res1[32];
ushort sit_tmcntsc;
char res2[2];
uint sit_tmcnt;
char res3[4];
uint sit_tmcntal;
char res4[16];
ushort sit_piscr;
char res5[2];
uint sit_pitc;
uint sit_pitr;
char res6[94];
char res7[2390];
} sit8260_t;
#define PISCR_PIRQ_MASK ((ushort)0xff00)
#define PISCR_PS ((ushort)0x0080)
#define PISCR_PIE ((ushort)0x0004)
#define PISCR_PTF ((ushort)0x0002)
#define PISCR_PTE ((ushort)0x0001)
/* Interrupt Controller.
*/
typedef struct interrupt_controller {
ushort ic_sicr;
char res1[2];
uint ic_sivec;
uint ic_sipnrh;
uint ic_sipnrl;
uint ic_siprr;
uint ic_scprrh;
uint ic_scprrl;
uint ic_simrh;
uint ic_simrl;
uint ic_siexr;
char res2[88];
} intctl8260_t;
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
uint car_sccr;
char res1[4];
uint car_scmr;
char res2[4];
uint car_rsr;
uint car_rmr;
char res[104];
} car8260_t;
/* Input/Output Port control/status registers.
* Names consistent with processor manual, although they are different
* from the original 8xx names.......
*/
typedef struct io_port {
uint iop_pdira;
uint iop_ppara;
uint iop_psora;
uint iop_podra;
uint iop_pdata;
char res1[12];
uint iop_pdirb;
uint iop_pparb;
uint iop_psorb;
uint iop_podrb;
uint iop_pdatb;
char res2[12];
uint iop_pdirc;
uint iop_pparc;
uint iop_psorc;
uint iop_podrc;
uint iop_pdatc;
char res3[12];
uint iop_pdird;
uint iop_ppard;
uint iop_psord;
uint iop_podrd;
uint iop_pdatd;
char res4[12];
} iop8260_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
u_char cpmt_tgcr1;
char res1[3];
u_char cpmt_tgcr2;
char res2[11];
ushort cpmt_tmr1;
ushort cpmt_tmr2;
ushort cpmt_trr1;
ushort cpmt_trr2;
ushort cpmt_tcr1;
ushort cpmt_tcr2;
ushort cpmt_tcn1;
ushort cpmt_tcn2;
ushort cpmt_tmr3;
ushort cpmt_tmr4;
ushort cpmt_trr3;
ushort cpmt_trr4;
ushort cpmt_tcr3;
ushort cpmt_tcr4;
ushort cpmt_tcn3;
ushort cpmt_tcn4;
ushort cpmt_ter1;
ushort cpmt_ter2;
ushort cpmt_ter3;
ushort cpmt_ter4;
char res3[584];
} cpmtimer8260_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
char res0[24];
u_char sdma_sdsr;
char res1[3];
u_char sdma_sdmr;
char res2[3];
u_char sdma_idsr1;
char res3[3];
u_char sdma_idmr1;
char res4[3];
u_char sdma_idsr2;
char res5[3];
u_char sdma_idmr2;
char res6[3];
u_char sdma_idsr3;
char res7[3];
u_char sdma_idmr3;
char res8[3];
u_char sdma_idsr4;
char res9[3];
u_char sdma_idmr4;
char res10[707];
} sdma8260_t;
/* Fast controllers
*/
typedef struct fcc {
uint fcc_gfmr;
uint fcc_fpsmr;
ushort fcc_ftodr;
char res1[2];
ushort fcc_fdsr;
char res2[2];
ushort fcc_fcce;
char res3[2];
ushort fcc_fccm;
char res4[2];
u_char fcc_fccs;
char res5[3];
u_char fcc_ftirr_phy[4];
} fcc_t;
/* I2C
*/
typedef struct i2c {
u_char i2c_i2mod;
char res1[3];
u_char i2c_i2add;
char res2[3];
u_char i2c_i2brg;
char res3[3];
u_char i2c_i2com;
char res4[3];
u_char i2c_i2cer;
char res5[3];
u_char i2c_i2cmr;
char res6[331];
} i2c8260_t;
typedef struct scc { /* Serial communication channels */
uint scc_gsmrl;
uint scc_gsmrh;
ushort scc_pmsr;
char res1[2];
ushort scc_todr;
ushort scc_dsr;
ushort scc_scce;
char res2[2];
ushort scc_sccm;
char res3;
u_char scc_sccs;
char res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
char res1[2];
ushort smc_smcmr;
char res2[2];
u_char smc_smce;
char res3[3];
u_char smc_smcm;
char res4[5];
} smc_t;
/* Serial Peripheral Interface.
*/
typedef struct spi {
ushort spi_spmode;
char res1[4];
u_char spi_spie;
char res2[3];
u_char spi_spim;
char res3[2];
u_char spi_spcom;
char res4[82];
} spi_t;
/* CPM Mux.
*/
typedef struct cpmux {
u_char cmx_si1cr;
char res1;
u_char cmx_si2cr;
char res2;
uint cmx_fcr;
uint cmx_scr;
u_char cmx_smr;
char res3;
ushort cmx_uar;
char res4[16];
} cpmux_t;
/* SIRAM control
*/
typedef struct siram {
ushort si_amr;
ushort si_bmr;
ushort si_cmr;
ushort si_dmr;
u_char si_gmr;
char res1;
u_char si_cmdr;
char res2;
u_char si_str;
char res3;
ushort si_rsr;
} siramctl_t;
typedef struct mcc {
ushort mcc_mcce;
char res1[2];
ushort mcc_mccm;
char res2[2];
u_char mcc_mccf;
char res3[7];
} mcc_t;
typedef struct comm_proc {
uint cp_cpcr;
uint cp_rccr;
char res1[14];
ushort cp_rter;
char res2[2];
ushort cp_rtmr;
ushort cp_rtscr;
char res3[2];
uint cp_rtsr;
char res4[12];
} cpm8260_t;
/* ...and the whole thing wrapped up....
*/
typedef struct immap {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
#define im_dprambase im_dpram1
u_char im_dpram1[16*1024];
char res1[16*1024];
u_char im_dpram2[4*1024];
char res2[8*1024];
u_char im_dpram3[4*1024];
char res3[16*1024];
sysconf8260_t im_siu_conf; /* SIU Configuration */
memctl8260_t im_memctl; /* Memory Controller */
sit8260_t im_sit; /* System Integration Timers */
intctl8260_t im_intctl; /* Interrupt Controller */
car8260_t im_clkrst; /* Clocks and reset */
iop8260_t im_ioport; /* IO Port control/status */
cpmtimer8260_t im_cpmtimer; /* CPM timers */
sdma8260_t im_sdma; /* SDMA control/status */
fcc_t im_fcc[3]; /* Three FCCs */
char res4[159];
/* First set of baud rate generators.
*/
char res4a[496];
uint im_brgc5;
uint im_brgc6;
uint im_brgc7;
uint im_brgc8;
char res5[608];
i2c8260_t im_i2c; /* I2C control/status */
cpm8260_t im_cpm; /* Communication processor */
/* Second set of baud rate generators.
*/
uint im_brgc1;
uint im_brgc2;
uint im_brgc3;
uint im_brgc4;
scc_t im_scc[4]; /* Four SCCs */
smc_t im_smc[2]; /* Couple of SMCs */
spi_t im_spi; /* A SPI */
cpmux_t im_cpmux; /* CPM clock route mux */
siramctl_t im_siramctl1; /* First SI RAM Control */
mcc_t im_mcc1; /* First MCC */
siramctl_t im_siramctl2; /* Second SI RAM Control */
mcc_t im_mcc2; /* Second MCC */
char res6[1184];
ushort im_si1txram[256];
char res7[512];
ushort im_si1rxram[256];
char res8[512];
ushort im_si2txram[256];
char res9[512];
ushort im_si2rxram[256];
char res10[512];
char res11[4096];
} immap_t;
extern immap_t *immr;
#endif /* __IMMAP_82XX__ */
#endif /* __KERNEL__ */
include/asm-ppc/immap_cpm2.h 0 → 100644
View file @ def37267
/*
* CPM2 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* The Internal Memory Map for devices with CPM2 on them. This
* is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
* 8560).
*/
#ifdef __KERNEL__
#ifndef __IMMAP_CPM2__
#define __IMMAP_CPM2__
/* System configuration registers.
*/
typedef struct sys_82xx_conf {
u32 sc_siumcr;
u32 sc_sypcr;
u8 res1[6];
u16 sc_swsr;
u8 res2[20];
u32 sc_bcr;
u8 sc_ppc_acr;
u8 res3[3];
u32 sc_ppc_alrh;
u32 sc_ppc_alrl;
u8 sc_lcl_acr;
u8 res4[3];
u32 sc_lcl_alrh;
u32 sc_lcl_alrl;
u32 sc_tescr1;
u32 sc_tescr2;
u32 sc_ltescr1;
u32 sc_ltescr2;
u32 sc_pdtea;
u8 sc_pdtem;
u8 res5[3];
u32 sc_ldtea;
u8 sc_ldtem;
u8 res6[163];
} sysconf_82xx_cpm2_t;
typedef struct sys_85xx_conf {
u32 sc_cear;
u16 sc_ceer;
u16 sc_cemr;
u8 res1[70];
u32 sc_smaer;
u8 res2[4];
u32 sc_smevr;
u32 sc_smctr;
u32 sc_lmaer;
u8 res3[4];
u32 sc_lmevr;
u32 sc_lmctr;
u8 res4[144];
} sysconf_85xx_cpm2_t;
typedef union sys_conf {
sysconf_82xx_cpm2_t siu_82xx;
sysconf_85xx_cpm2_t siu_85xx;
} sysconf_cpm2_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
u32 memc_br0;
u32 memc_or0;
u32 memc_br1;
u32 memc_or1;
u32 memc_br2;
u32 memc_or2;
u32 memc_br3;
u32 memc_or3;
u32 memc_br4;
u32 memc_or4;
u32 memc_br5;
u32 memc_or5;
u32 memc_br6;
u32 memc_or6;
u32 memc_br7;
u32 memc_or7;
u32 memc_br8;
u32 memc_or8;
u32 memc_br9;
u32 memc_or9;
u32 memc_br10;
u32 memc_or10;
u32 memc_br11;
u32 memc_or11;
u8 res1[8];
u32 memc_mar;
u8 res2[4];
u32 memc_mamr;
u32 memc_mbmr;
u32 memc_mcmr;
u8 res3[8];
u16 memc_mptpr;
u8 res4[2];
u32 memc_mdr;
u8 res5[4];
u32 memc_psdmr;
u32 memc_lsdmr;
u8 memc_purt;
u8 res6[3];
u8 memc_psrt;
u8 res7[3];
u8 memc_lurt;
u8 res8[3];
u8 memc_lsrt;
u8 res9[3];
u32 memc_immr;
u32 memc_pcibr0;
u32 memc_pcibr1;
u8 res10[16];
u32 memc_pcimsk0;
u32 memc_pcimsk1;
u8 res11[52];
} memctl_cpm2_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
u8 res1[32];
u16 sit_tmcntsc;
u8 res2[2];
u32 sit_tmcnt;
u8 res3[4];
u32 sit_tmcntal;
u8 res4[16];
u16 sit_piscr;
u8 res5[2];
u32 sit_pitc;
u32 sit_pitr;
u8 res6[92];
u8 res7[390];
} sit_cpm2_t;
#define PISCR_PIRQ_MASK ((u16)0xff00)
#define PISCR_PS ((u16)0x0080)
#define PISCR_PIE ((u16)0x0004)
#define PISCR_PTF ((u16)0x0002)
#define PISCR_PTE ((u16)0x0001)
/* PCI Controller.
*/
typedef struct pci_ctlr {
u32 pci_omisr;
u32 pci_omimr;
u8 res1[8];
u32 pci_ifqpr;
u32 pci_ofqpr;
u8 res2[8];
u32 pci_imr0;
u32 pci_imr1;
u32 pci_omr0;
u32 pci_omr1;
u32 pci_odr;
u8 res3[4];
u32 pci_idr;
u8 res4[20];
u32 pci_imisr;
u32 pci_imimr;
u8 res5[24];
u32 pci_ifhpr;
u8 res6[4];
u32 pci_iftpr;
u8 res7[4];
u32 pci_iphpr;
u8 res8[4];
u32 pci_iptpr;
u8 res9[4];
u32 pci_ofhpr;
u8 res10[4];
u32 pci_oftpr;
u8 res11[4];
u32 pci_ophpr;
u8 res12[4];
u32 pci_optpr;
u8 res13[8];
u32 pci_mucr;
u8 res14[8];
u32 pci_qbar;
u8 res15[12];
u32 pci_dmamr0;
u32 pci_dmasr0;
u32 pci_dmacdar0;
u8 res16[4];
u32 pci_dmasar0;
u8 res17[4];
u32 pci_dmadar0;
u8 res18[4];
u32 pci_dmabcr0;
u32 pci_dmandar0;
u8 res19[86];
u32 pci_dmamr1;
u32 pci_dmasr1;
u32 pci_dmacdar1;
u8 res20[4];
u32 pci_dmasar1;
u8 res21[4];
u32 pci_dmadar1;
u8 res22[4];
u32 pci_dmabcr1;
u32 pci_dmandar1;
u8 res23[88];
u32 pci_dmamr2;
u32 pci_dmasr2;
u32 pci_dmacdar2;
u8 res24[4];
u32 pci_dmasar2;
u8 res25[4];
u32 pci_dmadar2;
u8 res26[4];
u32 pci_dmabcr2;
u32 pci_dmandar2;
u8 res27[88];
u32 pci_dmamr3;
u32 pci_dmasr3;
u32 pci_dmacdar3;
u8 res28[4];
u32 pci_dmasar3;
u8 res29[4];
u32 pci_dmadar3;
u8 res30[4];
u32 pci_dmabcr3;
u32 pci_dmandar3;
u8 res31[344];
u32 pci_potar0;
u8 res32[4];
u32 pci_pobar0;
u8 res33[4];
u32 pci_pocmr0;
u8 res34[4];
u32 pci_potar1;
u8 res35[4];
u32 pci_pobar1;
u8 res36[4];
u32 pci_pocmr1;
u8 res37[4];
u32 pci_potar2;
u8 res38[4];
u32 pci_pobar2;
u8 res39[4];
u32 pci_pocmr2;
u8 res40[50];
u32 pci_ptcr;
u32 pci_gpcr;
u32 pci_gcr;
u32 pci_esr;
u32 pci_emr;
u32 pci_ecr;
u32 pci_eacr;
u8 res41[4];
u32 pci_edcr;
u8 res42[4];
u32 pci_eccr;
u8 res43[44];
u32 pci_pitar1;
u8 res44[4];
u32 pci_pibar1;
u8 res45[4];
u32 pci_picmr1;
u8 res46[4];
u32 pci_pitar0;
u8 res47[4];
u32 pci_pibar0;
u8 res48[4];
u32 pci_picmr0;
u8 res49[4];
u32 pci_cfg_addr;
u32 pci_cfg_data;
u32 pci_int_ack;
u8 res50[756];
} pci_cpm2_t;
/* Interrupt Controller.
*/
typedef struct interrupt_controller {
u16 ic_sicr;
u8 res1[2];
u32 ic_sivec;
u32 ic_sipnrh;
u32 ic_sipnrl;
u32 ic_siprr;
u32 ic_scprrh;
u32 ic_scprrl;
u32 ic_simrh;
u32 ic_simrl;
u32 ic_siexr;
u8 res2[88];
} intctl_cpm2_t;
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
u32 car_sccr;
u8 res1[4];
u32 car_scmr;
u8 res2[4];
u32 car_rsr;
u32 car_rmr;
u8 res[104];
} car_cpm2_t;
/* Input/Output Port control/status registers.
* Names consistent with processor manual, although they are different
* from the original 8xx names.......
*/
typedef struct io_port {
u32 iop_pdira;
u32 iop_ppara;
u32 iop_psora;
u32 iop_podra;
u32 iop_pdata;
u8 res1[12];
u32 iop_pdirb;
u32 iop_pparb;
u32 iop_psorb;
u32 iop_podrb;
u32 iop_pdatb;
u8 res2[12];
u32 iop_pdirc;
u32 iop_pparc;
u32 iop_psorc;
u32 iop_podrc;
u32 iop_pdatc;
u8 res3[12];
u32 iop_pdird;
u32 iop_ppard;
u32 iop_psord;
u32 iop_podrd;
u32 iop_pdatd;
u8 res4[12];
} iop_cpm2_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
u8 cpmt_tgcr1;
u8 res1[3];
u8 cpmt_tgcr2;
u8 res2[11];
u16 cpmt_tmr1;
u16 cpmt_tmr2;
u16 cpmt_trr1;
u16 cpmt_trr2;
u16 cpmt_tcr1;
u16 cpmt_tcr2;
u16 cpmt_tcn1;
u16 cpmt_tcn2;
u16 cpmt_tmr3;
u16 cpmt_tmr4;
u16 cpmt_trr3;
u16 cpmt_trr4;
u16 cpmt_tcr3;
u16 cpmt_tcr4;
u16 cpmt_tcn3;
u16 cpmt_tcn4;
u16 cpmt_ter1;
u16 cpmt_ter2;
u16 cpmt_ter3;
u16 cpmt_ter4;
u8 res3[584];
} cpmtimer_cpm2_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
u8 res0[24];
u8 sdma_sdsr;
u8 res1[3];
u8 sdma_sdmr;
u8 res2[3];
u8 sdma_idsr1;
u8 res3[3];
u8 sdma_idmr1;
u8 res4[3];
u8 sdma_idsr2;
u8 res5[3];
u8 sdma_idmr2;
u8 res6[3];
u8 sdma_idsr3;
u8 res7[3];
u8 sdma_idmr3;
u8 res8[3];
u8 sdma_idsr4;
u8 res9[3];
u8 sdma_idmr4;
u8 res10[707];
} sdma_cpm2_t;
/* Fast controllers
*/
typedef struct fcc {
u32 fcc_gfmr;
u32 fcc_fpsmr;
u16 fcc_ftodr;
u8 res1[2];
u16 fcc_fdsr;
u8 res2[2];
u16 fcc_fcce;
u8 res3[2];
u16 fcc_fccm;
u8 res4[2];
u8 fcc_fccs;
u8 res5[3];
u8 fcc_ftirr_phy[4];
} fcc_t;
/* Fast controllers continued
*/
typedef struct fcc_c {
u32 fcc_firper;
u32 fcc_firer;
u32 fcc_firsr_hi;
u32 fcc_firsr_lo;
u8 fcc_gfemr;
u8 res1[15];
} fcc_c_t;
/* TC Layer
*/
typedef struct tclayer {
u16 tc_tcmode;
u16 tc_cdsmr;
u16 tc_tcer;
u16 tc_rcc;
u16 tc_tcmr;
u16 tc_fcc;
u16 tc_ccc;
u16 tc_icc;
u16 tc_tcc;
u16 tc_ecc;
u8 res1[12];
} tclayer_t;
/* I2C
*/
typedef struct i2c {
u8 i2c_i2mod;
u8 res1[3];
u8 i2c_i2add;
u8 res2[3];
u8 i2c_i2brg;
u8 res3[3];
u8 i2c_i2com;
u8 res4[3];
u8 i2c_i2cer;
u8 res5[3];
u8 i2c_i2cmr;
u8 res6[331];
} i2c_cpm2_t;
typedef struct scc { /* Serial communication channels */
u32 scc_gsmrl;
u32 scc_gsmrh;
u16 scc_psmr;
u8 res1[2];
u16 scc_todr;
u16 scc_dsr;
u16 scc_scce;
u8 res2[2];
u16 scc_sccm;
u8 res3;
u8 scc_sccs;
u8 res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
u8 res1[2];
u16 smc_smcmr;
u8 res2[2];
u8 smc_smce;
u8 res3[3];
u8 smc_smcm;
u8 res4[5];
} smc_t;
/* Serial Peripheral Interface.
*/
typedef struct spi_ctrl {
u16 spi_spmode;
u8 res1[4];
u8 spi_spie;
u8 res2[3];
u8 spi_spim;
u8 res3[2];
u8 spi_spcom;
u8 res4[82];
} spictl_cpm2_t;
/* CPM Mux.
*/
typedef struct cpmux {
u8 cmx_si1cr;
u8 res1;
u8 cmx_si2cr;
u8 res2;
u32 cmx_fcr;
u32 cmx_scr;
u8 cmx_smr;
u8 res3;
u16 cmx_uar;
u8 res4[16];
} cpmux_t;
/* SIRAM control
*/
typedef struct siram {
u16 si_amr;
u16 si_bmr;
u16 si_cmr;
u16 si_dmr;
u8 si_gmr;
u8 res1;
u8 si_cmdr;
u8 res2;
u8 si_str;
u8 res3;
u16 si_rsr;
} siramctl_t;
typedef struct mcc {
u16 mcc_mcce;
u8 res1[2];
u16 mcc_mccm;
u8 res2[2];
u8 mcc_mccf;
u8 res3[7];
} mcc_t;
typedef struct comm_proc {
u32 cp_cpcr;
u32 cp_rccr;
u8 res1[14];
u16 cp_rter;
u8 res2[2];
u16 cp_rtmr;
u16 cp_rtscr;
u8 res3[2];
u32 cp_rtsr;
u8 res4[12];
} cpm_cpm2_t;
/* USB Controller.
*/
typedef struct usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
u8 res1[1];
u16 usb_usep1;
u16 usb_usep2;
u16 usb_usep3;
u16 usb_usep4;
u8 res2[4];
u16 usb_usber;
u8 res3[2];
u16 usb_usbmr;
u8 usb_usbs;
u8 res4[7];
} usb_cpm2_t;
/* ...and the whole thing wrapped up....
*/
typedef struct immap {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
#define im_dprambase im_dpram1
u8 im_dpram1[16*1024];
u8 res1[16*1024];
u8 im_dpram2[4*1024];
u8 res2[8*1024];
u8 im_dpram3[4*1024];
u8 res3[16*1024];
sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
memctl_cpm2_t im_memctl; /* Memory Controller */
sit_cpm2_t im_sit; /* System Integration Timers */
pci_cpm2_t im_pci; /* PCI Controller */
intctl_cpm2_t im_intctl; /* Interrupt Controller */
car_cpm2_t im_clkrst; /* Clocks and reset */
iop_cpm2_t im_ioport; /* IO Port control/status */
cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
sdma_cpm2_t im_sdma; /* SDMA control/status */
fcc_t im_fcc[3]; /* Three FCCs */
u8 res4z[32];
fcc_c_t im_fcc_c[3]; /* Continued FCCs */
u8 res4[32];
tclayer_t im_tclayer[8]; /* Eight TCLayers */
u16 tc_tcgsr;
u16 tc_tcger;
/* First set of baud rate generators.
*/
u8 res[236];
u32 im_brgc5;
u32 im_brgc6;
u32 im_brgc7;
u32 im_brgc8;
u8 res5[608];
i2c_cpm2_t im_i2c; /* I2C control/status */
cpm_cpm2_t im_cpm; /* Communication processor */
/* Second set of baud rate generators.
*/
u32 im_brgc1;
u32 im_brgc2;
u32 im_brgc3;
u32 im_brgc4;
scc_t im_scc[4]; /* Four SCCs */
smc_t im_smc[2]; /* Couple of SMCs */
spictl_cpm2_t im_spi; /* A SPI */
cpmux_t im_cpmux; /* CPM clock route mux */
siramctl_t im_siramctl1; /* First SI RAM Control */
mcc_t im_mcc1; /* First MCC */
siramctl_t im_siramctl2; /* Second SI RAM Control */
mcc_t im_mcc2; /* Second MCC */
usb_cpm2_t im_usb; /* USB Controller */
u8 res6[1153];
u16 im_si1txram[256];
u8 res7[512];
u16 im_si1rxram[256];
u8 res8[512];
u16 im_si2txram[256];
u8 res9[512];
u16 im_si2rxram[256];
u8 res10[512];
u8 res11[4096];
} cpm2_map_t;
extern cpm2_map_t *cpm2_immr;
#endif /* __IMMAP_CPM2__ */
#endif /* __KERNEL__ */
include/asm-ppc/irq.h
View file @ def37267
......@@ -177,17 +177,55 @@ static __inline__ int irq_canonicalize(int irq)
*/
#define NR_SIU_INTS 64
/* There are many more than these, we will add them as we need them.
*/
#define SIU_INT_ERROR ((uint)0x00)
#define SIU_INT_I2C ((uint)0x01)
#define SIU_INT_SPI ((uint)0x02)
#define SIU_INT_RISC ((uint)0x03)
#define SIU_INT_SMC1 ((uint)0x04)
#define SIU_INT_SMC2 ((uint)0x05)
#define SIU_INT_IDMA1 ((uint)0x06)
#define SIU_INT_IDMA2 ((uint)0x07)
#define SIU_INT_IDMA3 ((uint)0x08)
#define SIU_INT_IDMA4 ((uint)0x09)
#define SIU_INT_SDMA ((uint)0x0a)
#define SIU_INT_TIMER1 ((uint)0x0c)
#define SIU_INT_TIMER2 ((uint)0x0d)
#define SIU_INT_TIMER3 ((uint)0x0e)
#define SIU_INT_TIMER4 ((uint)0x0f)
#define SIU_INT_TMCNT ((uint)0x10)
#define SIU_INT_PIT ((uint)0x11)
#define SIU_INT_IRQ1 ((uint)0x13)
#define SIU_INT_IRQ2 ((uint)0x14)
#define SIU_INT_IRQ3 ((uint)0x15)
#define SIU_INT_IRQ4 ((uint)0x16)
#define SIU_INT_IRQ5 ((uint)0x17)
#define SIU_INT_IRQ6 ((uint)0x18)
#define SIU_INT_IRQ7 ((uint)0x19)
#define SIU_INT_FCC1 ((uint)0x20)
#define SIU_INT_FCC2 ((uint)0x21)
#define SIU_INT_FCC3 ((uint)0x22)
#define SIU_INT_MCC1 ((uint)0x24)
#define SIU_INT_MCC2 ((uint)0x25)
#define SIU_INT_SCC1 ((uint)0x28)
#define SIU_INT_SCC2 ((uint)0x29)
#define SIU_INT_SCC3 ((uint)0x2a)
#define SIU_INT_SCC4 ((uint)0x2b)
#define SIU_INT_PC15 ((uint)0x30)
#define SIU_INT_PC14 ((uint)0x31)
#define SIU_INT_PC13 ((uint)0x32)
#define SIU_INT_PC12 ((uint)0x33)
#define SIU_INT_PC11 ((uint)0x34)
#define SIU_INT_PC10 ((uint)0x35)
#define SIU_INT_PC9 ((uint)0x36)
#define SIU_INT_PC8 ((uint)0x37)
#define SIU_INT_PC7 ((uint)0x38)
#define SIU_INT_PC6 ((uint)0x39)
#define SIU_INT_PC5 ((uint)0x3a)
#define SIU_INT_PC4 ((uint)0x3b)
#define SIU_INT_PC3 ((uint)0x3c)
#define SIU_INT_PC2 ((uint)0x3d)
#define SIU_INT_PC1 ((uint)0x3e)
#define SIU_INT_PC0 ((uint)0x3f)
#endif /* CONFIG_8260 */
......
include/asm-ppc/ppcboot.h
View file @ def37267
......@@ -52,7 +52,7 @@ typedef struct bd_info {
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
#if defined(CONFIG_8xx) || defined(CONFIG_CPM2)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
......@@ -61,7 +61,7 @@ typedef struct bd_info {
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#if defined(CONFIG_8260)
#if defined(CONFIG_CPM2)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
......
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