ppc64: we use rtas for all config accesses, so remove the unecessary ioremaps

arch/ppc64/kernel/iSeries_pci.c

@@ -55,7 +55,6 @@ extern int    global_phb_number;
 extern int    panic_timeout;
 
 extern struct device_node *allnodes;
-extern unsigned long phb_tce_table_init(struct pci_controller *phb);
 extern unsigned long iSeries_Base_Io_Memory;    
 
 extern struct pci_ops iSeries_pci_ops;

arch/ppc64/kernel/pSeries_pci.c

@@ -45,15 +45,13 @@
 #include "open_pic.h"
 #include "pci.h"
 
-extern struct device_node *allnodes;
-
 /*******************************************************************
  * Forward declares of prototypes. 
  *******************************************************************/
-unsigned long find_and_init_phbs(void);
-struct pci_controller* alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words) ;
-void pSeries_pcibios_fixup(void);
-static int rtas_fake_read(struct device_node *dn, int offset, int nbytes, unsigned long *returnval);
+struct pci_controller *alloc_phb(struct device_node *dev, char *model,
+				 unsigned int addr_size_words) ;
+static int rtas_fake_read(struct device_node *dn, int offset, int nbytes,
+			  unsigned long *returnval);
 
 /* RTAS tokens */
 static int read_pci_config;
@@ -467,33 +465,27 @@ alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words)
 	* Python
 	***************************************************************/
 	if (strstr(model, "Python")) {
+		unsigned long chip_regs;
+		volatile u32 *tmp, i;
+
 		PPCDBG(PPCDBG_PHBINIT, "\tCreate python\n");
-	        phb = pci_alloc_pci_controller("PHB PY",phb_type_python);
-		if (phb == NULL) return NULL;
-	
-       		phb->cfg_addr = (volatile unsigned long *) 
-			ioremap(reg_struct.address + 0xf8000, PAGE_SIZE);
-		PPCDBG(PPCDBG_PHBINIT, "\tcfg_addr_r = 0x%lx\n", 
-		       reg_struct.address + 0xf8000);
-		PPCDBG(PPCDBG_PHBINIT, "\tcfg_addr_v = 0x%lx\n", 
-		       phb->cfg_addr);
-		phb->cfg_data = (char*)(phb->cfg_addr + 0x02);
-       		phb->phb_regs = (volatile unsigned long *) 
-			ioremap(reg_struct.address + 0xf7000, PAGE_SIZE);
+
+		phb = pci_alloc_pci_controller("PHB PY", phb_type_python);
+		if (phb == NULL)
+			return NULL;
+
 		/* Python's register file is 1 MB in size. */
-		phb->chip_regs = ioremap(reg_struct.address & ~(0xfffffUL), 
+		chip_regs = ioremap(reg_struct.address & ~(0xfffffUL),
 				    0x100000); 
 
 		/* 
 		 * Firmware doesn't always clear this bit which is critical
 		 * for good performance - Anton
 		 */
-		{
-			volatile u32 *tmp, i;
 
 #define PRG_CL_RESET_VALID 0x00010000
 
-			tmp = (u32 *)((unsigned long)phb->chip_regs + 0xf6030);
+		tmp = (u32 *)((unsigned long)chip_regs + 0xf6030);
 
 		if (*tmp & PRG_CL_RESET_VALID) {
 			printk("Python workaround: ");
@@ -505,7 +497,6 @@ alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words)
 			i = *tmp;
 			printk("reg0: %x\n", i);
 		}
-		}
 
 	/***************************************************************
 	* Speedwagon
@@ -514,28 +505,12 @@ alloc_phb(struct device_node *dev, char *model, unsigned int addr_size_words)
 	} else if ((strstr(model, "Speedwagon")) || 
 		   (strstr(model, "Winnipeg"))) {
 		PPCDBG(PPCDBG_PHBINIT, "\tCreate speedwagon\n");
-	        phb = pci_alloc_pci_controller("PHB SW",phb_type_speedwagon);
-		if (phb == NULL) return NULL;
-
-		if (naca->platform == PLATFORM_PSERIES) {
-			phb->cfg_addr = (volatile unsigned long *) 
-			  ioremap(reg_struct.address + 0x140, PAGE_SIZE);
-			phb->cfg_data = (char*)(phb->cfg_addr - 0x02); /* minus is correct */
-			phb->phb_regs = (volatile unsigned long *) 
-			  ioremap(reg_struct.address, PAGE_SIZE);
-			/* Speedwagon's register file is 1 MB in size. */
-			phb->chip_regs = ioremap(reg_struct.address & ~(0xfffffUL),
-						 0x100000); 
-			PPCDBG(PPCDBG_PHBINIT, "\tmapping chip_regs from 0x%lx -> 0x%lx\n", 
-			       reg_struct.address & 0xfffff, phb->chip_regs);
-		} else {
-			phb->cfg_addr = NULL;
-			phb->cfg_data = NULL; 
-			phb->phb_regs = NULL;
-			phb->chip_regs = NULL;
-		}
+	        phb = pci_alloc_pci_controller("PHB SW", phb_type_speedwagon);
+		if (phb == NULL)
+			return NULL;
 
 		phb->local_number = ((reg_struct.address >> 12) & 0xf) - 0x8;
+
 	/***************************************************************
 	* Trying to build a known just gets the code in trouble.
 	***************************************************************/

arch/ppc64/kernel/pci.c

@@ -924,12 +924,6 @@ void dumpPci_Controller(struct pci_controller* phb)
 		udbg_printf("\tpci_mem_offset= 0x%016LX\n", phb->pci_mem_offset);
 		udbg_printf("\tpci_io_offset = 0x%016LX\n", phb->pci_io_offset);
 
-		udbg_printf("\tcfg_addr      = 0x%016LX\n", phb->cfg_addr);
-		udbg_printf("\tcfg_data      = 0x%016LX\n", phb->cfg_data);
-		udbg_printf("\tphb_regs      = 0x%016LX\n", phb->phb_regs);
-		udbg_printf("\tchip_regs     = 0x%016LX\n", phb->chip_regs);
-
-
 		udbg_printf("\tResources\n");
 		dumpResources(&phb->io_resource);
 		if (phb->mem_resource_count >  0) dumpResources(&phb->mem_resources[0]);

arch/ppc64/kernel/pci_dma.c

@@ -1438,69 +1438,6 @@ void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems,
 }
 #endif
 
-/*
- * phb_tce_table_init
- * 
- * Function: Display TCE config registers.  Could be easily changed
- *           to initialize the hardware to use TCEs.
- */
-unsigned long phb_tce_table_init(struct pci_controller *phb) {
-	unsigned int r, cfg_rw, i;	
-	unsigned long r64;	
-	phandle node;
-
-	PPCDBG(PPCDBG_TCE, "phb_tce_table_init: start.\n"); 
-
-	node = ((struct device_node *)(phb->arch_data))->node;
-
-	PPCDBG(PPCDBG_TCEINIT, "\tphb            = 0x%lx\n", phb); 
-	PPCDBG(PPCDBG_TCEINIT, "\tphb->type      = 0x%lx\n", phb->type); 
-	PPCDBG(PPCDBG_TCEINIT, "\tphb->phb_regs  = 0x%lx\n", phb->phb_regs); 
-	PPCDBG(PPCDBG_TCEINIT, "\tphb->chip_regs = 0x%lx\n", phb->chip_regs); 
-	PPCDBG(PPCDBG_TCEINIT, "\tphb: node      = 0x%lx\n", node);
-	PPCDBG(PPCDBG_TCEINIT, "\tphb->arch_data = 0x%lx\n", phb->arch_data); 
-
-	i = 0;
-	while(of_tce_table[i].node) {
-		if(of_tce_table[i].node == node) {
-			if(phb->type == phb_type_python) {
-				r = *(((unsigned int *)phb->phb_regs) + (0xf10>>2)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR(low)    = 0x%x\n", r);
-				r = *(((unsigned int *)phb->phb_regs) + (0xf00>>2)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR(high)   = 0x%x\n", r);
-				r = *(((unsigned int *)phb->phb_regs) + (0xfd0>>2)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tPHB cfg(rw) = 0x%x\n", r);
-				break;
-			} else if(phb->type == phb_type_speedwagon) {
-				r64 = *(((unsigned long *)phb->chip_regs) + 
-					(0x800>>3)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tNCFG    = 0x%lx\n", r64);
-				r64 = *(((unsigned long *)phb->chip_regs) + 
-					(0x580>>3)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR0    = 0x%lx\n", r64);
-				r64 = *(((unsigned long *)phb->chip_regs) + 
-					(0x588>>3)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR1    = 0x%lx\n", r64);
-				r64 = *(((unsigned long *)phb->chip_regs) + 
-					(0x590>>3)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR2    = 0x%lx\n", r64);
-				r64 = *(((unsigned long *)phb->chip_regs) + 
-					(0x598>>3)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tTAR3    = 0x%lx\n", r64);
-				cfg_rw = *(((unsigned int *)phb->chip_regs) + 
-					   ((0x160 +
-					     (((phb->local_number)+8)<<12))>>2)); 
-				PPCDBG(PPCDBG_TCEINIT, "\tcfg_rw = 0x%x\n", cfg_rw);
-			}
-		}
-		i++;
-	}
-
-	PPCDBG(PPCDBG_TCEINIT, "phb_tce_table_init: done\n"); 
-
-	return(0); 
-}
-
 /* These are called very early. */
 void tce_init_pSeries(void)
 {

include/asm-ppc64/pci-bridge.h

@@ -57,10 +57,6 @@ struct pci_controller {
 	unsigned long pci_io_offset;
 
 	struct pci_ops *ops;
-	volatile unsigned long *cfg_addr;
-	volatile unsigned char *cfg_data;
-	volatile unsigned long *phb_regs;
-	volatile unsigned long *chip_regs;
 
 	/* Currently, we limit ourselves to 1 IO range and 3 mem
 	 * ranges since the common pci_bus structure can't handle more
@@ -70,27 +66,11 @@ struct pci_controller {
 	int mem_resource_count;
 	int global_number;		
 	int local_number;		
-	int    system_bus_number;	
 	unsigned long buid;
 	unsigned long dma_window_base_cur;
 	unsigned long dma_window_size;
 };
 
-
-/* This version handles the new Uni-N host bridge, the iobase is now
- * a per-device thing. I also added the memory base so PReP can
- * be fixed to return 0xc0000000 (I didn't actually implement it)
- *
- * pci_dev_io_base() returns either a virtual (ioremap'ed) address or
- * a physical address. In-kernel clients will use logical while the
- * sys_pciconfig_iobase syscall returns a physical one to userland.
- */
-void *pci_dev_io_base(unsigned char bus, unsigned char devfn, int physical);
-void *pci_dev_mem_base(unsigned char bus, unsigned char devfn);
-
-/* Returns the root-bridge number (Uni-N number) of a device */
-int pci_dev_root_bridge(unsigned char bus, unsigned char devfn);
-
 /*
  * pci_device_loc returns the bus number and device/function number
  * for a device on a PCI bus, given its device_node struct.
@@ -99,16 +79,5 @@ int pci_dev_root_bridge(unsigned char bus, unsigned char devfn);
 int pci_device_loc(struct device_node *dev, unsigned char *bus_ptr,
 		   unsigned char *devfn_ptr);
 
-struct bridge_data {
-	volatile unsigned int *cfg_addr;
-	volatile unsigned char *cfg_data;
-	void *io_base;		/* virtual */
-	unsigned long io_base_phys;
-	int bus_number;
-	int max_bus;
-	struct bridge_data *next;
-	struct device_node *node;
-};
-
 #endif
 #endif /* __KERNEL__ */