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nexedi
linux
Commits
e368b510
Commit
e368b510
authored
Jun 12, 2013
by
Vinod Koul
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dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically
Signed-off-by:
Vinod Koul
<
vinod.koul@intel.com
>
parent
fed42c19
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2
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8 additions
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9 deletions
+8
-9
drivers/dma/dw/Kconfig
drivers/dma/dw/Kconfig
+2
-9
drivers/dma/dw/regs.h
drivers/dma/dw/regs.h
+6
-0
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drivers/dma/dw/Kconfig
View file @
e368b510
...
@@ -10,6 +10,7 @@ config DW_DMAC_CORE
...
@@ -10,6 +10,7 @@ config DW_DMAC_CORE
config DW_DMAC
config DW_DMAC
tristate "Synopsys DesignWare AHB DMA platform driver"
tristate "Synopsys DesignWare AHB DMA platform driver"
select DW_DMAC_CORE
select DW_DMAC_CORE
select DW_DMAC_BIG_ENDIAN_IO if AVR32
default y if CPU_AT32AP7000
default y if CPU_AT32AP7000
help
help
Support the Synopsys DesignWare AHB DMA controller. This
Support the Synopsys DesignWare AHB DMA controller. This
...
@@ -25,12 +26,4 @@ config DW_DMAC_PCI
...
@@ -25,12 +26,4 @@ config DW_DMAC_PCI
Intel Medfield has integrated this GPDMA controller.
Intel Medfield has integrated this GPDMA controller.
config DW_DMAC_BIG_ENDIAN_IO
config DW_DMAC_BIG_ENDIAN_IO
bool "Use big endian I/O register access"
bool
default y if AVR32
depends on DW_DMAC_CORE
help
Say yes here to use big endian I/O access when reading and writing
to the DMA controller registers. This is needed on some platforms,
like the Atmel AVR32 architecture.
If unsure, use the default setting.
drivers/dma/dw/regs.h
View file @
e368b510
...
@@ -101,6 +101,12 @@ struct dw_dma_regs {
...
@@ -101,6 +101,12 @@ struct dw_dma_regs {
u32
DW_PARAMS
;
u32
DW_PARAMS
;
};
};
/*
* Big endian I/O access when reading and writing to the DMA controller
* registers. This is needed on some platforms, like the Atmel AVR32
* architecture.
*/
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
#define dma_readl_native ioread32be
#define dma_readl_native ioread32be
#define dma_writel_native iowrite32be
#define dma_writel_native iowrite32be
...
...
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