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Commit e3b334c9 authored by Russell King's avatar Russell King
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Add more big endian support to ARM, specifically stat structures and 

checksum functions.
parent 050bfcfe
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Showing with 104 additions and 76 deletions
arch/arm/lib/csumpartial.S
View file @ e3b334c9
...@@ -41,7 +41,7 @@ td3 .req lr ...@@ -41,7 +41,7 @@ td3 .req lr
tst buf, #1 @ odd address? tst buf, #1 @ odd address?
ldrneb td0, [buf], #1 ldrneb td0, [buf], #1
subne len, len, #1 subne len, len, #1
adcnes sum, sum, td0, lsl #8 adcnes sum, sum, td0, lsl #byte(1)
.less4: tst len, #6 .less4: tst len, #6
beq .less8_byte beq .less8_byte
...@@ -56,7 +56,11 @@ td3 .req lr ...@@ -56,7 +56,11 @@ td3 .req lr
ldrb td0, [buf], #1 ldrb td0, [buf], #1
ldrb td3, [buf], #1 ldrb td3, [buf], #1
sub len, len, #2 sub len, len, #2
#ifndef __ARMEB__
orr td0, td0, td3, lsl #8 orr td0, td0, td3, lsl #8
#else
orr td0, td3, td0, lsl #8
#endif
#endif #endif
adcs sum, sum, td0 adcs sum, sum, td0
tst len, #6 tst len, #6
...@@ -64,7 +68,7 @@ td3 .req lr ...@@ -64,7 +68,7 @@ td3 .req lr
.less8_byte: tst len, #1 @ odd number of bytes .less8_byte: tst len, #1 @ odd number of bytes
ldrneb td0, [buf], #1 @ include last byte ldrneb td0, [buf], #1 @ include last byte
adcnes sum, sum, td0 @ update checksum adcnes sum, sum, td0, lsl #byte(0) @ update checksum
.done: adc r0, sum, #0 @ collect up the last carry .done: adc r0, sum, #0 @ collect up the last carry
ldr td0, [sp], #4 ldr td0, [sp], #4
...@@ -76,7 +80,7 @@ td3 .req lr ...@@ -76,7 +80,7 @@ td3 .req lr
.not_aligned: tst buf, #1 @ odd address .not_aligned: tst buf, #1 @ odd address
ldrneb td0, [buf], #1 @ make even ldrneb td0, [buf], #1 @ make even
subne len, len, #1 subne len, len, #1
adcnes sum, sum, td0, lsl #8 @ update checksum adcnes sum, sum, td0, lsl #byte(1) @ update checksum
tst buf, #2 @ 32-bit aligned? tst buf, #2 @ 32-bit aligned?
#ifdef __ARM_ARCH_4__ #ifdef __ARM_ARCH_4__
...@@ -86,7 +90,11 @@ td3 .req lr ...@@ -86,7 +90,11 @@ td3 .req lr
ldrneb td0, [buf], #1 ldrneb td0, [buf], #1
ldrneb ip, [buf], #1 ldrneb ip, [buf], #1
subne len, len, #2 subne len, len, #2
#ifndef __ARMEB__
orrne td0, td0, ip, lsl #8 orrne td0, td0, ip, lsl #8
#else
orrne td0, ip, td0, lsl #8
#endif
#endif #endif
adcnes sum, sum, td0 @ update checksum adcnes sum, sum, td0 @ update checksum
mov pc, lr mov pc, lr
......
arch/arm/lib/csumpartialcopygeneric.S
View file @ e3b334c9
...@@ -36,16 +36,16 @@ sum .req r3 ...@@ -36,16 +36,16 @@ sum .req r3
load1b ip load1b ip
sub len, len, #1 sub len, len, #1
adcs sum, sum, ip, lsl #8 @ update checksum adcs sum, sum, ip, lsl #byte(1) @ update checksum
strb ip, [dst], #1 strb ip, [dst], #1
tst dst, #2 tst dst, #2
moveq pc, lr @ dst is now 32bit aligned moveq pc, lr @ dst is now 32bit aligned
.dst_16bit: load2b r8, ip .dst_16bit: load2b r8, ip
sub len, len, #2 sub len, len, #2
adcs sum, sum, r8 adcs sum, sum, r8, lsl #byte(0)
strb r8, [dst], #1 strb r8, [dst], #1
adcs sum, sum, ip, lsl #8 adcs sum, sum, ip, lsl #byte(1)
strb ip, [dst], #1 strb ip, [dst], #1
mov pc, lr @ dst is now 32bit aligned mov pc, lr @ dst is now 32bit aligned
...@@ -63,16 +63,16 @@ sum .req r3 ...@@ -63,16 +63,16 @@ sum .req r3
/* Align dst */ /* Align dst */
load1b ip load1b ip
sub len, len, #1 sub len, len, #1
adcs sum, sum, ip, lsl #8 @ update checksum adcs sum, sum, ip, lsl #byte(1) @ update checksum
strb ip, [dst], #1 strb ip, [dst], #1
tst len, #6 tst len, #6
beq .less8_byteonly beq .less8_byteonly
1: load2b r8, ip 1: load2b r8, ip
sub len, len, #2 sub len, len, #2
adcs sum, sum, r8 adcs sum, sum, r8, lsl #byte(0)
strb r8, [dst], #1 strb r8, [dst], #1
adcs sum, sum, ip, lsl #8 adcs sum, sum, ip, lsl #byte(1)
strb ip, [dst], #1 strb ip, [dst], #1
.less8_aligned: tst len, #6 .less8_aligned: tst len, #6
bne 1b bne 1b
...@@ -80,7 +80,7 @@ sum .req r3 ...@@ -80,7 +80,7 @@ sum .req r3
tst len, #1 tst len, #1
beq .done beq .done
load1b r8 load1b r8
adcs sum, sum, r8 @ update checksum adcs sum, sum, r8, lsl #byte(0) @ update checksum
strb r8, [dst], #1 strb r8, [dst], #1
b .done b .done
...@@ -137,18 +137,19 @@ FN_ENTRY ...@@ -137,18 +137,19 @@ FN_ENTRY
4: ands len, len, #3 4: ands len, len, #3
beq .done beq .done
load1l r4 load1l r5
tst len, #2 tst len, #2
mov r4, r5, lsr #byte(0)
beq .exit beq .exit
adcs sum, sum, r4, lsl #16 adcs sum, sum, r5, push #16
strb r4, [dst], #1 strb r4, [dst], #1
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(1)
strb r4, [dst], #1 strb r4, [dst], #1
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(2)
.exit: tst len, #1 .exit: tst len, #1
strneb r4, [dst], #1 strneb r4, [dst], #1
andne r4, r4, #255 andne r4, r4, #255
adcnes sum, sum, r4 adcnes sum, sum, r4, lsl #byte(0)
/* /*
* If the dst pointer was not 16-bit aligned, we * If the dst pointer was not 16-bit aligned, we
...@@ -167,27 +168,27 @@ FN_ENTRY ...@@ -167,27 +168,27 @@ FN_ENTRY
adc sum, sum, #0 @ include C from dst alignment adc sum, sum, #0 @ include C from dst alignment
and ip, src, #3 and ip, src, #3
bic src, src, #3 bic src, src, #3
load1l r4 load1l r5
cmp ip, #2 cmp ip, #2
beq .src2_aligned beq .src2_aligned
bhi .src3_aligned bhi .src3_aligned
mov r4, r4, lsr #8 @ C = 0 mov r4, r5, pull #8 @ C = 0
bics ip, len, #15 bics ip, len, #15
beq 2f beq 2f
1: load4l r5, r6, r7, r8 1: load4l r5, r6, r7, r8
orr r4, r4, r5, lsl #24 orr r4, r4, r5, push #24
mov r5, r5, lsr #8 mov r5, r5, pull #8
orr r5, r5, r6, lsl #24 orr r5, r5, r6, push #24
mov r6, r6, lsr #8 mov r6, r6, pull #8
orr r6, r6, r7, lsl #24 orr r6, r6, r7, push #24
mov r7, r7, lsr #8 mov r7, r7, pull #8
orr r7, r7, r8, lsl #24 orr r7, r7, r8, push #24
stmia dst!, {r4, r5, r6, r7} stmia dst!, {r4, r5, r6, r7}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
adcs sum, sum, r6 adcs sum, sum, r6
adcs sum, sum, r7 adcs sum, sum, r7
mov r4, r8, lsr #8 mov r4, r8, pull #8
sub ip, ip, #16 sub ip, ip, #16
teq ip, #0 teq ip, #0
bne 1b bne 1b
...@@ -196,49 +197,50 @@ FN_ENTRY ...@@ -196,49 +197,50 @@ FN_ENTRY
tst ip, #8 tst ip, #8
beq 3f beq 3f
load2l r5, r6 load2l r5, r6
orr r4, r4, r5, lsl #24 orr r4, r4, r5, push #24
mov r5, r5, lsr #8 mov r5, r5, pull #8
orr r5, r5, r6, lsl #24 orr r5, r5, r6, push #24
stmia dst!, {r4, r5} stmia dst!, {r4, r5}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
mov r4, r6, lsr #8 mov r4, r6, pull #8
tst ip, #4 tst ip, #4
beq 4f beq 4f
3: load1l r5 3: load1l r5
orr r4, r4, r5, lsl #24 orr r4, r4, r5, push #24
str r4, [dst], #4 str r4, [dst], #4
adcs sum, sum, r4 adcs sum, sum, r4
mov r4, r5, lsr #8
4: ands len, len, #3 4: ands len, len, #3
beq .done beq .done
mov r4, r5, lsr #byte(1)
tst len, #2 tst len, #2
beq .exit beq .exit
adcs sum, sum, r4, lsl #16 bic r5, r5, #0xff << byte(0)
adcs sum, sum, r5, push #8
strb r4, [dst], #1 strb r4, [dst], #1
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(2)
strb r4, [dst], #1 strb r4, [dst], #1
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(3)
b .exit b .exit
.src2_aligned: mov r4, r4, lsr #16 .src2_aligned: mov r4, r5, pull #16
adds sum, sum, #0 adds sum, sum, #0
bics ip, len, #15 bics ip, len, #15
beq 2f beq 2f
1: load4l r5, r6, r7, r8 1: load4l r5, r6, r7, r8
orr r4, r4, r5, lsl #16 orr r4, r4, r5, push #16
mov r5, r5, lsr #16 mov r5, r5, pull #16
orr r5, r5, r6, lsl #16 orr r5, r5, r6, push #16
mov r6, r6, lsr #16 mov r6, r6, pull #16
orr r6, r6, r7, lsl #16 orr r6, r6, r7, push #16
mov r7, r7, lsr #16 mov r7, r7, pull #16
orr r7, r7, r8, lsl #16 orr r7, r7, r8, push #16
stmia dst!, {r4, r5, r6, r7} stmia dst!, {r4, r5, r6, r7}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
adcs sum, sum, r6 adcs sum, sum, r6
adcs sum, sum, r7 adcs sum, sum, r7
mov r4, r8, lsr #16 mov r4, r8, pull #16
sub ip, ip, #16 sub ip, ip, #16
teq ip, #0 teq ip, #0
bne 1b bne 1b
...@@ -247,51 +249,51 @@ FN_ENTRY ...@@ -247,51 +249,51 @@ FN_ENTRY
tst ip, #8 tst ip, #8
beq 3f beq 3f
load2l r5, r6 load2l r5, r6
orr r4, r4, r5, lsl #16 orr r4, r4, r5, push #16
mov r5, r5, lsr #16 mov r5, r5, pull #16
orr r5, r5, r6, lsl #16 orr r5, r5, r6, push #16
stmia dst!, {r4, r5} stmia dst!, {r4, r5}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
mov r4, r6, lsr #16 mov r4, r6, pull #16
tst ip, #4 tst ip, #4
beq 4f beq 4f
3: load1l r5 3: load1l r5
orr r4, r4, r5, lsl #16 orr r4, r4, r5, push #16
str r4, [dst], #4 str r4, [dst], #4
adcs sum, sum, r4 adcs sum, sum, r4
mov r4, r5, lsr #16
4: ands len, len, #3 4: ands len, len, #3
beq .done beq .done
mov r4, r5, lsr #byte(2)
tst len, #2 tst len, #2
beq .exit beq .exit
adcs sum, sum, r4, lsl #16 adcs sum, sum, r5, pull #16
strb r4, [dst], #1 strb r4, [dst], #1
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(3)
strb r4, [dst], #1 strb r4, [dst], #1
tst len, #1 tst len, #1
beq .done beq .done
load1b r4 load1b r4
b .exit b .exit
.src3_aligned: mov r4, r4, lsr #24 .src3_aligned: mov r4, r5, pull #24
adds sum, sum, #0 adds sum, sum, #0
bics ip, len, #15 bics ip, len, #15
beq 2f beq 2f
1: load4l r5, r6, r7, r8 1: load4l r5, r6, r7, r8
orr r4, r4, r5, lsl #8 orr r4, r4, r5, push #8
mov r5, r5, lsr #24 mov r5, r5, pull #24
orr r5, r5, r6, lsl #8 orr r5, r5, r6, push #8
mov r6, r6, lsr #24 mov r6, r6, pull #24
orr r6, r6, r7, lsl #8 orr r6, r6, r7, push #8
mov r7, r7, lsr #24 mov r7, r7, pull #24
orr r7, r7, r8, lsl #8 orr r7, r7, r8, push #8
stmia dst!, {r4, r5, r6, r7} stmia dst!, {r4, r5, r6, r7}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
adcs sum, sum, r6 adcs sum, sum, r6
adcs sum, sum, r7 adcs sum, sum, r7
mov r4, r8, lsr #24 mov r4, r8, pull #24
sub ip, ip, #16 sub ip, ip, #16
teq ip, #0 teq ip, #0
bne 1b bne 1b
...@@ -300,28 +302,29 @@ FN_ENTRY ...@@ -300,28 +302,29 @@ FN_ENTRY
tst ip, #8 tst ip, #8
beq 3f beq 3f
load2l r5, r6 load2l r5, r6
orr r4, r4, r5, lsl #8 orr r4, r4, r5, push #8
mov r5, r5, lsr #24 mov r5, r5, pull #24
orr r5, r5, r6, lsl #8 orr r5, r5, r6, push #8
stmia dst!, {r4, r5} stmia dst!, {r4, r5}
adcs sum, sum, r4 adcs sum, sum, r4
adcs sum, sum, r5 adcs sum, sum, r5
mov r4, r6, lsr #24 mov r4, r6, pull #24
tst ip, #4 tst ip, #4
beq 4f beq 4f
3: load1l r5 3: load1l r5
orr r4, r4, r5, lsl #8 orr r4, r4, r5, push #8
str r4, [dst], #4 str r4, [dst], #4
adcs sum, sum, r4 adcs sum, sum, r4
mov r4, r5, lsr #24
4: ands len, len, #3 4: ands len, len, #3
beq .done beq .done
mov r4, r5, lsr #byte(3)
tst len, #2 tst len, #2
beq .exit beq .exit
adcs sum, sum, r4, lsl #16 adcs sum, sum, r5, pull #24
strb r4, [dst], #1 strb r4, [dst], #1
load1l r4 load1l r5
mov r4, r5, lsr #byte(0)
strb r4, [dst], #1 strb r4, [dst], #1
adcs sum, sum, r4, lsl #24 adcs sum, sum, r4, push #24
mov r4, r4, lsr #8 mov r4, r5, lsr #byte(1)
b .exit b .exit
include/asm-arm/stat.h
View file @ e3b334c9
...@@ -42,8 +42,14 @@ struct stat { ...@@ -42,8 +42,14 @@ struct stat {
* insane amounts of padding around dev_t's. * insane amounts of padding around dev_t's.
*/ */
struct stat64 { struct stat64 {
#if defined(__ARMEB__)
unsigned char __pad0b[6];
unsigned short st_dev; unsigned short st_dev;
unsigned char __pad0[10]; #else
unsigned short st_dev;
unsigned char __pad0b[6];
#endif
unsigned char __pad0[4];
#define STAT64_HAS_BROKEN_ST_INO 1 #define STAT64_HAS_BROKEN_ST_INO 1
unsigned long __st_ino; unsigned long __st_ino;
...@@ -53,14 +59,25 @@ struct stat64 { ...@@ -53,14 +59,25 @@ struct stat64 {
unsigned long st_uid; unsigned long st_uid;
unsigned long st_gid; unsigned long st_gid;
#if defined(__ARMEB__)
unsigned char __pad3b[6];
unsigned short st_rdev;
#else /* Must be little */
unsigned short st_rdev; unsigned short st_rdev;
unsigned char __pad3[10]; unsigned char __pad3b[6];
#endif
unsigned char __pad3[4];
long long st_size; long long st_size;
unsigned long st_blksize; unsigned long st_blksize;
#if defined(__ARMEB__)
unsigned long __pad4; /* Future possible st_blocks hi bits */
unsigned long st_blocks; /* Number 512-byte blocks allocated. */
#else /* Must be little */
unsigned long st_blocks; /* Number 512-byte blocks allocated. */ unsigned long st_blocks; /* Number 512-byte blocks allocated. */
unsigned long __pad4; /* future possible st_blocks high bits */ unsigned long __pad4; /* Future possible st_blocks hi bits */
#endif
unsigned long st_atime; unsigned long st_atime;
unsigned long __pad5; unsigned long __pad5;
......
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