drm/amdgpu: update df_v3_6 for xgmi perfmons (v2)

add pmu attribute groups and structures for perf events.
add sysfs to track available df perfmon counters
fix overflow handling in perfmon counter reads.

v2: squash in fix (Alex)
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu.h

@@ -679,6 +679,7 @@ struct amdgpu_nbio_funcs {
 
 struct amdgpu_df_funcs {
 	void (*init)(struct amdgpu_device *adev);
+	void (*sw_init)(struct amdgpu_device *adev);
 	void (*enable_broadcast_mode)(struct amdgpu_device *adev,
 				      bool enable);
 	u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
@@ -729,6 +730,7 @@ struct amd_powerplay {
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
+#define AMDGPU_MAX_DF_PERFMONS 4
 struct amdgpu_device {
 	struct device			*dev;
 	struct drm_device		*ddev;
@@ -959,6 +961,7 @@ struct amdgpu_device {
 	long				compute_timeout;
 
 	uint64_t			unique_id;
+	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
 };
 
 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -1198,4 +1201,19 @@ static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return
 #endif
 
 #include "amdgpu_object.h"
+
+/* used by df_v3_6.c and amdgpu_pmu.c */
+#define AMDGPU_PMU_ATTR(_name, _object)					\
+static ssize_t								\
+_name##_show(struct device *dev,					\
+			       struct device_attribute *attr,		\
+			       char *page)				\
+{									\
+	BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1);			\
+	return sprintf(page, _object "\n");				\
+}									\
+									\
+static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
+
 #endif
+

drivers/gpu/drm/amd/amdgpu/df_v3_6.h

@@ -36,22 +36,15 @@ enum DF_V3_6_MGCG {
 };
 
 /* Defined in global_features.h as FTI_PERFMON_VISIBLE */
-#define AMDGPU_DF_MAX_COUNTERS		4
+#define DF_V3_6_MAX_COUNTERS		4
 
 /* get flags from df perfmon config */
-#define GET_EVENT(x)			(x & 0xFFUL)
-#define GET_INSTANCE(x)			((x >> 8) & 0xFFUL)
-#define GET_UNITMASK(x)			((x >> 16) & 0xFFUL)
-#define GET_INSTANCE_CONFIG(x)		(0ULL | (0x07ULL) \
-					| ((0x046ULL + x) << 8) \
-					| (0x02 << 16))
-
-/* df event conf macros */
-#define IS_DF_XGMI_0_TX(x) (GET_EVENT(x) == 0x7 \
-		&& GET_INSTANCE(x) == 0x46 && GET_UNITMASK(x) == 0x2)
-#define IS_DF_XGMI_1_TX(x) (GET_EVENT(x) == 0x7 \
-		&& GET_INSTANCE(x) == 0x47 && GET_UNITMASK(x) == 0x2)
+#define DF_V3_6_GET_EVENT(x)		(x & 0xFFUL)
+#define DF_V3_6_GET_INSTANCE(x)		((x >> 8) & 0xFFUL)
+#define DF_V3_6_GET_UNITMASK(x)		((x >> 16) & 0xFFUL)
+#define DF_V3_6_PERFMON_OVERFLOW	0xFFFFFFFFFFFFULL
 
+extern const struct attribute_group *df_v3_6_attr_groups[];
 extern const struct amdgpu_df_funcs df_v3_6_funcs;
 
 #endif

drivers/gpu/drm/amd/amdgpu/soc15.c

@@ -1034,6 +1034,8 @@ static int soc15_common_sw_init(void *handle)
 	if (amdgpu_sriov_vf(adev))
 		xgpu_ai_mailbox_add_irq_id(adev);
 
+	adev->df_funcs->sw_init(adev);
+
 	return 0;
 }
 
@@ -1080,6 +1082,7 @@ static int soc15_common_hw_init(void *handle)
 	 */
 	if (adev->nbio_funcs->remap_hdp_registers)
 		adev->nbio_funcs->remap_hdp_registers(adev);
+
 	/* enable the doorbell aperture */
 	soc15_enable_doorbell_aperture(adev, true);
 	/* HW doorbell routing policy: doorbell writing not