Commit e4d2a598 authored by Anders Grafström's avatar Anders Grafström Committed by Russell King

[ARM] 5310/1: Fix cache flush functions for ARMv4

ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels.
The issue was introduced by commit f12d0d7c
This patch corrects the CPU_CP15 ifdef statements so that they actually
do something.
Signed-off-by: default avatarAnders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 957cf333
...@@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all) ...@@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all)
* Clean and invalidate the entire cache. * Clean and invalidate the entire cache.
*/ */
ENTRY(v4_flush_kern_cache_all) ENTRY(v4_flush_kern_cache_all)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
mov pc, lr mov pc, lr
...@@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all) ...@@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all)
* - flags - vma_area_struct flags describing address space * - flags - vma_area_struct flags describing address space
*/ */
ENTRY(v4_flush_user_cache_range) ENTRY(v4_flush_user_cache_range)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov ip, #0 mov ip, #0
mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
mov pc, lr mov pc, lr
...@@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range) ...@@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range)
* - end - virtual end address * - end - virtual end address
*/ */
ENTRY(v4_dma_flush_range) ENTRY(v4_dma_flush_range)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
#endif #endif
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment