Commit e696268a authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4165/1: S3C24XX: Select CONFIG_NO_IOPORT
  [ARM] Fix s3c2410 ALSA audio for typedef elimination
  [ARM] Fix ARM AACI ALSA driver
  [ARM] fix mach-at91 build breakage
  [ARM] Fix jornada720 build errors
  [ARM] Fix iop13xx build error
  [ARM] Fix build error caused by move of apm
  [ARM] 4223/1: ixdp2351 : Fix for a define error
  [ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xx
  [ARM] 4186/1: iop: remove cp6_enable/disable routines
  [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user
parents 91aa6931 5a84d159
...@@ -23,11 +23,11 @@ ...@@ -23,11 +23,11 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/leds.h> #include <linux/leds.h>
#include <linux/apm-emulation.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/apm-emulation.h>
#include <asm/arch/pm.h> #include <asm/arch/pm.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/sharpsl.h> #include <asm/arch/sharpsl.h>
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
* Interrupt handling. Preserves r7, r8, r9 * Interrupt handling. Preserves r7, r8, r9
*/ */
.macro irq_handler .macro irq_handler
get_irqnr_preamble r5, lr
1: get_irqnr_and_base r0, r6, r5, lr 1: get_irqnr_and_base r0, r6, r5, lr
movne r1, sp movne r1, sp
@ @
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
*/ */
#include <asm/unistd.h> #include <asm/unistd.h>
#include <asm/arch/entry-macro.S>
#include "entry-header.S" #include "entry-header.S"
...@@ -25,6 +26,9 @@ ret_fast_syscall: ...@@ -25,6 +26,9 @@ ret_fast_syscall:
tst r1, #_TIF_WORK_MASK tst r1, #_TIF_WORK_MASK
bne fast_work_pending bne fast_work_pending
/* perform architecture specific actions before user return */
arch_ret_to_user r1, lr
@ fast_restore_user_regs @ fast_restore_user_regs
ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr
ldr lr, [sp, #S_OFF + S_PC]! @ get pc ldr lr, [sp, #S_OFF + S_PC]! @ get pc
...@@ -61,6 +65,9 @@ ret_slow_syscall: ...@@ -61,6 +65,9 @@ ret_slow_syscall:
tst r1, #_TIF_WORK_MASK tst r1, #_TIF_WORK_MASK
bne work_pending bne work_pending
no_work_pending: no_work_pending:
/* perform architecture specific actions before user return */
arch_ret_to_user r1, lr
@ slow_restore_user_regs @ slow_restore_user_regs
ldr r1, [sp, #S_PSR] @ get calling cpsr ldr r1, [sp, #S_PSR] @ get calling cpsr
ldr lr, [sp, #S_PC]! @ get pc ldr lr, [sp, #S_PC]! @ get pc
......
...@@ -5,7 +5,6 @@ obj- := ...@@ -5,7 +5,6 @@ obj- :=
obj-$(CONFIG_ARCH_IOP13XX) += setup.o obj-$(CONFIG_ARCH_IOP13XX) += setup.o
obj-$(CONFIG_ARCH_IOP13XX) += irq.o obj-$(CONFIG_ARCH_IOP13XX) += irq.o
obj-$(CONFIG_ARCH_IOP13XX) += time.o
obj-$(CONFIG_ARCH_IOP13XX) += pci.o obj-$(CONFIG_ARCH_IOP13XX) += pci.o
obj-$(CONFIG_ARCH_IOP13XX) += io.o obj-$(CONFIG_ARCH_IOP13XX) += io.o
obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/arch/pci.h> #include <asm/arch/pci.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/arch/time.h>
extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
...@@ -78,12 +79,12 @@ static void __init iq81340mc_init(void) ...@@ -78,12 +79,12 @@ static void __init iq81340mc_init(void)
static void __init iq81340mc_timer_init(void) static void __init iq81340mc_timer_init(void)
{ {
iop13xx_init_time(400000000); iop_init_time(400000000);
} }
static struct sys_timer iq81340mc_timer = { static struct sys_timer iq81340mc_timer = {
.init = iq81340mc_timer_init, .init = iq81340mc_timer_init,
.offset = iop13xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
MACHINE_START(IQ81340MC, "Intel IQ81340MC") MACHINE_START(IQ81340MC, "Intel IQ81340MC")
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/arch/pci.h> #include <asm/arch/pci.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/arch/time.h>
extern int init_atu; extern int init_atu;
...@@ -80,12 +81,12 @@ static void __init iq81340sc_init(void) ...@@ -80,12 +81,12 @@ static void __init iq81340sc_init(void)
static void __init iq81340sc_timer_init(void) static void __init iq81340sc_timer_init(void)
{ {
iop13xx_init_time(400000000); iop_init_time(400000000);
} }
static struct sys_timer iq81340sc_timer = { static struct sys_timer iq81340sc_timer = {
.init = iq81340sc_timer_init, .init = iq81340sc_timer_init,
.offset = iop13xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
MACHINE_START(IQ81340SC, "Intel IQ81340SC") MACHINE_START(IQ81340SC, "Intel IQ81340SC")
......
...@@ -161,65 +161,49 @@ static void write_intsize(u32 val) ...@@ -161,65 +161,49 @@ static void write_intsize(u32 val)
static void static void
iop13xx_irq_mask0 (unsigned int irq) iop13xx_irq_mask0 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask1 (unsigned int irq) iop13xx_irq_mask1 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask2 (unsigned int irq) iop13xx_irq_mask2 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_mask3 (unsigned int irq) iop13xx_irq_mask3 (unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask0(unsigned int irq) iop13xx_irq_unmask0(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_0(read_intctl_0() | (1 << (irq - 0))); write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask1(unsigned int irq) iop13xx_irq_unmask1(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_1(read_intctl_1() | (1 << (irq - 32))); write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask2(unsigned int irq) iop13xx_irq_unmask2(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_2(read_intctl_2() | (1 << (irq - 64))); write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
iop13xx_cp6_restore(cp_flags);
} }
static void static void
iop13xx_irq_unmask3(unsigned int irq) iop13xx_irq_unmask3(unsigned int irq)
{ {
u32 cp_flags = iop13xx_cp6_save();
write_intctl_3(read_intctl_3() | (1 << (irq - 96))); write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
iop13xx_cp6_restore(cp_flags);
} }
static struct irq_chip iop13xx_irqchip1 = { static struct irq_chip iop13xx_irqchip1 = {
...@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void) ...@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void)
{ {
unsigned int i; unsigned int i;
u32 cp_flags = iop13xx_cp6_save();
iop_init_cp6_handler(); iop_init_cp6_handler();
/* disable all interrupts */ /* disable all interrupts */
...@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void) ...@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void)
set_irq_handler(i, handle_level_irq); set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
iop13xx_cp6_restore(cp_flags);
} }
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/io.h>
#define IOP13XX_UART_XTAL 33334000 #define IOP13XX_UART_XTAL 33334000
#define IOP13XX_SETUP_DEBUG 0 #define IOP13XX_SETUP_DEBUG 0
......
/*
* arch/arm/mach-iop13xx/time.c
*
* Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright 2002-2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
static unsigned long ticks_per_jiffy;
static unsigned long ticks_per_usec;
static unsigned long next_jiffy_time;
static inline u32 read_tcr1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
return val;
}
unsigned long iop13xx_gettimeoffset(void)
{
unsigned long offset;
u32 cp_flags;
cp_flags = iop13xx_cp6_save();
offset = next_jiffy_time - read_tcr1();
iop13xx_cp6_restore(cp_flags);
return offset / ticks_per_usec;
}
static irqreturn_t
iop13xx_timer_interrupt(int irq, void *dev_id)
{
u32 cp_flags = iop13xx_cp6_save();
write_seqlock(&xtime_lock);
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
while ((signed long)(next_jiffy_time - read_tcr1())
>= ticks_per_jiffy) {
timer_tick();
next_jiffy_time -= ticks_per_jiffy;
}
write_sequnlock(&xtime_lock);
iop13xx_cp6_restore(cp_flags);
return IRQ_HANDLED;
}
static struct irqaction iop13xx_timer_irq = {
.name = "IOP13XX Timer Tick",
.handler = iop13xx_timer_interrupt,
.flags = IRQF_DISABLED | IRQF_TIMER,
};
void __init iop13xx_init_time(unsigned long tick_rate)
{
u32 timer_ctl;
u32 cp_flags;
ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
ticks_per_usec = tick_rate / 1000000;
next_jiffy_time = 0xffffffff;
timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
/*
* We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies.
*/
cp_flags = iop13xx_cp6_save();
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
iop13xx_cp6_restore(cp_flags);
setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
}
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/arch/time.h>
/* /*
* GLAN Tank timer tick configuration. * GLAN Tank timer tick configuration.
...@@ -38,12 +39,12 @@ ...@@ -38,12 +39,12 @@
static void __init glantank_timer_init(void) static void __init glantank_timer_init(void)
{ {
/* 33.333 MHz crystal. */ /* 33.333 MHz crystal. */
iop3xx_init_time(200000000); iop_init_time(200000000);
} }
static struct sys_timer glantank_timer = { static struct sys_timer glantank_timer = {
.init = glantank_timer_init, .init = glantank_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/arch/time.h>
/* /*
* The EP80219 and IQ31244 use the same machine ID. To find out * The EP80219 and IQ31244 use the same machine ID. To find out
...@@ -56,16 +56,16 @@ static void __init iq31244_timer_init(void) ...@@ -56,16 +56,16 @@ static void __init iq31244_timer_init(void)
{ {
if (is_80219()) { if (is_80219()) {
/* 33.333 MHz crystal. */ /* 33.333 MHz crystal. */
iop3xx_init_time(200000000); iop_init_time(200000000);
} else { } else {
/* 33.000 MHz crystal. */ /* 33.000 MHz crystal. */
iop3xx_init_time(198000000); iop_init_time(198000000);
} }
} }
static struct sys_timer iq31244_timer = { static struct sys_timer iq31244_timer = {
.init = iq31244_timer_init, .init = iq31244_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/arch/time.h>
/* /*
* IQ80321 timer tick configuration. * IQ80321 timer tick configuration.
...@@ -40,12 +41,12 @@ ...@@ -40,12 +41,12 @@
static void __init iq80321_timer_init(void) static void __init iq80321_timer_init(void)
{ {
/* 33.333 MHz crystal. */ /* 33.333 MHz crystal. */
iop3xx_init_time(200000000); iop_init_time(200000000);
} }
static struct sys_timer iq80321_timer = { static struct sys_timer iq80321_timer = {
.init = iq80321_timer_init, .init = iq80321_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -23,16 +23,12 @@ static u32 iop32x_mask; ...@@ -23,16 +23,12 @@ static u32 iop32x_mask;
static inline void intctl_write(u32 val) static inline void intctl_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr_write(u32 val) static inline void intstr_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static void static void
......
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/arch/time.h>
/* /*
* N2100 timer tick configuration. * N2100 timer tick configuration.
...@@ -44,12 +45,12 @@ ...@@ -44,12 +45,12 @@
static void __init n2100_timer_init(void) static void __init n2100_timer_init(void)
{ {
/* 33.000 MHz crystal. */ /* 33.000 MHz crystal. */
iop3xx_init_time(198000000); iop_init_time(198000000);
} }
static struct sys_timer n2100_timer = { static struct sys_timer n2100_timer = {
.init = n2100_timer_init, .init = n2100_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/arch/time.h>
/* /*
* IQ80331 timer tick configuration. * IQ80331 timer tick configuration.
...@@ -40,14 +41,14 @@ static void __init iq80331_timer_init(void) ...@@ -40,14 +41,14 @@ static void __init iq80331_timer_init(void)
{ {
/* D-Step parts run at a higher internal bus frequency */ /* D-Step parts run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa) if (*IOP3XX_ATURID >= 0xa)
iop3xx_init_time(333000000); iop_init_time(333000000);
else else
iop3xx_init_time(266000000); iop_init_time(266000000);
} }
static struct sys_timer iq80331_timer = { static struct sys_timer iq80331_timer = {
.init = iq80331_timer_init, .init = iq80331_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/arch/time.h>
/* /*
* IQ80332 timer tick configuration. * IQ80332 timer tick configuration.
...@@ -40,14 +41,14 @@ static void __init iq80332_timer_init(void) ...@@ -40,14 +41,14 @@ static void __init iq80332_timer_init(void)
{ {
/* D-Step parts and the iop333 run at a higher internal bus frequency */ /* D-Step parts and the iop333 run at a higher internal bus frequency */
if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374) if (*IOP3XX_ATURID >= 0xa || *IOP3XX_ATUDID == 0x374)
iop3xx_init_time(333000000); iop_init_time(333000000);
else else
iop3xx_init_time(266000000); iop_init_time(266000000);
} }
static struct sys_timer iq80332_timer = { static struct sys_timer iq80332_timer = {
.init = iq80332_timer_init, .init = iq80332_timer_init,
.offset = iop3xx_gettimeoffset, .offset = iop_gettimeoffset,
}; };
......
...@@ -24,44 +24,32 @@ static u32 iop33x_mask1; ...@@ -24,44 +24,32 @@ static u32 iop33x_mask1;
static inline void intctl0_write(u32 val) static inline void intctl0_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intctl1_write(u32 val) static inline void intctl1_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr0_write(u32 val) static inline void intstr0_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intstr1_write(u32 val) static inline void intstr1_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intbase_write(u32 val) static inline void intbase_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static inline void intsize_write(u32 val) static inline void intsize_write(u32 val)
{ {
iop3xx_cp6_enable();
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
iop3xx_cp6_disable();
} }
static void static void
......
...@@ -231,12 +231,6 @@ static struct platform_device *devices[] __initdata = { ...@@ -231,12 +231,6 @@ static struct platform_device *devices[] __initdata = {
&s1d13xxxfb_device, &s1d13xxxfb_device,
}; };
/* a stub for now, we theoretically cannot suspend without a flashboard */
int pm_suspend(suspend_state_t state)
{
return -1;
}
static int __init jornada720_init(void) static int __init jornada720_init(void)
{ {
int ret = -ENODEV; int ret = -ENODEV;
......
...@@ -24,6 +24,7 @@ obj-$(CONFIG_ARCH_IOP33X) += cp6.o ...@@ -24,6 +24,7 @@ obj-$(CONFIG_ARCH_IOP33X) += cp6.o
# IOP13XX # IOP13XX
obj-$(CONFIG_ARCH_IOP13XX) += cp6.o obj-$(CONFIG_ARCH_IOP13XX) += cp6.o
obj-$(CONFIG_ARCH_IOP13XX) += time.o
obj-m := obj-m :=
obj-n := obj-n :=
......
...@@ -24,38 +24,44 @@ ...@@ -24,38 +24,44 @@
#include <asm/uaccess.h> #include <asm/uaccess.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/arch/time.h>
#ifdef CONFIG_ARCH_IOP32X
#define IRQ_IOP3XX_TIMER0 IRQ_IOP32X_TIMER0
#else
#ifdef CONFIG_ARCH_IOP33X
#define IRQ_IOP3XX_TIMER0 IRQ_IOP33X_TIMER0
#endif
#endif
static unsigned long ticks_per_jiffy; static unsigned long ticks_per_jiffy;
static unsigned long ticks_per_usec; static unsigned long ticks_per_usec;
static unsigned long next_jiffy_time; static unsigned long next_jiffy_time;
unsigned long iop3xx_gettimeoffset(void) unsigned long iop_gettimeoffset(void)
{ {
unsigned long offset; unsigned long offset, temp1, temp2;
offset = next_jiffy_time - *IOP3XX_TU_TCR1; /* enable cp6, if necessary, to avoid taking the overhead of an
* undefined instruction trap
*/
asm volatile (
"mrc p15, 0, %0, c15, c1, 0\n\t"
"ands %1, %0, #(1 << 6)\n\t"
"orreq %0, %0, #(1 << 6)\n\t"
"mcreq p15, 0, %0, c15, c1, 0\n\t"
#ifdef CONFIG_XSCALE
"mrceq p15, 0, %0, c15, c1, 0\n\t"
"moveq %0, %0\n\t"
"subeq pc, pc, #4\n\t"
#endif
: "=r"(temp1), "=r"(temp2) : : "cc");
offset = next_jiffy_time - read_tcr1();
return offset / ticks_per_usec; return offset / ticks_per_usec;
} }
static irqreturn_t static irqreturn_t
iop3xx_timer_interrupt(int irq, void *dev_id) iop_timer_interrupt(int irq, void *dev_id)
{ {
write_seqlock(&xtime_lock); write_seqlock(&xtime_lock);
iop3xx_cp6_enable(); write_tisr(1);
asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
iop3xx_cp6_disable();
while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) while ((signed long)(next_jiffy_time - read_tcr1())
>= ticks_per_jiffy) { >= ticks_per_jiffy) {
timer_tick(); timer_tick();
next_jiffy_time -= ticks_per_jiffy; next_jiffy_time -= ticks_per_jiffy;
...@@ -66,13 +72,13 @@ iop3xx_timer_interrupt(int irq, void *dev_id) ...@@ -66,13 +72,13 @@ iop3xx_timer_interrupt(int irq, void *dev_id)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static struct irqaction iop3xx_timer_irq = { static struct irqaction iop_timer_irq = {
.name = "IOP3XX Timer Tick", .name = "IOP Timer Tick",
.handler = iop3xx_timer_interrupt, .handler = iop_timer_interrupt,
.flags = IRQF_DISABLED | IRQF_TIMER, .flags = IRQF_DISABLED | IRQF_TIMER,
}; };
void __init iop3xx_init_time(unsigned long tick_rate) void __init iop_init_time(unsigned long tick_rate)
{ {
u32 timer_ctl; u32 timer_ctl;
...@@ -80,19 +86,17 @@ void __init iop3xx_init_time(unsigned long tick_rate) ...@@ -80,19 +86,17 @@ void __init iop3xx_init_time(unsigned long tick_rate)
ticks_per_usec = tick_rate / 1000000; ticks_per_usec = tick_rate / 1000000;
next_jiffy_time = 0xffffffff; next_jiffy_time = 0xffffffff;
timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED | timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1; IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
/* /*
* We use timer 0 for our timer interrupt, and timer 1 as * We use timer 0 for our timer interrupt, and timer 1 as
* monotonic counter for tracking missed jiffies. * monotonic counter for tracking missed jiffies.
*/ */
iop3xx_cp6_enable(); write_trr0(ticks_per_jiffy - 1);
asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); write_tmr0(timer_ctl);
asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); write_trr1(0xffffffff);
asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); write_tmr1(timer_ctl);
asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
iop3xx_cp6_disable(); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
} }
...@@ -8,6 +8,7 @@ config PLAT_S3C24XX ...@@ -8,6 +8,7 @@ config PLAT_S3C24XX
bool bool
depends on ARCH_S3C2410 depends on ARCH_S3C2410
default y if ARCH_S3C2410 default y if ARCH_S3C2410
select NO_IOPORT
help help
Base platform code for any Samsung S3C device Base platform code for any Samsung S3C device
......
...@@ -15,6 +15,12 @@ ...@@ -15,6 +15,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xf8000000 mov r4, #0xf8000000
add r4, r4, #0x00000500 add r4, r4, #0x00000500
......
...@@ -16,6 +16,12 @@ ...@@ -16,6 +16,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
......
/*
* include/asm-arm/arch-at91rm9200/entry-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Low-level IRQ helper macros for AT91RM9200 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
#include <asm/arch/at91_aic.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals
ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
.endm
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/hardware/entry-macro-iomd.S> #include <asm/hardware/entry-macro-iomd.S>
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
...@@ -13,6 +13,12 @@ ...@@ -13,6 +13,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1) #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
#error INTSR stride != INTMR stride #error INTSR stride != INTMR stride
#endif #endif
......
...@@ -15,6 +15,12 @@ ...@@ -15,6 +15,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, stat, base, tmp .macro get_irqnr_and_base, irqnr, stat, base, tmp
mov \base, #IRQ_STAT mov \base, #IRQ_STAT
ldrb \stat, [\base] @ get interrupts ldrb \stat, [\base] @ get interrupts
......
...@@ -14,6 +14,12 @@ ...@@ -14,6 +14,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.equ dc21285_high, ARMCSR_BASE & 0xff000000 .equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
......
...@@ -14,6 +14,12 @@ ...@@ -14,6 +14,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =(EP93XX_AHB_VIRT_BASE) ldr \base, =(EP93XX_AHB_VIRT_BASE)
orr \base, \base, #0x000b0000 orr \base, \base, #0x000b0000
......
...@@ -11,6 +11,12 @@ ...@@ -11,6 +11,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
@ we could use the id register on H7202, but this is not @ we could use the id register on H7202, but this is not
......
...@@ -11,6 +11,13 @@ ...@@ -11,6 +11,13 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
#define AITC_NIVECSR 0x40 #define AITC_NIVECSR 0x40
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(IMX_AITC_BASE) ldr \base, =IO_ADDRESS(IMX_AITC_BASE)
......
...@@ -13,6 +13,12 @@ ...@@ -13,6 +13,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* FIXME: should not be using soo many LDRs here */ /* FIXME: should not be using soo many LDRs here */
ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
......
...@@ -19,21 +19,27 @@ ...@@ -19,21 +19,27 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
.endm
/* /*
* Note: a 1-cycle window exists where iintvec will return the value * Note: a 1-cycle window exists where iintvec will return the value
* of iintbase, so we explicitly check for "bad zeros" * of iintbase, so we explicitly check for "bad zeros"
*/ */
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
cmp \irqnr, #0 cmp \irqnr, #0
mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
adds \irqstat, \irqnr, #1 @ Check for 0xffffffff adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
.endm
biceq \tmp, \tmp, #(1 << 6) .macro arch_ret_to_user, tmp1, tmp2
mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm .endm
...@@ -9,34 +9,6 @@ void iop13xx_init_irq(void); ...@@ -9,34 +9,6 @@ void iop13xx_init_irq(void);
void iop13xx_map_io(void); void iop13xx_map_io(void);
void iop13xx_platform_init(void); void iop13xx_platform_init(void);
void iop13xx_init_irq(void); void iop13xx_init_irq(void);
void iop13xx_init_time(unsigned long tickrate);
unsigned long iop13xx_gettimeoffset(void);
/* handle cp6 access
* to do: handle access in entry-armv5.S and unify with
* the iop3xx implementation
* note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
* when interrupts are enabled
*/
static inline unsigned long iop13xx_cp6_save(void)
{
u32 temp, cp_flags;
asm volatile (
"mrc p15, 0, %1, c15, c1, 0\n\t"
"orr %0, %1, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
: "=r" (temp), "=r"(cp_flags));
return cp_flags;
}
static inline void iop13xx_cp6_restore(unsigned long cp_flags)
{
asm volatile (
"mcr p15, 0, %0, c15, c1, 0\n\t"
: : "r" (cp_flags) );
}
/* CPUID CP6 R0 Page 0 */ /* CPUID CP6 R0 Page 0 */
static inline int iop13xx_cpu_id(void) static inline int iop13xx_cpu_id(void)
...@@ -479,14 +451,4 @@ static inline int iop13xx_cpu_id(void) ...@@ -479,14 +451,4 @@ static inline int iop13xx_cpu_id(void)
#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
#define IOP13XX_TMR_TC 0x01
#define IOP13XX_TMR_EN 0x02
#define IOP13XX_TMR_RELOAD 0x04
#define IOP13XX_TMR_PRIVILEGED 0x08
#define IOP13XX_TMR_RATIO_1_1 0x00
#define IOP13XX_TMR_RATIO_4_1 0x10
#define IOP13XX_TMR_RATIO_8_1 0x20
#define IOP13XX_TMR_RATIO_16_1 0x30
#endif /* _IOP13XX_HW_H_ */ #endif /* _IOP13XX_HW_H_ */
...@@ -3,8 +3,6 @@ ...@@ -3,8 +3,6 @@
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
#include <linux/types.h> #include <linux/types.h>
#include <asm/system.h> /* local_irq_save */
#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
/* INTPND0 CP6 R0 Page 3 /* INTPND0 CP6 R0 Page 3
*/ */
...@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void) ...@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void)
asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
return val; return val;
} }
static inline void
iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
{
local_irq_save(*irq_flags);
*cp_flags = iop13xx_cp6_save();
}
static inline void
iop13xx_cp6_irq_restore(unsigned long *cp_flags,
unsigned long *irq_flags)
{
iop13xx_cp6_restore(*cp_flags);
local_irq_restore(*irq_flags);
}
#endif #endif
#define INTBASE 0 #define INTBASE 0
......
...@@ -48,12 +48,10 @@ static inline void arch_reset(char mode) ...@@ -48,12 +48,10 @@ static inline void arch_reset(char mode)
/* /*
* Reset the internal bus (warning both cores are reset) * Reset the internal bus (warning both cores are reset)
*/ */
u32 cp_flags = iop13xx_cp6_save();
write_wdtcr(IOP13XX_WDTCR_EN_ARM); write_wdtcr(IOP13XX_WDTCR_EN_ARM);
write_wdtcr(IOP13XX_WDTCR_EN); write_wdtcr(IOP13XX_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000); write_wdtcr(0x1000);
iop13xx_cp6_restore(cp_flags);
for(;;); for(;;);
} }
#ifndef _IOP13XX_TIME_H_
#define _IOP13XX_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
#define IOP_TMR_EN 0x02
#define IOP_TMR_RELOAD 0x04
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1 0x00
void iop_init_time(unsigned long tickrate);
unsigned long iop_gettimeoffset(void);
static inline void write_tmr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
}
static inline void write_tmr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
}
static inline u32 read_tcr0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
return val;
}
static inline u32 read_tcr1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
return val;
}
static inline void write_trr0(u32 val)
{
asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
}
static inline void write_trr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
}
static inline void write_tisr(u32 val)
{
asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
}
#endif
...@@ -12,10 +12,25 @@ ...@@ -12,10 +12,25 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p15, 0, \tmp, c15, c1, 0
mov \tmp, \tmp
sub pc, pc, #4 @ cp_wait
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IOP3XX_REG_ADDR(0x07D8) mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
ldr \irqstat, [\base] @ Read IINTSRC
cmp \irqstat, #0 cmp \irqstat, #0
clzne \irqnr, \irqstat clzne \irqnr, \irqstat
rsbne \irqnr, \irqnr, #31 rsbne \irqnr, \irqnr, #31
.endm .endm
.macro arch_ret_to_user, tmp1, tmp2
mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm
#ifndef _IOP32X_TIME_H_
#define _IOP32X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP32X_TIMER0
#endif
...@@ -12,11 +12,26 @@ ...@@ -12,11 +12,26 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p15, 0, \tmp, c15, c1, 0
mov \tmp, \tmp
sub pc, pc, #4 @ cp_wait
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IOP3XX_REG_ADDR(0x07C8) mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
ldr \irqstat, [\base] @ Read IINTVEC
cmp \irqstat, #0 cmp \irqstat, #0
ldreq \irqstat, [\base] @ erratum 63 workaround mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
adds \irqnr, \irqstat, #1 adds \irqnr, \irqstat, #1
movne \irqnr, \irqstat, lsr #2 movne \irqnr, \irqstat, lsr #2
.endm .endm
.macro arch_ret_to_user, tmp1, tmp2
mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm
#ifndef _IOP33X_TIME_H_
#define _IOP33X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
#endif
...@@ -12,6 +12,12 @@ ...@@ -12,6 +12,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0x0 @clear out irqnr as default mov \irqnr, #0x0 @clear out irqnr as default
......
...@@ -5,6 +5,12 @@ ...@@ -5,6 +5,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
ldr \irqnr, [\irqnr] @ get interrupt number ldr \irqnr, [\irqnr] @ get interrupt number
......
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0) #define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
#define IXDP2351_NVRAM_SIZE (0x20000) #define IXDP2351_NVRAM_SIZE (0x20000)
#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP3251_BB_AREA_BASE(0x00020000) #define IXDP2351_VIRT_MB_IXF1104_BASE IXDP2351_BB_AREA_BASE(0x00020000)
#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0) #define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000) #define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000) #define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
......
...@@ -12,6 +12,12 @@ ...@@ -12,6 +12,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
ldr \irqstat, [\irqstat] @ get interrupts ldr \irqstat, [\irqstat] @ get interrupts
......
...@@ -14,6 +14,12 @@ ...@@ -14,6 +14,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqstat, #irq_base_addr @ Virt addr IRQ regs mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
add \irqstat, \irqstat, #0x00001000 @ Status reg add \irqstat, \irqstat, #0x00001000 @ Status reg
......
...@@ -26,6 +26,12 @@ ...@@ -26,6 +26,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
branch_irq_lh7a400: b 1000f branch_irq_lh7a400: b 1000f
......
...@@ -23,6 +23,12 @@ ...@@ -23,6 +23,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #io_p2v(0x00100000) mov \base, #io_p2v(0x00100000)
add \base, \base, #0x000ff000 add \base, \base, #0x000ff000
......
...@@ -29,6 +29,12 @@ ...@@ -29,6 +29,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
......
...@@ -28,6 +28,12 @@ ...@@ -28,6 +28,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* decode the MIC interrupt numbers */ /* decode the MIC interrupt numbers */
ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
......
...@@ -13,6 +13,12 @@ ...@@ -13,6 +13,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x #ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
......
...@@ -13,6 +13,12 @@ ...@@ -13,6 +13,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
/* /*
* The interrupt numbering scheme is defined in the * The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit: * interrupt controller spec. To wit:
......
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/hardware/entry-macro-iomd.S> #include <asm/hardware/entry-macro-iomd.S>
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
...@@ -31,9 +31,9 @@ struct s3c24xx_iis_ops { ...@@ -31,9 +31,9 @@ struct s3c24xx_iis_ops {
int (*suspend)(struct s3c24xx_iis_ops *me); int (*suspend)(struct s3c24xx_iis_ops *me);
int (*resume)(struct s3c24xx_iis_ops *me); int (*resume)(struct s3c24xx_iis_ops *me);
int (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm); int (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
int (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm); int (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm);
int (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt); int (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt);
}; };
struct s3c24xx_platdata_iis { struct s3c24xx_platdata_iis {
......
...@@ -22,6 +22,12 @@ ...@@ -22,6 +22,12 @@
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/irq.h> #include <asm/irq.h>
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #S3C24XX_VA_IRQ mov \base, #S3C24XX_VA_IRQ
......
...@@ -11,6 +11,12 @@ ...@@ -11,6 +11,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xfa000000 @ ICIP = 0xfa050000 mov r4, #0xfa000000 @ ICIP = 0xfa050000
add r4, r4, #0x00050000 add r4, r4, #0x00050000
......
...@@ -10,6 +10,12 @@ ...@@ -10,6 +10,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xe0000000 mov r4, #0xe0000000
......
...@@ -13,6 +13,12 @@ ...@@ -13,6 +13,12 @@
.macro disable_fiq .macro disable_fiq
.endm .endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
......
...@@ -188,14 +188,10 @@ extern void gpio_line_set(int line, int value); ...@@ -188,14 +188,10 @@ extern void gpio_line_set(int line, int value);
#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
#define IOP3XX_TMR_TC 0x01 #define IOP_TMR_EN 0x02
#define IOP3XX_TMR_EN 0x02 #define IOP_TMR_RELOAD 0x04
#define IOP3XX_TMR_RELOAD 0x04 #define IOP_TMR_PRIVILEGED 0x08
#define IOP3XX_TMR_PRIVILEGED 0x09 #define IOP_TMR_RATIO_1_1 0x00
#define IOP3XX_TMR_RATIO_1_1 0x00
#define IOP3XX_TMR_RATIO_4_1 0x10
#define IOP3XX_TMR_RATIO_8_1 0x20
#define IOP3XX_TMR_RATIO_16_1 0x30
/* Application accelerator unit */ /* Application accelerator unit */
#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
...@@ -276,40 +272,52 @@ extern void gpio_line_set(int line, int value); ...@@ -276,40 +272,52 @@ extern void gpio_line_set(int line, int value);
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
void iop3xx_map_io(void); void iop3xx_map_io(void);
void iop3xx_init_time(unsigned long);
unsigned long iop3xx_gettimeoffset(void);
void iop_init_cp6_handler(void); void iop_init_cp6_handler(void);
void iop_init_time(unsigned long tickrate);
unsigned long iop_gettimeoffset(void);
extern struct platform_device iop3xx_i2c0_device; static inline void write_tmr0(u32 val)
extern struct platform_device iop3xx_i2c1_device; {
asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val));
}
static inline void write_tmr1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val));
}
static inline u32 read_tcr0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val));
return val;
}
extern inline void iop3xx_cp6_enable(void) static inline u32 read_tcr1(void)
{ {
u32 temp; u32 val;
asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val));
return val;
}
asm volatile ( static inline void write_trr0(u32 val)
"mrc p15, 0, %0, c15, c1, 0\n\t" {
"orr %0, %0, #(1 << 6)\n\t" asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
"mcr p15, 0, %0, c15, c1, 0\n\t"
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) );
} }
extern inline void iop3xx_cp6_disable(void) static inline void write_trr1(u32 val)
{ {
u32 temp; asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val));
}
asm volatile ( static inline void write_tisr(u32 val)
"mrc p15, 0, %0, c15, c1, 0\n\t" {
"bic %0, %0, #(1 << 6)\n\t" asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
"mcr p15, 0, %0, c15, c1, 0\n\t"
"mrc p15, 0, %0, c15, c1, 0\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) );
} }
extern struct platform_device iop3xx_i2c0_device;
extern struct platform_device iop3xx_i2c1_device;
#endif #endif
......
...@@ -726,8 +726,8 @@ static struct snd_pcm_ops aaci_playback_ops = { ...@@ -726,8 +726,8 @@ static struct snd_pcm_ops aaci_playback_ops = {
.mmap = aaci_pcm_mmap, .mmap = aaci_pcm_mmap,
}; };
static int aaci_pcm_capture_hw_params(snd_pcm_substream_t *substream, static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
snd_pcm_hw_params_t *params) struct snd_pcm_hw_params *params)
{ {
struct aaci *aaci = substream->private_data; struct aaci *aaci = substream->private_data;
struct aaci_runtime *aacirun = substream->runtime->private_data; struct aaci_runtime *aacirun = substream->runtime->private_data;
...@@ -783,8 +783,8 @@ static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) ...@@ -783,8 +783,8 @@ static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
writel(ie, aacirun->base + AACI_IE); writel(ie, aacirun->base + AACI_IE);
} }
static int aaci_pcm_capture_trigger(snd_pcm_substream_t *substream, int cmd){ static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct aaci *aaci = substream->private_data; struct aaci *aaci = substream->private_data;
struct aaci_runtime *aacirun = substream->runtime->private_data; struct aaci_runtime *aacirun = substream->runtime->private_data;
unsigned long flags; unsigned long flags;
...@@ -824,7 +824,7 @@ static int aaci_pcm_capture_trigger(snd_pcm_substream_t *substream, int cmd){ ...@@ -824,7 +824,7 @@ static int aaci_pcm_capture_trigger(snd_pcm_substream_t *substream, int cmd){
return ret; return ret;
} }
static int aaci_pcm_capture_prepare(snd_pcm_substream_t *substream) static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
{ {
struct snd_pcm_runtime *runtime = substream->runtime; struct snd_pcm_runtime *runtime = substream->runtime;
struct aaci *aaci = substream->private_data; struct aaci *aaci = substream->private_data;
...@@ -842,7 +842,7 @@ static int aaci_pcm_capture_prepare(snd_pcm_substream_t *substream) ...@@ -842,7 +842,7 @@ static int aaci_pcm_capture_prepare(snd_pcm_substream_t *substream)
return 0; return 0;
} }
static snd_pcm_ops_t aaci_capture_ops = { static struct snd_pcm_ops aaci_capture_ops = {
.open = aaci_pcm_open, .open = aaci_pcm_open,
.close = aaci_pcm_close, .close = aaci_pcm_close,
.ioctl = snd_pcm_lib_ioctl, .ioctl = snd_pcm_lib_ioctl,
......
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