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Commit e8a7fdc5 authored by Sivaprakash Murugesan's avatar Sivaprakash Murugesan Committed by Bjorn Andersson
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arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on address 

This patch re-arranges ipq8074 device nodes based on node address
followed by node names followed by node labels.
Suggested-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1586572830-22727-1-git-send-email-sivaprak@codeaurora.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 5a307c66
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Showing with 292 additions and 294 deletions
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View file @ e8a7fdc5
...@@ -24,63 +24,61 @@ memory { ...@@ -24,63 +24,61 @@ memory {
device_type = "memory"; device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>; reg = <0x0 0x40000000 0x0 0x20000000>;
}; };
};
&blsp1_i2c2 {
status = "ok";
};
&blsp1_spi1 {
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart3 {
status = "ok";
};
&blsp1_uart5 {
status = "ok";
};
&pcie0 {
status = "ok";
perst-gpio = <&tlmm 61 0x1>;
};
&pcie1 {
status = "ok";
perst-gpio = <&tlmm 58 0x1>;
};
&pcie_phy0 {
status = "ok";
};
&pcie_phy1 {
status = "ok";
};
&qpic_bam {
status = "ok";
};
&qpic_nand {
status = "ok";
soc { nand@0 {
serial@78b3000 { reg = <0>;
status = "ok"; nand-ecc-strength = <4>;
}; nand-ecc-step-size = <512>;
nand-bus-width = <8>;
spi@78b5000 {
status = "ok";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
serial@78b1000 {
status = "ok";
};
i2c@78b6000 {
status = "ok";
};
dma@7984000 {
status = "ok";
};
nand@79b0000 {
status = "ok";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
};
};
phy@86000 {
status = "ok";
};
phy@8e000 {
status = "ok";
};
pci@20000000 {
status = "ok";
perst-gpio = <&tlmm 58 0x1>;
};
pci@10000000 {
status = "ok";
perst-gpio = <&tlmm 61 0x1>;
};
}; };
}; };
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ e8a7fdc5
...@@ -10,15 +10,111 @@ / { ...@@ -10,15 +10,111 @@ / {
model = "Qualcomm Technologies, Inc. IPQ8074"; model = "Qualcomm Technologies, Inc. IPQ8074";
compatible = "qcom,ipq8074"; compatible = "qcom,ipq8074";
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <19200000>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc { soc: soc {
#address-cells = <0x1>; #address-cells = <0x1>;
#size-cells = <0x1>; #size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>; ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus"; compatible = "simple-bus";
pcie_phy0: phy@86000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x00086000 0x1000>;
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
clock-names = "pipe_clk";
clock-output-names = "pcie20_phy0_pipe_clk";
resets = <&gcc GCC_PCIE0_PHY_BCR>,
<&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
};
pcie_phy1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x0008e000 0x1000>;
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
clock-names = "pipe_clk";
clock-output-names = "pcie20_phy1_pipe_clk";
resets = <&gcc GCC_PCIE1_PHY_BCR>,
<&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
};
tlmm: pinctrl@1000000 { tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl"; compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>; reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&tlmm 0 0 70>; gpio-ranges = <&tlmm 0 0 70>;
...@@ -66,102 +162,16 @@ qpic_pins: qpic-pins { ...@@ -66,102 +162,16 @@ qpic_pins: qpic-pins {
}; };
}; };
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xb120000 0x1000>;
clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb121000 0x1000>,
<0xb122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb128000 0x1000>;
status = "disabled";
};
};
gcc: gcc@1800000 { gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074"; compatible = "qcom,gcc-ipq8074";
reg = <0x1800000 0x80000>; reg = <0x01800000 0x80000>;
#clock-cells = <0x1>; #clock-cells = <0x1>;
#reset-cells = <0x1>; #reset-cells = <0x1>;
}; };
blsp1_uart5: serial@78b3000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b3000 0x200>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-0 = <&serial_4_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp_dma: dma@7884000 { blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0"; compatible = "qcom,bam-v1.7.0";
reg = <0x7884000 0x2b000>; reg = <0x07884000 0x2b000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>; clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
...@@ -171,7 +181,7 @@ blsp_dma: dma@7884000 { ...@@ -171,7 +181,7 @@ blsp_dma: dma@7884000 {
blsp1_uart1: serial@78af000 { blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>; reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
...@@ -181,7 +191,7 @@ blsp1_uart1: serial@78af000 { ...@@ -181,7 +191,7 @@ blsp1_uart1: serial@78af000 {
blsp1_uart3: serial@78b1000 { blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b1000 0x200>; reg = <0x078b1000 0x200>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>; <&gcc GCC_BLSP1_AHB_CLK>;
...@@ -194,11 +204,23 @@ blsp1_uart3: serial@78b1000 { ...@@ -194,11 +204,23 @@ blsp1_uart3: serial@78b1000 {
status = "disabled"; status = "disabled";
}; };
blsp1_uart5: serial@78b3000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b3000 0x200>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-0 = <&serial_4_pins>;
pinctrl-names = "default";
status = "disabled";
};
blsp1_spi1: spi@78b5000 { blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1"; compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x78b5000 0x600>; reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
...@@ -215,7 +237,7 @@ blsp1_i2c2: i2c@78b6000 { ...@@ -215,7 +237,7 @@ blsp1_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x78b6000 0x600>; reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
...@@ -232,7 +254,7 @@ blsp1_i2c3: i2c@78b7000 { ...@@ -232,7 +254,7 @@ blsp1_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1"; compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x78b7000 0x600>; reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>, clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
...@@ -245,7 +267,7 @@ blsp1_i2c3: i2c@78b7000 { ...@@ -245,7 +267,7 @@ blsp1_i2c3: i2c@78b7000 {
qpic_bam: dma@7984000 { qpic_bam: dma@7984000 {
compatible = "qcom,bam-v1.7.0"; compatible = "qcom,bam-v1.7.0";
reg = <0x7984000 0x1a000>; reg = <0x07984000 0x1a000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_AHB_CLK>; clocks = <&gcc GCC_QPIC_AHB_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
...@@ -256,7 +278,7 @@ qpic_bam: dma@7984000 { ...@@ -256,7 +278,7 @@ qpic_bam: dma@7984000 {
qpic_nand: nand@79b0000 { qpic_nand: nand@79b0000 {
compatible = "qcom,ipq8074-nand"; compatible = "qcom,ipq8074-nand";
reg = <0x79b0000 0x10000>; reg = <0x079b0000 0x10000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>, clocks = <&gcc GCC_QPIC_CLK>,
...@@ -272,104 +294,85 @@ qpic_nand: nand@79b0000 { ...@@ -272,104 +294,85 @@ qpic_nand: nand@79b0000 {
status = "disabled"; status = "disabled";
}; };
pcie_phy0: phy@86000 { intc: interrupt-controller@b000000 {
compatible = "qcom,ipq8074-qmp-pcie-phy"; compatible = "qcom,msm-qgic2";
reg = <0x86000 0x1000>; interrupt-controller;
#phy-cells = <0>; #interrupt-cells = <0x3>;
clocks = <&gcc GCC_PCIE0_PIPE_CLK>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
clock-names = "pipe_clk"; };
clock-output-names = "pcie20_phy0_pipe_clk";
resets = <&gcc GCC_PCIE0_PHY_BCR>, timer {
<&gcc GCC_PCIE0PHY_PHY_BCR>; compatible = "arm,armv8-timer";
reset-names = "phy", interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
"common"; <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
status = "disabled"; <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
pcie0: pci@20000000 { timer@b120000 {
compatible = "qcom,pcie-ipq8074"; #address-cells = <1>;
reg = <0x20000000 0xf1d #size-cells = <1>;
0x20000f20 0xa8 ranges;
0x80000 0x2000 compatible = "arm,armv7-timer-mem";
0x20100000 0x1000>; reg = <0x0b120000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config"; clock-frequency = <19200000>;
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
phys = <&pcie_phy0>; frame@b120000 {
phy-names = "pciephy"; frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};
ranges = <0x81000000 0 0x20200000 0x20200000 frame@b123000 {
0 0x100000 /* downstream I/O */ frame-number = <1>;
0x82000000 0 0x20300000 0x20300000 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0 0xd00000>; /* non-prefetchable memory */ reg = <0x0b123000 0x1000>;
status = "disabled";
};
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; frame@b124000 {
interrupt-names = "msi"; frame-number = <2>;
#interrupt-cells = <1>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>; reg = <0x0b124000 0x1000>;
interrupt-map = <0 0 0 1 &intc 0 75 status = "disabled";
IRQ_TYPE_LEVEL_HIGH>, /* int_a */ };
<0 0 0 2 &intc 0 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, frame@b125000 {
<&gcc GCC_PCIE0_AXI_M_CLK>, frame-number = <3>;
<&gcc GCC_PCIE0_AXI_S_CLK>, interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
<&gcc GCC_PCIE0_AHB_CLK>, reg = <0x0b125000 0x1000>;
<&gcc GCC_PCIE0_AUX_CLK>; status = "disabled";
};
clock-names = "iface", frame@b126000 {
"axi_m", frame-number = <4>;
"axi_s", interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
"ahb", reg = <0x0b126000 0x1000>;
"aux"; status = "disabled";
resets = <&gcc GCC_PCIE0_PIPE_ARES>, };
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky";
status = "disabled";
};
pcie_phy1: phy@8e000 { frame@b127000 {
compatible = "qcom,ipq8074-qmp-pcie-phy"; frame-number = <5>;
reg = <0x8e000 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
#phy-cells = <0>; reg = <0x0b127000 0x1000>;
clocks = <&gcc GCC_PCIE1_PIPE_CLK>; status = "disabled";
clock-names = "pipe_clk"; };
clock-output-names = "pcie20_phy1_pipe_clk";
resets = <&gcc GCC_PCIE1_PHY_BCR>, frame@b128000 {
<&gcc GCC_PCIE1PHY_PHY_BCR>; frame-number = <6>;
reset-names = "phy", interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
"common"; reg = <0x0b128000 0x1000>;
status = "disabled"; status = "disabled";
};
}; };
pcie1: pci@10000000 { pcie1: pci@10000000 {
compatible = "qcom,pcie-ipq8074"; compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d reg = <0x10000000 0xf1d
0x10000f20 0xa8 0x10000f20 0xa8
0x88000 0x2000 0x00088000 0x2000
0x10100000 0x1000>; 0x10100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config"; reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci"; device_type = "pci";
...@@ -426,71 +429,68 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ...@@ -426,71 +429,68 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"axi_m_sticky"; "axi_m_sticky";
status = "disabled"; status = "disabled";
}; };
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 { pcie0: pci@20000000 {
device_type = "cpu"; compatible = "qcom,pcie-ipq8074";
compatible = "arm,cortex-a53"; reg = <0x20000000 0xf1d
enable-method = "psci"; 0x20000f20 0xa8
reg = <0x2>; 0x00080000 0x2000
next-level-cache = <&L2_0>; 0x20100000 0x1000>;
}; reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
CPU3: cpu@3 { linux,pci-domain = <0>;
device_type = "cpu"; bus-range = <0x00 0xff>;
compatible = "arm,cortex-a53"; num-lanes = <1>;
enable-method = "psci"; #address-cells = <3>;
reg = <0x3>; #size-cells = <2>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache { phys = <&pcie_phy0>;
compatible = "cache"; phy-names = "pciephy";
cache-level = <0x2>;
};
};
psci { ranges = <0x81000000 0 0x20200000 0x20200000
compatible = "arm,psci-1.0"; 0 0x100000 /* downstream I/O */
method = "smc"; 0x82000000 0 0x20300000 0x20300000
}; 0 0xd00000>; /* non-prefetchable memory */
pmu { interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
compatible = "arm,armv8-pmuv3"; interrupt-names = "msi";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <1>;
}; interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks { clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
sleep_clk: sleep_clk { <&gcc GCC_PCIE0_AXI_M_CLK>,
compatible = "fixed-clock"; <&gcc GCC_PCIE0_AXI_S_CLK>,
clock-frequency = <32000>; <&gcc GCC_PCIE0_AHB_CLK>,
#clock-cells = <0>; <&gcc GCC_PCIE0_AUX_CLK>;
};
xo: xo { clock-names = "iface",
compatible = "fixed-clock"; "axi_m",
clock-frequency = <19200000>; "axi_s",
#clock-cells = <0>; "ahb",
"aux";
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
<&gcc GCC_PCIE0_SLEEP_ARES>,
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
<&gcc GCC_PCIE0_AHB_ARES>,
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
reset-names = "pipe",
"sleep",
"sticky",
"axi_m",
"axi_s",
"ahb",
"axi_m_sticky";
status = "disabled";
}; };
}; };
}; };
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