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Commit e919c24b authored by Mark Brown's avatar Mark Brown
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ASoC: Remove old i.MX driver code 

This has been superceeded by Sascha's new driver but was not removed in
the patch series due to cutdowns for review.
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent d08a68bf
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sound/soc/imx/mx1_mx2-pcm.c deleted 100644 → 0
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sound/soc/imx/mx1_mx2-pcm.h deleted 100644 → 0
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/*
* mx1_mx2-pcm.h :- ASoC platform header for Freescale i.MX1x, i.MX2x
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _MX1_MX2_PCM_H
#define _MX1_MX2_PCM_H
/* DMA information for mx1_mx2 platforms */
struct mx1_mx2_pcm_dma_params {
char *name; /* stream identifier */
unsigned int transfer_type; /* READ or WRITE DMA transfer */
dma_addr_t per_address; /* physical address of SSI fifo */
int event_id; /* fixed DMA number for SSI fifo */
int watermark_level; /* SSI fifo watermark level */
int per_config; /* DMA Config flags for peripheral */
int mem_config; /* DMA Config flags for RAM */
};
/* platform data */
extern struct snd_soc_platform mx1_mx2_soc_platform;
#endif
sound/soc/imx/mx27vis_wm8974.c deleted 100644 → 0
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/*
* mx27vis_wm8974.c -- SoC audio for mx27vis
*
* Copyright 2009 Vista Silicon S.L.
* Author: Javier Martin
* javier.martin@vista-silicon.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "../codecs/wm8974.h"
#include "mx1_mx2-pcm.h"
#include "mxc-ssi.h"
#include <mach/gpio.h>
#include <mach/iomux.h>
#define IGNORED_ARG 0
static struct snd_soc_card mx27vis;
/**
* This function connects SSI1 (HPCR1) as slave to
* SSI1 external signals (PPCR1)
* As slave, HPCR1 must set TFSDIR and TCLKDIR as inputs from
* port 4
*/
void audmux_connect_1_4(void)
{
pr_debug("AUDMUX: normal operation mode\n");
/* Reset HPCR1 and PPCR1 */
DAM_HPCR1 = 0x00000000;
DAM_PPCR1 = 0x00000000;
/* set to synchronous */
DAM_HPCR1 |= AUDMUX_HPCR_SYN;
DAM_PPCR1 |= AUDMUX_PPCR_SYN;
/* set Rx sources 1 <--> 4 */
DAM_HPCR1 |= AUDMUX_HPCR_RXDSEL(3); /* port 4 */
DAM_PPCR1 |= AUDMUX_PPCR_RXDSEL(0); /* port 1 */
/* set Tx frame and Clock direction and source 4 --> 1 output */
DAM_HPCR1 |= AUDMUX_HPCR_TFSDIR | AUDMUX_HPCR_TCLKDIR;
DAM_HPCR1 |= AUDMUX_HPCR_TFCSEL(3); /* TxDS and TxCclk from port 4 */
return;
}
static int mx27vis_hifi_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
unsigned int pll_out = 0, bclk = 0, fmt = 0, mclk = 0;
int ret = 0;
/*
* The WM8974 is better at generating accurate audio clocks than the
* MX27 SSI controller, so we will use it as master when we can.
*/
switch (params_rate(params)) {
case 8000:
fmt = SND_SOC_DAIFMT_CBM_CFM;
mclk = WM8974_MCLKDIV_12;
pll_out = 24576000;
break;
case 16000:
fmt = SND_SOC_DAIFMT_CBM_CFM;
pll_out = 12288000;
break;
case 48000:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_4;
pll_out = 12288000;
break;
case 96000:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_2;
pll_out = 12288000;
break;
case 11025:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_16;
pll_out = 11289600;
break;
case 22050:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_8;
pll_out = 11289600;
break;
case 44100:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_4;
mclk = WM8974_MCLKDIV_2;
pll_out = 11289600;
break;
case 88200:
fmt = SND_SOC_DAIFMT_CBM_CFM;
bclk = WM8974_BCLKDIV_2;
pll_out = 11289600;
break;
}
/* set codec DAI configuration */
ret = codec_dai->ops->set_fmt(codec_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
SND_SOC_DAIFMT_SYNC | fmt);
if (ret < 0) {
printk(KERN_ERR "Error from codec DAI configuration\n");
return ret;
}
/* set cpu DAI configuration */
ret = cpu_dai->ops->set_fmt(cpu_dai,
SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_SYNC | fmt);
if (ret < 0) {
printk(KERN_ERR "Error from cpu DAI configuration\n");
return ret;
}
/* Put DC field of STCCR to 1 (not zero) */
ret = cpu_dai->ops->set_tdm_slot(cpu_dai, 0, 2);
/* set the SSI system clock as input */
ret = cpu_dai->ops->set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
SND_SOC_CLOCK_IN);
if (ret < 0) {
printk(KERN_ERR "Error when setting system SSI clk\n");
return ret;
}
/* set codec BCLK division for sample rate */
ret = codec_dai->ops->set_clkdiv(codec_dai, WM8974_BCLKDIV, bclk);
if (ret < 0) {
printk(KERN_ERR "Error when setting BCLK division\n");
return ret;
}
/* codec PLL input is 25 MHz */
ret = codec_dai->ops->set_pll(codec_dai, IGNORED_ARG, IGNORED_ARG,
25000000, pll_out);
if (ret < 0) {
printk(KERN_ERR "Error when setting PLL input\n");
return ret;
}
/*set codec MCLK division for sample rate */
ret = codec_dai->ops->set_clkdiv(codec_dai, WM8974_MCLKDIV, mclk);
if (ret < 0) {
printk(KERN_ERR "Error when setting MCLK division\n");
return ret;
}
return 0;
}
static int mx27vis_hifi_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
/* disable the PLL */
return codec_dai->ops->set_pll(codec_dai, IGNORED_ARG, 0, 0);
}
/*
* mx27vis WM8974 HiFi DAI opserations.
*/
static struct snd_soc_ops mx27vis_hifi_ops = {
.hw_params = mx27vis_hifi_hw_params,
.hw_free = mx27vis_hifi_hw_free,
};
static int mx27vis_suspend(struct platform_device *pdev, pm_message_t state)
{
return 0;
}
static int mx27vis_resume(struct platform_device *pdev)
{
return 0;
}
static int mx27vis_probe(struct platform_device *pdev)
{
int ret = 0;
ret = get_ssi_clk(0, &pdev->dev);
if (ret < 0) {
printk(KERN_ERR "%s: cant get ssi clock\n", __func__);
return ret;
}
return 0;
}
static int mx27vis_remove(struct platform_device *pdev)
{
put_ssi_clk(0);
return 0;
}
static struct snd_soc_dai_link mx27vis_dai[] = {
{ /* Hifi Playback*/
.name = "WM8974",
.stream_name = "WM8974 HiFi",
.cpu_dai = &imx_ssi_pcm_dai[0],
.codec_dai = &wm8974_dai,
.ops = &mx27vis_hifi_ops,
},
};
static struct snd_soc_card mx27vis = {
.name = "mx27vis",
.platform = &mx1_mx2_soc_platform,
.probe = mx27vis_probe,
.remove = mx27vis_remove,
.suspend_pre = mx27vis_suspend,
.resume_post = mx27vis_resume,
.dai_link = mx27vis_dai,
.num_links = ARRAY_SIZE(mx27vis_dai),
};
static struct snd_soc_device mx27vis_snd_devdata = {
.card = &mx27vis,
.codec_dev = &soc_codec_dev_wm8974,
};
static struct platform_device *mx27vis_snd_device;
/* Temporal definition of board specific behaviour */
void gpio_ssi_active(int ssi_num)
{
int ret = 0;
unsigned int ssi1_pins[] = {
PC20_PF_SSI1_FS,
PC21_PF_SSI1_RXD,
PC22_PF_SSI1_TXD,
PC23_PF_SSI1_CLK,
};
unsigned int ssi2_pins[] = {
PC24_PF_SSI2_FS,
PC25_PF_SSI2_RXD,
PC26_PF_SSI2_TXD,
PC27_PF_SSI2_CLK,
};
if (ssi_num == 0)
ret = mxc_gpio_setup_multiple_pins(ssi1_pins,
ARRAY_SIZE(ssi1_pins), "USB OTG");
else
ret = mxc_gpio_setup_multiple_pins(ssi2_pins,
ARRAY_SIZE(ssi2_pins), "USB OTG");
if (ret)
printk(KERN_ERR "Error requesting ssi %x pins\n", ssi_num);
}
static int __init mx27vis_init(void)
{
int ret;
mx27vis_snd_device = platform_device_alloc("soc-audio", -1);
if (!mx27vis_snd_device)
return -ENOMEM;
platform_set_drvdata(mx27vis_snd_device, &mx27vis_snd_devdata);
mx27vis_snd_devdata.dev = &mx27vis_snd_device->dev;
ret = platform_device_add(mx27vis_snd_device);
if (ret) {
printk(KERN_ERR "ASoC: Platform device allocation failed\n");
platform_device_put(mx27vis_snd_device);
}
/* WM8974 uses SSI1 (HPCR1) via AUDMUX port 4 for audio (PPCR1) */
gpio_ssi_active(0);
audmux_connect_1_4();
return ret;
}
static void __exit mx27vis_exit(void)
{
/* We should call some "ssi_gpio_inactive()" properly */
}
module_init(mx27vis_init);
module_exit(mx27vis_exit);
MODULE_AUTHOR("Javier Martin, javier.martin@vista-silicon.com");
MODULE_DESCRIPTION("ALSA SoC WM8974 mx27vis");
MODULE_LICENSE("GPL");
sound/soc/imx/mxc-ssi.c deleted 100644 → 0
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sound/soc/imx/mxc-ssi.h deleted 100644 → 0
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _IMX_SSI_H
#define _IMX_SSI_H
#include <mach/hardware.h>
/* SSI regs definition - MOVE to /arch/arm/plat-mxc/include/mach/ when stable */
#define SSI1_IO_BASE_ADDR IO_ADDRESS(SSI1_BASE_ADDR)
#define SSI2_IO_BASE_ADDR IO_ADDRESS(SSI2_BASE_ADDR)
#define STX0 0x00
#define STX1 0x04
#define SRX0 0x08
#define SRX1 0x0c
#define SCR 0x10
#define SISR 0x14
#define SIER 0x18
#define STCR 0x1c
#define SRCR 0x20
#define STCCR 0x24
#define SRCCR 0x28
#define SFCSR 0x2c
#define STR 0x30
#define SOR 0x34
#define SACNT 0x38
#define SACADD 0x3c
#define SACDAT 0x40
#define SATAG 0x44
#define STMSK 0x48
#define SRMSK 0x4c
#define SSI1_STX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX0)))
#define SSI1_STX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STX1)))
#define SSI1_SRX0 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX0)))
#define SSI1_SRX1 (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRX1)))
#define SSI1_SCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SCR)))
#define SSI1_SISR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SISR)))
#define SSI1_SIER (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SIER)))
#define SSI1_STCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCR)))
#define SSI1_SRCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCR)))
#define SSI1_STCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STCCR)))
#define SSI1_SRCCR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRCCR)))
#define SSI1_SFCSR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SFCSR)))
#define SSI1_STR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STR)))
#define SSI1_SOR (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SOR)))
#define SSI1_SACNT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACNT)))
#define SSI1_SACADD (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACADD)))
#define SSI1_SACDAT (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SACDAT)))
#define SSI1_SATAG (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SATAG)))
#define SSI1_STMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + STMSK)))
#define SSI1_SRMSK (*((volatile u32 *)(SSI1_IO_BASE_ADDR + SRMSK)))
#define SSI2_STX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX0)))
#define SSI2_STX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STX1)))
#define SSI2_SRX0 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX0)))
#define SSI2_SRX1 (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRX1)))
#define SSI2_SCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SCR)))
#define SSI2_SISR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SISR)))
#define SSI2_SIER (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SIER)))
#define SSI2_STCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCR)))
#define SSI2_SRCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCR)))
#define SSI2_STCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STCCR)))
#define SSI2_SRCCR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRCCR)))
#define SSI2_SFCSR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SFCSR)))
#define SSI2_STR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STR)))
#define SSI2_SOR (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SOR)))
#define SSI2_SACNT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACNT)))
#define SSI2_SACADD (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACADD)))
#define SSI2_SACDAT (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SACDAT)))
#define SSI2_SATAG (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SATAG)))
#define SSI2_STMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + STMSK)))
#define SSI2_SRMSK (*((volatile u32 *)(SSI2_IO_BASE_ADDR + SRMSK)))
#define SSI_SCR_CLK_IST (1 << 9)
#define SSI_SCR_TCH_EN (1 << 8)
#define SSI_SCR_SYS_CLK_EN (1 << 7)
#define SSI_SCR_I2S_MODE_NORM (0 << 5)
#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
#define SSI_SCR_SYN (1 << 4)
#define SSI_SCR_NET (1 << 3)
#define SSI_SCR_RE (1 << 2)
#define SSI_SCR_TE (1 << 1)
#define SSI_SCR_SSIEN (1 << 0)
#define SSI_SISR_CMDAU (1 << 18)
#define SSI_SISR_CMDDU (1 << 17)
#define SSI_SISR_RXT (1 << 16)
#define SSI_SISR_RDR1 (1 << 15)
#define SSI_SISR_RDR0 (1 << 14)
#define SSI_SISR_TDE1 (1 << 13)
#define SSI_SISR_TDE0 (1 << 12)
#define SSI_SISR_ROE1 (1 << 11)
#define SSI_SISR_ROE0 (1 << 10)
#define SSI_SISR_TUE1 (1 << 9)
#define SSI_SISR_TUE0 (1 << 8)
#define SSI_SISR_TFS (1 << 7)
#define SSI_SISR_RFS (1 << 6)
#define SSI_SISR_TLS (1 << 5)
#define SSI_SISR_RLS (1 << 4)
#define SSI_SISR_RFF1 (1 << 3)
#define SSI_SISR_RFF0 (1 << 2)
#define SSI_SISR_TFE1 (1 << 1)
#define SSI_SISR_TFE0 (1 << 0)
#define SSI_SIER_RDMAE (1 << 22)
#define SSI_SIER_RIE (1 << 21)
#define SSI_SIER_TDMAE (1 << 20)
#define SSI_SIER_TIE (1 << 19)
#define SSI_SIER_CMDAU_EN (1 << 18)
#define SSI_SIER_CMDDU_EN (1 << 17)
#define SSI_SIER_RXT_EN (1 << 16)
#define SSI_SIER_RDR1_EN (1 << 15)
#define SSI_SIER_RDR0_EN (1 << 14)
#define SSI_SIER_TDE1_EN (1 << 13)
#define SSI_SIER_TDE0_EN (1 << 12)
#define SSI_SIER_ROE1_EN (1 << 11)
#define SSI_SIER_ROE0_EN (1 << 10)
#define SSI_SIER_TUE1_EN (1 << 9)
#define SSI_SIER_TUE0_EN (1 << 8)
#define SSI_SIER_TFS_EN (1 << 7)
#define SSI_SIER_RFS_EN (1 << 6)
#define SSI_SIER_TLS_EN (1 << 5)
#define SSI_SIER_RLS_EN (1 << 4)
#define SSI_SIER_RFF1_EN (1 << 3)
#define SSI_SIER_RFF0_EN (1 << 2)
#define SSI_SIER_TFE1_EN (1 << 1)
#define SSI_SIER_TFE0_EN (1 << 0)
#define SSI_STCR_TXBIT0 (1 << 9)
#define SSI_STCR_TFEN1 (1 << 8)
#define SSI_STCR_TFEN0 (1 << 7)
#define SSI_STCR_TFDIR (1 << 6)
#define SSI_STCR_TXDIR (1 << 5)
#define SSI_STCR_TSHFD (1 << 4)
#define SSI_STCR_TSCKP (1 << 3)
#define SSI_STCR_TFSI (1 << 2)
#define SSI_STCR_TFSL (1 << 1)
#define SSI_STCR_TEFS (1 << 0)
#define SSI_SRCR_RXBIT0 (1 << 9)
#define SSI_SRCR_RFEN1 (1 << 8)
#define SSI_SRCR_RFEN0 (1 << 7)
#define SSI_SRCR_RFDIR (1 << 6)
#define SSI_SRCR_RXDIR (1 << 5)
#define SSI_SRCR_RSHFD (1 << 4)
#define SSI_SRCR_RSCKP (1 << 3)
#define SSI_SRCR_RFSI (1 << 2)
#define SSI_SRCR_RFSL (1 << 1)
#define SSI_SRCR_REFS (1 << 0)
#define SSI_STCCR_DIV2 (1 << 18)
#define SSI_STCCR_PSR (1 << 15)
#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)
#define SSI_STCCR_PM(x) (((x) & 0xff) << 0)
#define SSI_STCCR_WL_MASK (0xf << 13)
#define SSI_STCCR_DC_MASK (0x1f << 8)
#define SSI_STCCR_PM_MASK (0xff << 0)
#define SSI_SRCCR_DIV2 (1 << 18)
#define SSI_SRCCR_PSR (1 << 15)
#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)
#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)
#define SSI_SRCCR_WL_MASK (0xf << 13)
#define SSI_SRCCR_DC_MASK (0x1f << 8)
#define SSI_SRCCR_PM_MASK (0xff << 0)
#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)
#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)
#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)
#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)
#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)
#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)
#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)
#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)
#define SSI_STR_TEST (1 << 15)
#define SSI_STR_RCK2TCK (1 << 14)
#define SSI_STR_RFS2TFS (1 << 13)
#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)
#define SSI_STR_TXD2RXD (1 << 7)
#define SSI_STR_TCK2RCK (1 << 6)
#define SSI_STR_TFS2RFS (1 << 5)
#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)
#define SSI_SOR_CLKOFF (1 << 6)
#define SSI_SOR_RX_CLR (1 << 5)
#define SSI_SOR_TX_CLR (1 << 4)
#define SSI_SOR_INIT (1 << 3)
#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)
#define SSI_SOR_SYNRST (1 << 0)
#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
#define SSI_SACNT_WR (x << 4)
#define SSI_SACNT_RD (x << 3)
#define SSI_SACNT_TIF (x << 2)
#define SSI_SACNT_FV (x << 1)
#define SSI_SACNT_AC97EN (x << 0)
/* Watermarks for FIFO's */
#define TXFIFO_WATERMARK 0x4
#define RXFIFO_WATERMARK 0x4
/* i.MX DAI SSP ID's */
#define IMX_DAI_SSI0 0 /* SSI1 FIFO 0 */
#define IMX_DAI_SSI1 1 /* SSI1 FIFO 1 */
#define IMX_DAI_SSI2 2 /* SSI2 FIFO 0 */
#define IMX_DAI_SSI3 3 /* SSI2 FIFO 1 */
/* SSI clock sources */
#define IMX_SSP_SYS_CLK 0
/* SSI audio dividers */
#define IMX_SSI_TX_DIV_2 0
#define IMX_SSI_TX_DIV_PSR 1
#define IMX_SSI_TX_DIV_PM 2
#define IMX_SSI_RX_DIV_2 3
#define IMX_SSI_RX_DIV_PSR 4
#define IMX_SSI_RX_DIV_PM 5
/* SSI Div 2 */
#define IMX_SSI_DIV_2_OFF (~SSI_STCCR_DIV2)
#define IMX_SSI_DIV_2_ON SSI_STCCR_DIV2
extern struct snd_soc_dai imx_ssi_pcm_dai[4];
extern int get_ssi_clk(int ssi, struct device *dev);
extern void put_ssi_clk(int ssi);
#endif
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