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Commit ea5e9fa9 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] Remove Nino support 

This patch mostly removes the support for the Phillips Nino at the
request of the author.  The only remaining bits are directly related
to the SOC the Nino is based on which is used by other ports.
parent 7ec815be
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arch/mips/defconfig-nino deleted 100644 → 0
View file @ 7ec815be
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_NINO=y
# CONFIG_NINO_4MB is not set
CONFIG_NINO_8MB=y
# CONFIG_NINO_16MB is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_PC_KEYB=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_PCI is not set
# CONFIG_I8259 is not set
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
CONFIG_KMOD=y
#
# CPU selection
#
CONFIG_CPU_R3000=y
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_ADVANCED is not set
# CONFIG_CPU_HAS_LLSC is not set
# CONFIG_CPU_HAS_LLDSCD is not set
# CONFIG_CPU_HAS_WB is not set
#
# General setup
#
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=y
# CONFIG_NET is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_SYSCTL is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=2048
CONFIG_BLK_DEV_INITRD=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
# CONFIG_SCSI is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# ISDN subsystem
#
#
# Old CD-ROM drivers (not SCSI, not IDE)
#
# CONFIG_CD_NO_IDESCSI is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_COMPUTONE is not set
# CONFIG_ROCKETPORT is not set
# CONFIG_CYCLADES is not set
# CONFIG_DIGIEPCA is not set
# CONFIG_DIGI is not set
# CONFIG_ESPSERIAL is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_ISI is not set
# CONFIG_SYNCLINK is not set
# CONFIG_N_HDLC is not set
# CONFIG_RISCOM8 is not set
# CONFIG_SPECIALIX is not set
# CONFIG_SX is not set
# CONFIG_RIO is not set
# CONFIG_STALDRV is not set
CONFIG_SERIAL_TX3912=y
CONFIG_SERIAL_TX3912_CONSOLE=y
# CONFIG_AU1000_UART is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
#
# CONFIG_INPUT_GAMEPORT is not set
#
# Input core support is needed for gameports
#
#
# Input core support is needed for joysticks
#
# CONFIG_QIC02_TAPE is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_SMB_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
#
# USB Multimedia devices
#
#
# Video4Linux support is needed for USB Multimedia device support
#
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
#
# Networking support is needed for USB Networking device support
#
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
#
# Miscellaneous USB drivers
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
#
# Input core support
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
arch/mips/philips/nino/Makefile deleted 100644 → 0
View file @ 7ec815be
#
# Makefile for the Philips Nino specific parts of the kernel
#
obj-y := int-handler.o setup.o irq.o time.o reset.o rtc.o prom.o power.o
obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o
obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
ramdisk.o:
$(MAKE) -C ramdisk
mv ramdisk/ramdisk.o ramdisk.o
clean:
rm -f *.o
arch/mips/philips/nino/int-handler.S deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/int-handler.S
*
* Copyright (C) 1999 Harald Koerfgen
* Copyright (C) 2000 Jim Pick (jim@jimpick.com)
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Interrupt handler for Philips Nino.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/tx3912.h>
.data
.globl HighPriVect
HighPriVect: .word spurious # Reserved
.word io_posnegint0 # IOPOSINT(0) or IONEGINT(0)
.word spurious # CHIDMACNTINT
.word spurious # TELDMACNTINT
.word spurious # SNDDMACNTINT
.word spurious # Reserved
.word io_negint56 # IONEGINT(6) or IONEGINT(5)
.word spurious # Reserved
.word io_posint56 # IOPOSINT(6) or IOPOSINT(5)
.word spurious # Reserved
.word spurious # UARTBRXINT
.word uarta_rx # UARTARXINT
.word spurious # Reserved
.word periodic_timer # PERINT
.word spurious # ALARMINT
.word spurious # POSPWROKINT or NEGPWROKINT
/*
* Here is the entry point to handle all interrupts.
*/
.text
.set noreorder
.align 5
NESTED(nino_handle_int, PT_SIZE, ra)
.set noat
SAVE_ALL
CLI
.set at
/*
* Get pending Interrupts
*/
mfc0 t0, CP0_CAUSE # Get pending interrupts
andi t2, t0, IE_IRQ4 # IRQ4 (high priority)
bne t2, IE_IRQ4, low_priority
nop
/*
* Ok, we've got a high priority interrupt (a.k.a. an external interrupt).
* Read Interrupt Status Register 6 to get vector.
*/
high_priority:
lui t0, %hi(IntStatus6)
lw t1, %lo(IntStatus6)(t0)
andi t1, INT6_INTVECT
la t2, HighPriVect
addu t1, t1, t2
lw t2, 0(t1)
jr t2
nop
/*
* Ok, we've got one of over a hundred other interrupts.
*/
low_priority:
lui t0, %hi(IntStatus1)
lw t1, %lo(IntStatus1)(t0)
j handle_it
li a0, 20
/*
* We don't currently handle spurious interrupts.
*/
spurious:
j spurious_interrupt
nop
/*
* We have the IRQ number, dispatch to the real handler.
*/
handle_it: jal do_IRQ
move a1,sp
j ret_from_irq
nop
/************************************
* High priority interrupt mappings *
************************************/
/*
* Periodic timer - IRQ 0
*/
periodic_timer:
j handle_it
li a0, 0
/*
* UARTA RX - IRQ 3
*/
uarta_rx:
j handle_it
li a0, 3
/*
* GPIO Pin 0 transition - IRQ 10
*/
io_posnegint0:
j handle_it
li a0, 10
/*
* GPIO Pin 5 or 6 transition (0-to-1) - IRQ 11
*/
io_posint56:
j handle_it
li a0, 11
/*
* GPIO Pin 5 or 6 transition (1-to-0) - IRQ 12
*/
io_negint56:
j handle_it
li a0, 12
END(nino_handle_int)
arch/mips/philips/nino/irq.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/irq.c
*
* Copyright (C) 1992 Linus Torvalds
* Copyright (C) 1999 Harald Koerfgen
* Copyright (C) 2000 Pavel Machek (pavel@suse.cz)
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Generic interrupt handler for Philips Nino.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/seq_file.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/tx3912.h>
unsigned long spurious_count = 0;
irq_cpustat_t irq_stat [NR_CPUS];
static inline void mask_irq(unsigned int irq_nr)
{
switch (irq_nr) {
case 0: /* Periodic Timer Interrupt */
IntClear5 = INT5_PERIODICINT;
IntClear6 = INT6_PERIODICINT;
IntEnable6 &= ~INT6_PERIODICINT;
break;
case 3:
/* Serial port receive interrupt */
break;
case 2:
/* Serial port transmit interrupt */
break;
default:
printk( "Attempt to mask unknown IRQ %d?\n", irq_nr );
}
}
static inline void unmask_irq(unsigned int irq_nr)
{
switch (irq_nr) {
case 0:
IntEnable6 |= INT6_PERIODICINT;
break;
case 3:
/* Serial port receive interrupt */
break;
case 2:
/* Serial port transmit interrupt */
break;
default:
printk( "Attempt to unmask unknown IRQ %d?\n", irq_nr );
}
}
void disable_irq(unsigned int irq_nr)
{
unsigned long flags;
save_and_cli(flags);
mask_irq(irq_nr);
restore_flags(flags);
}
void enable_irq(unsigned int irq_nr)
{
unsigned long flags;
save_and_cli(flags);
unmask_irq(irq_nr);
restore_flags(flags);
}
/*
* Pointers to the low-level handlers: first the general ones, then the
* fast ones, then the bad ones.
*/
extern void interrupt(void);
static struct irqaction *irq_action[NR_IRQS] =
{
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
int show_interrupts(struct seq_file *p, void *v)
{
int i;
struct irqaction *action;
unsigned long flags;
for (i = 0; i < NR_IRQS; i++) {
local_irq_save(flags);
action = irq_action[i];
if (!action)
goto skip;
seq_printf(p, "%2d: %8d %c %s",
i, kstat_cpu(0).irqs[i],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action = action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_putc(p, '\n');
skip:
local_irq_restore(flags);
}
return 0;
}
atomic_t __mips_bh_counter;
/*
* do_IRQ handles IRQ's that have been installed without the
* SA_INTERRUPT flag: it uses the full signal-handling return
* and runs with other interrupts enabled. All relatively slow
* IRQ's should use this format: notably the keyboard/timer
* routines.
*/
asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
{
struct irqaction *action;
int do_random, cpu;
if (irq == 20) {
if (IntStatus2 & 0xfffff00) {
if (IntStatus2 & 0x0f000000)
return do_IRQ(2, regs);
}
}
cpu = smp_processor_id();
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
if (irq == 20) {
printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n",
IntStatus1, IntStatus2, IntStatus3,
IntStatus4, IntStatus5 );
printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n",
IntEnable1, IntEnable2, IntEnable3,
IntEnable4, IntEnable5 );
}
mask_irq(irq);
action = *(irq + irq_action);
if (action) {
if (!(action->flags & SA_INTERRUPT))
local_irq_enable();
do_random = 0;
do {
do_random |= action->flags;
action->handler(irq, action->dev_id, regs);
action = action->next;
} while (action);
if (do_random & SA_SAMPLE_RANDOM)
add_interrupt_randomness(irq);
unmask_irq(irq);
local_irq_disable();
} else {
IntClear1 = ~0;
IntClear3 = ~0;
IntClear4 = ~0;
IntClear5 = ~0;
unmask_irq(irq);
}
irq_exit(cpu, irq);
/* unmasking and bottom half handling is done magically for us. */
}
/*
* Idea is to put all interrupts
* in a single table and differenciate them just by number.
*/
int setup_nino_irq(int irq, struct irqaction *new)
{
int shared = 0;
struct irqaction *old, **p;
unsigned long flags;
p = irq_action + irq;
if ((old = *p) != NULL) {
/* Can't share interrupts unless both agree to */
if (!(old->flags & new->flags & SA_SHIRQ))
return -EBUSY;
/* Can't share interrupts unless both are same type */
if ((old->flags ^ new->flags) & SA_INTERRUPT)
return -EBUSY;
/* add new interrupt at end of irq queue */
do {
p = &old->next;
old = *p;
} while (old);
shared = 1;
}
if (new->flags & SA_SAMPLE_RANDOM)
rand_initialize_irq(irq);
save_and_cli(flags);
*p = new;
if (!shared) {
unmask_irq(irq);
}
restore_flags(flags);
return 0;
}
int request_irq(unsigned int irq,
void (*handler) (int, void *, struct pt_regs *),
unsigned long irqflags,
const char *devname,
void *dev_id)
{
int retval;
struct irqaction *action;
if (irq >= NR_IRQS)
return -EINVAL;
if (!handler)
return -EINVAL;
action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if (!action)
return -ENOMEM;
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->next = NULL;
action->dev_id = dev_id;
retval = setup_nino_irq(irq, action);
if (retval)
kfree(action);
return retval;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction *action, **p;
unsigned long flags;
if (irq >= NR_IRQS) {
printk(KERN_CRIT __FUNCTION__ ": trying to free IRQ%d\n", irq);
return;
}
for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) {
if (action->dev_id != dev_id)
continue;
/* Found it - now free it */
save_and_cli(flags);
*p = action->next;
if (!irq[irq_action])
mask_irq(irq);
restore_flags(flags);
kfree(action);
return;
}
printk(KERN_CRIT __FUNCTION__ ": trying to free free IRQ%d\n", irq);
}
unsigned long probe_irq_on(void)
{
/* TODO */
return 0;
}
int probe_irq_off(unsigned long irqs)
{
/* TODO */
return 0;
}
void __init init_IRQ(void)
{
irq_setup();
}
arch/mips/philips/nino/kgdb.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/kgdb.c
*
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Kernel debugging on the Philips Nino.
*/
#include <asm/system.h>
#include <asm/tx3912.h>
static int remoteDebugInitialized = 0;
void debugInit(void)
{
/*
* If low-level debugging (before GDB or console operational) is
* configured, then we do not need to re-initialize the UART.
*/
#ifndef CONFIG_DEBUG_LL
earlyInitUartPR31700();
#endif
}
char getDebugChar(void)
{
char buf;
unsigned long int2, flags;
if (!remoteDebugInitialized) {
debugInit();
remoteDebugInitialized = 1;
}
save_and_cli(flags);
int2 = IntEnable2;
IntEnable2 = 0;
while(!(UartA_Ctrl1 & UART_RX_HOLD_FULL));
buf = UartA_Data;
IntEnable2 = int2;
restore_flags(flags);
return buf;
}
int putDebugChar(char c)
{
int i;
unsigned long int2;
if (!remoteDebugInitialized) {
debugInit();
remoteDebugInitialized = 1;
}
int2 = IntEnable2;
IntEnable2 &=
~(INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY);
for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++);
IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
UartA_Data = c;
for (i = 0; !(IntStatus2 & INT2_UARTATXINT) && (i < 10000); i++);
IntClear2 = INT2_UARTATXINT | INT2_UARTATXOVERRUN | INT2_UARTAEMPTY;
IntEnable2 = int2;
return 1;
}
arch/mips/philips/nino/power.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/power.c
*
* Copyright (C) 2000 Jim Pick <jim@jimpick.com>
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Power management routines on the Philips Nino.
*/
#include <asm/tx3912.h>
void nino_wait(void)
{
/* We stop the CPU to conserve power */
PowerControl |= PWR_STOPCPU;
/*
* We wait until an interrupt happens...
*/
/* We resume here */
PowerControl &= ~PWR_STOPCPU;
/* Give ourselves a little delay */
__asm__ __volatile__(
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t");
}
arch/mips/philips/nino/prom.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/prom.c
*
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Early initialization code for the Philips Nino.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/page.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
#ifdef CONFIG_FB_TX3912
extern u_long tx3912fb_paddr;
extern u_long tx3912fb_vaddr;
extern u_long tx3912fb_size;
#endif
/* Do basic initialization */
void __init prom_init(int argc, char **argv,
unsigned long magic, int *prom_vec)
{
u_long free_end, mem_size;
u_int i;
/*
* collect args and prepare cmd_line
*/
for (i = 1; i < argc; i++) {
strcat(arcs_cmdline, argv[i]);
if (i < (argc - 1))
strcat(arcs_cmdline, " ");
}
mips_machgroup = MACH_GROUP_PHILIPS;
mips_machtype = MACH_PHILIPS_NINO;
#ifdef CONFIG_NINO_4MB
mem_size = 4 << 20;
#elif CONFIG_NINO_8MB
mem_size = 8 << 20;
#elif CONFIG_NINO_16MB
mem_size = 16 << 20;
#endif
#ifdef CONFIG_FB_TX3912
/*
* The LCD controller requires that the framebuffer
* start address fall within a 1MB segment and is
* aligned on a 16 byte boundary. The way to assure
* this is to place the framebuffer at the end of
* memory and mark it as reserved.
*/
free_end = (mem_size - tx3912fb_size) & PAGE_MASK;
add_memory_region(0, free_end, BOOT_MEM_RAM);
add_memory_region(free_end, (mem_size - free_end), BOOT_MEM_RESERVED);
/*
* Calculate physical and virtual addresses for
* the beginning of the framebuffer.
*/
tx3912fb_paddr = PHYSADDR(free_end);
tx3912fb_vaddr = KSEG1ADDR(free_end);
#else
add_memory_region(0, mem_size, BOOT_MEM_RAM);
#endif
}
void __init prom_free_prom_memory (void)
{
}
arch/mips/philips/nino/ramdisk/Makefile deleted 100644 → 0
View file @ 7ec815be
#
# Makefile for the Philips Nino ramdisk
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
ramdisk.o: ramdisk.gz ld.script
$(LD) $(LDFLAGS) -T ld.script -b binary -o $@ ramdisk.gz
arch/mips/philips/nino/ramdisk/ld.script deleted 100644 → 0
View file @ 7ec815be
OUTPUT_FORMAT("ecoff-littlemips")
OUTPUT_ARCH(mips)
SECTIONS
{
.initrd :
{
*(.data)
}
}
arch/mips/philips/nino/reset.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/reset.c
*
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Generic restart, halt and power off functions for Philips Nino.
*/
#include <linux/init.h>
#include <asm/reboot.h>
void (*reset_vector)(void) = (void (*)(void)) 0xBFC00000;
void nino_machine_restart(char *command)
{
reset_vector();
}
void nino_machine_halt(void)
{
reset_vector();
}
void nino_machine_power_off(void)
{
reset_vector();
}
void __init setup_nino_reset_vectors(void)
{
_machine_restart = nino_machine_restart;
_machine_halt = nino_machine_halt;
_machine_power_off = nino_machine_power_off;
}
arch/mips/philips/nino/rtc.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/rtc.c
*
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Functions to access RTC on the Philips Nino.
*/
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
static unsigned char nino_rtc_read_data(unsigned long addr)
{
return 0;
}
static void nino_rtc_write_data(unsigned char data, unsigned long addr)
{
}
static int nino_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops nino_rtc_ops =
{
&nino_rtc_read_data,
&nino_rtc_write_data,
&nino_rtc_bcd_mode
};
arch/mips/philips/nino/setup.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/setup.c
*
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Interrupt and exception initialization for Philips Nino.
*/
#include <linux/console.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/sched.h>
#include <asm/addrspace.h>
#include <asm/gdb-stub.h>
#include <asm/irq.h>
#include <asm/wbflush.h>
#include <asm/tx3912.h>
extern struct rtc_ops nino_rtc_ops;
extern void nino_wait(void);
extern void setup_nino_reset_vectors(void);
extern asmlinkage void nino_handle_int(void);
extern int setup_nino_irq(int, struct irqaction *);
void (*board_time_init) (struct irqaction * irq);
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
extern void breakpoint(void);
static int remote_debug = 0;
#endif
static void __init nino_irq_setup(void)
{
unsigned int tmp;
/* Turn all interrupts off */
IntEnable1 = 0;
IntEnable2 = 0;
IntEnable3 = 0;
IntEnable4 = 0;
IntEnable5 = 0;
IntEnable6 = 0;
/* Clear all interrupts */
IntClear1 = 0xffffffff;
IntClear2 = 0xffffffff;
IntClear3 = 0xffffffff;
IntClear4 = 0xffffffff;
IntClear5 = 0xffffffff;
IntClear6 = 0xffffffff;
/*
* Enable only the interrupts for the UART and negative
* edge (1-to-0) triggered multi-function I/O pins.
*/
change_cp0_status(ST0_BEV, 0);
tmp = read_32bit_cp0_register(CP0_STATUS);
change_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4);
/* Register the global interrupt handler */
set_except_vector(0, nino_handle_int);
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
static __init void nino_time_init(struct irqaction *irq)
{
unsigned int scratch = 0;
/*
* Enable periodic interrupts
*/
setup_nino_irq(0, irq);
RTCperiodTimer = PER_TIMER_COUNT;
RTCtimerControl = TIM_ENPERTIMER;
IntEnable5 |= INT5_PERIODICINT;
scratch = inl(TX3912_CLK_CTRL_BASE);
scratch |= TX3912_CLK_CTRL_ENTIMERCLK;
outl(scratch, TX3912_CLK_CTRL_BASE);
/* Enable all interrupts */
IntEnable6 |= INT6_GLOBALEN | INT6_PERIODICINT;
}
void __init nino_setup(void)
{
irq_setup = nino_irq_setup;
board_time_init = nino_time_init;
/* Base address to use for PC type I/O accesses */
mips_io_port_base = KSEG1ADDR(0xB0C00000);
setup_nino_reset_vectors();
/* Function called during process idle (cpu_idle) */
cpu_wait = nino_wait;
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_REMOTE_DEBUG
remote_debug = 1;
#endif
rtc_ops = &nino_rtc_ops;
}
arch/mips/philips/nino/time.c deleted 100644 → 0
View file @ 7ec815be
/*
* linux/arch/mips/philips/nino/time.c
*
* Copyright (C) 1999 Harald Koerfgen
* Copyright (C) 2000 Pavel Machek (pavel@suse.cz)
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Time handling functinos for Philips Nino.
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/delay.h>
#include <asm/tx3912.h>
extern volatile unsigned long wall_jiffies;
static struct timeval xbase;
#define USECS_PER_JIFFY (1000000/HZ)
/*
* Poll the Interrupt Status Registers
*/
#undef POLL_STATUS
static unsigned long do_gettimeoffset(void)
{
/*
* This is a kludge
*/
return 0;
}
static
void inline readRTC(unsigned long *high, unsigned long *low)
{
/* read twice, and keep reading till we find two
* the same pairs. This is needed in case the RTC
* was updating its registers and we read a old
* High but a new Low. */
do {
*high = RTChigh & RTC_HIGHMASK;
*low = RTClow;
} while (*high != (RTChigh & RTC_HIGHMASK) || RTClow!=*low);
}
/*
* This version of gettimeofday has near millisecond resolution.
*/
void do_gettimeofday(struct timeval *tv)
{
unsigned long flags;
unsigned long seq;
unsigned long high, low;
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
// 40 bit RTC, driven by 32khz source:
// +-----------+-----------------------------------------+
// | HHHH.HHHH | LLLL.LLLL.LLLL.LLLL.LMMM.MMMM.MMMM.MMMM |
// +-----------+-----------------------------------------+
readRTC(&high,&low);
tv->tv_sec = (high << 17) | (low >> 15);
tv->tv_usec = (low % 32768) * 1953 / 64;
tv->tv_sec += xbase.tv_sec;
tv->tv_usec += xbase.tv_usec;
tv->tv_usec += do_gettimeoffset();
/*
* xtime is atomically updated in timer_bh. lost_ticks is
* nonzero if the timer bottom half hasnt executed yet.
*/
if (jiffies - wall_jiffies)
tv->tv_usec += USECS_PER_JIFFY;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
if (tv->tv_usec >= 1000000) {
tv->tv_usec -= 1000000;
tv->tv_sec++;
}
}
void do_settimeofday(struct timeval *tv)
{
write_seqlock_irq(&xtime_lock);
/* This is revolting. We need to set the xtime.tv_usec
* correctly. However, the value in this location is
* is value at the last tick.
* Discover what correction gettimeofday
* would have done, and then undo it!
*/
tv->tv_usec -= do_gettimeoffset();
if (tv->tv_usec < 0) {
tv->tv_usec += 1000000;
tv->tv_sec--;
}
/* reset RTC to 0 (real time is xbase + RTC) */
xbase = *tv;
RTCtimerControl |= TIM_RTCCLEAR;
RTCtimerControl &= ~TIM_RTCCLEAR;
RTCalarmHigh = RTCalarmLow = ~0UL;
xtime = *tv;
time_state = TIME_BAD;
time_maxerror = MAXPHASE;
time_esterror = MAXPHASE;
write_sequnlock_irq(&xtime_lock);
}
static int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
return retval;
}
/* last time the cmos clock got updated */
static long last_rtc_update = 0;
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
*/
int do_write = 1;
static void
timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
#ifdef POLL_STATUS
static unsigned long old_IntStatus1 = 0;
static unsigned long old_IntStatus3 = 0;
static unsigned long old_IntStatus4 = 0;
static unsigned long old_IntStatus5 = 0;
static int counter = 0;
int i;
new_spircv = SPIData & 0xff;
if ((old_spircv != new_spircv) && (new_spircv != 0xff)) {
printk( "SPIData changed: %x\n", new_spircv );
}
old_spircv = new_spircv;
if (do_write)
SPIData = 0;
#endif
if (!user_mode(regs)) {
if (prof_buffer && current->pid) {
extern int _stext;
unsigned long pc = regs->cp0_epc;
pc -= (unsigned long) &_stext;
pc >>= prof_shift;
/*
* Dont ignore out-of-bounds pc values silently,
* put them into the last histogram slot, so if
* present, they will show up as a sharp peak.
*/
if (pc > prof_len - 1)
pc = prof_len - 1;
atomic_inc((atomic_t *) & prof_buffer[pc]);
}
}
/*
* aaaand... action!
*/
do_timer(regs);
/*
* If we have an externally syncronized Linux clock, then update
* CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
* called as close as possible to 500 ms before the new second starts.
*/
if (time_state != TIME_BAD && xtime.tv_sec > last_rtc_update + 660 &&
xtime.tv_usec > 500000 - (tick >> 1) &&
xtime.tv_usec < 500000 + (tick >> 1))
{
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
}
}
static struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0,
"timer", NULL, NULL};
void (*board_time_init) (struct irqaction * irq);
int __init time_init(void)
{
struct timeval starttime;
starttime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
starttime.tv_usec = 0;
do_settimeofday(&starttime);
board_time_init(&irq0);
return 0;
}
include/asm-mips/tx3912.h
View file @ ea5e9fa9
/* /*
* linux/include/asm-mips/tx3912.h * include/asm-mips/tx3912.h
* *
* Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
* *
...@@ -7,77 +7,22 @@ ...@@ -7,77 +7,22 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
* *
* Register includes for TMPR3912/05 and PR31700 processors * Registers for TMPR3912/05 and PR31700 processors
*/ */
#ifndef __TX3912_H__ #ifndef _TX3912_H_
#define __TX3912_H__ #define _TX3912_H_
#include <asm/addrspace.h> /*****************************************************************************
* Clock Subsystem *
/****************************************************************************** * --------------- *
* * Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals *
* 01 General macro definitions *****************************************************************************/
* #define TX3912_CLK_CTRL 0x01c0
******************************************************************************/
#define REGISTER_BASE 0xb0c00000
#ifndef _LANGUAGE_ASSEMBLY
#define REG_AT(x) (*((volatile unsigned long *)(REGISTER_BASE + x)))
#else
#define REG_AT(x) (REGISTER_BASE + x)
#endif
#define BIT(x) (1 << x)
/******************************************************************************
*
* 02 Bus Interface Unit
*
******************************************************************************/
#define MemConfig0 REG_AT(0x000)
#define MemConfig1 REG_AT(0x004)
#define MemConfig2 REG_AT(0x008)
#define MemConfig3 REG_AT(0x00c)
#define MemConfig4 REG_AT(0x010)
#define MemConfig5 REG_AT(0x014)
#define MemConfig6 REG_AT(0x018)
#define MemConfig7 REG_AT(0x01c)
#define MemConfig8 REG_AT(0x020)
/* Memory config register 1 */
#define MEM1_ENCS1USER BIT(21)
/* Memory config register 3 */
#define MEM3_CARD1ACCVAL_MASK (BIT(24) | BIT(25) | BIT(26) | BIT(27))
#define MEM3_CARD1IOEN BIT(4)
/* Memory config register 4 */
#define MEM4_ARBITRATIONEN BIT(29)
#define MEM4_MEMPOWERDOWN BIT(16)
#define MEM4_ENREFRESH1 BIT(15)
#define MEM4_ENREFRESH0 BIT(14)
#define MEM4_ENWATCH BIT(24)
#define MEM4_WATCHTIMEVAL_MASK (0xf)
#define MEM4_WATCHTIMEVAL_SHIFT (20)
#define MEM4_WATCHTIME_VALUE (0xf)
/* /*
*********************************************************************** * Clock control register values
* *
* 06 Clock Module *
* *
***********************************************************************
*/ */
#define TX3912_CLK_CTRL_BASE (REGISTER_BASE + 0x1c0)
#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 #define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000
#define TX3912_CLK_CTRL_CHICLKDIV_SHIFT 24
#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 #define TX3912_CLK_CTRL_ENCLKTEST 0x00800000
#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 #define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000
#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 #define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000
...@@ -89,480 +34,328 @@ ...@@ -89,480 +34,328 @@
#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 #define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000
#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 #define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000
#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 #define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000
#define TX3912_CLK_CTRL_RESERVED 0x00001000 #define TX3912_CLK_CTRL_reserved1 0x00001000
#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 #define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800
#define TX3912_CLK_CTRL_SIBMCLKDIV_MASK 0x00000700 #define TX3912_CLK_CTRL_SIBMCLKDIV_6 0x00000600
#define TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT 8 #define TX3912_CLK_CTRL_SIBMCLKDIV_5 0x00000500
#define TX3912_CLK_CTRL_SIBMCLKDIV_4 0x00000400
#define TX3912_CLK_CTRL_SIBMCLKDIV_3 0x00000300
#define TX3912_CLK_CTRL_SIBMCLKDIV_2 0x00000200
#define TX3912_CLK_CTRL_SIBMCLKDIV_1 0x00000100
#define TX3912_CLK_CTRL_CSERSEL 0x00000080 #define TX3912_CLK_CTRL_CSERSEL 0x00000080
#define TX3912_CLK_CTRL_CSERDIV_MASK 0x00000070 #define TX3912_CLK_CTRL_CSERDIV_6 0x00000060
#define TX3912_CLK_CTRL_CSERDIV_SHIFT 4 #define TX3912_CLK_CTRL_CSERDIV_5 0x00000050
#define TX3912_CLK_CTRL_CSERDIV_4 0x00000040
#define TX3912_CLK_CTRL_CSERDIV_3 0x00000030
#define TX3912_CLK_CTRL_CSERDIV_2 0x00000020
#define TX3912_CLK_CTRL_CSERDIV_1 0x00000010
#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 #define TX3912_CLK_CTRL_ENCSERCLK 0x00000008
#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 #define TX3912_CLK_CTRL_ENIRCLK 0x00000004
#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 #define TX3912_CLK_CTRL_ENUARTACLK 0x00000002
#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 #define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001
/*****************************************************************************
* Interrupt Subsystem *
* ------------------- *
* Chapter 8 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals *
*****************************************************************************/
#define TX3912_INT1_CLEAR 0x0100
#define TX3912_INT2_CLEAR 0x0104
#define TX3912_INT3_CLEAR 0x0108
#define TX3912_INT4_CLEAR 0x010c
#define TX3912_INT5_CLEAR 0x0110
#define TX3912_INT1_ENABLE 0x0118
#define TX3912_INT2_ENABLE 0x011c
#define TX3912_INT3_ENABLE 0x0120
#define TX3912_INT4_ENABLE 0x0124
#define TX3912_INT5_ENABLE 0x0128
#define TX3912_INT6_ENABLE 0x012c
#define TX3912_INT1_STATUS 0x0100
#define TX3912_INT2_STATUS 0x0104
#define TX3912_INT3_STATUS 0x0108
#define TX3912_INT4_STATUS 0x010c
#define TX3912_INT5_STATUS 0x0110
#define TX3912_INT6_STATUS 0x0114
/*
* Interrupt 2 register values
*/
#define TX3912_INT2_UARTARXINT 0x80000000
#define TX3912_INT2_UARTARXOVERRUNINT 0x40000000
#define TX3912_INT2_UARTAFRAMEERRINT 0x20000000
#define TX3912_INT2_UARTABREAKINT 0x10000000
#define TX3912_INT2_UARTAPARITYINT 0x08000000
#define TX3912_INT2_UARTATXINT 0x04000000
#define TX3912_INT2_UARTATXOVERRUNINT 0x02000000
#define TX3912_INT2_UARTAEMPTYINT 0x01000000
#define TX3912_INT2_UARTADMAFULLINT 0x00800000
#define TX3912_INT2_UARTADMAHALFINT 0x00400000
#define TX3912_INT2_UARTBRXINT 0x00200000
#define TX3912_INT2_UARTBRXOVERRUNINT 0x00100000
#define TX3912_INT2_UARTBFRAMEERRINT 0x00080000
#define TX3912_INT2_UARTBBREAKINT 0x00040000
#define TX3912_INT2_UARTBPARITYINT 0x00020000
#define TX3912_INT2_UARTBTXINT 0x00010000
#define TX3912_INT2_UARTBTXOVERRUNINT 0x00008000
#define TX3912_INT2_UARTBEMPTYINT 0x00004000
#define TX3912_INT2_UARTBDMAFULLINT 0x00002000
#define TX3912_INT2_UARTBDMAHALFINT 0x00001000
#define TX3912_INT2_UARTA_RX_BITS 0xf8000000
#define TX3912_INT2_UARTA_TX_BITS 0x07c00000
#define TX3912_INT2_UARTB_RX_BITS 0x003e0000
#define TX3912_INT2_UARTB_TX_BITS 0x0001f000
/****************************************************************************** /*
* * Interrupt 5 register values
* 07 CHI module */
* #define TX3912_INT5_RTCINT 0x80000000
******************************************************************************/ #define TX3912_INT5_ALARMINT 0x40000000
#define TX3912_INT5_PERINT 0x20000000
#define CHIControl REG_AT(0x1D8) #define TX3912_INT5_STPTIMERINT 0x10000000
#define CHIPointerEnable REG_AT(0x1DC) #define TX3912_INT5_POSPWRINT 0x08000000
#define CHIReceivePtrA REG_AT(0x1E0) #define TX3912_INT5_NEGPWRINT 0x04000000
#define CHIReceivePtrB REG_AT(0x1E4) #define TX3912_INT5_POSPWROKINT 0x02000000
#define CHITransmitPtrA REG_AT(0x1E8) #define TX3912_INT5_NEGPWROKINT 0x01000000
#define CHITransmitPtrB REG_AT(0x1EC) #define TX3912_INT5_POSONBUTINT 0x00800000
#define CHISize REG_AT(0x1F0) #define TX3912_INT5_NEGONBUTINT 0x00400000
#define CHIReceiveStart REG_AT(0x1F4) #define TX3912_INT5_SPIBUFAVAILINT 0x00200000
#define CHITransmitStart REG_AT(0x1F8) #define TX3912_INT5_SPIERRINT 0x00100000
#define CHIHoldingReg REG_AT(0x1FC) #define TX3912_INT5_SPIRCVINT 0x00080000
#define TX3912_INT5_SPIEMPTYINT 0x00040000
/* CHI Control Register */ #define TX3912_INT5_IRCONSMINT 0x00020000
/* <incomplete!> */ #define TX3912_INT5_CARSTINT 0x00010000
#define CHI_RXEN BIT(2) #define TX3912_INT5_POSCARINT 0x00008000
#define CHI_TXEN BIT(1) #define TX3912_INT5_NEGCARINT 0x00004000
#define CHI_ENCHI BIT(0) #define TX3912_INT5_IOPOSINT6 0x00002000
#define TX3912_INT5_IOPOSINT5 0x00001000
/****************************************************************************** #define TX3912_INT5_IOPOSINT4 0x00000800
* #define TX3912_INT5_IOPOSINT3 0x00000400
* 08 Interrupt module #define TX3912_INT5_IOPOSINT2 0x00000200
* #define TX3912_INT5_IOPOSINT1 0x00000100
******************************************************************************/ #define TX3912_INT5_IOPOSINT0 0x00000080
#define TX3912_INT5_IONEGINT6 0x00000040
/* Register locations */ #define TX3912_INT5_IONEGINT5 0x00000020
#define TX3912_INT5_IONEGINT4 0x00000010
#define IntStatus1 REG_AT(0x100) #define TX3912_INT5_IONEGINT3 0x00000008
#define IntStatus2 REG_AT(0x104) #define TX3912_INT5_IONEGINT2 0x00000004
#define IntStatus3 REG_AT(0x108) #define TX3912_INT5_IONEGINT1 0x00000002
#define IntStatus4 REG_AT(0x10c) #define TX3912_INT5_IONEGINT0 0x00000001
#define IntStatus5 REG_AT(0x110)
#define IntStatus6 REG_AT(0x114)
#define IntClear1 REG_AT(0x100)
#define IntClear2 REG_AT(0x104)
#define IntClear3 REG_AT(0x108)
#define IntClear4 REG_AT(0x10c)
#define IntClear5 REG_AT(0x110)
#define IntClear6 REG_AT(0x114)
#define IntEnable1 REG_AT(0x118)
#define IntEnable2 REG_AT(0x11c)
#define IntEnable3 REG_AT(0x120)
#define IntEnable4 REG_AT(0x124)
#define IntEnable5 REG_AT(0x128)
#define IntEnable6 REG_AT(0x12c)
/* Interrupt Status Register 1 at offset 100 */
#define INT1_LCDINT BIT(31)
#define INT1_DFINT BIT(30)
#define INT1_CHIDMAHALF BIT(29)
#define INT1_CHIDMAFULL BIT(28)
#define INT1_CHIDMACNTINT BIT(27)
#define INT1_CHIRXAINT BIT(26)
#define INT1_CHIRXBINT BIT(25)
#define INT1_CHIACTINT BIT(24)
#define INT1_CHIERRINT BIT(23)
#define INT1_SND0_5INT BIT(22)
#define INT1_SND1_0INT BIT(21)
#define INT1_TEL0_5INT BIT(20)
#define INT1_TEL1_0INT BIT(19)
#define INT1_SNDDMACNTINT BIT(18)
#define INT1_TELDMACNTINT BIT(17)
#define INT1_LSNDCLIPINT BIT(16)
#define INT1_RSNDCLIPINT BIT(15)
#define INT1_VALSNDPOSINT BIT(14)
#define INT1_VALSNDNEGINT BIT(13)
#define INT1_VALTELPOSINT BIT(12)
#define INT1_VALTELNEGINT BIT(11)
#define INT1_SNDININT BIT(10)
#define INT1_TELININT BIT(9)
#define INT1_SIBSF0INT BIT(8)
#define INT1_SIBSF1INT BIT(7)
#define INT1_SIBIRQPOSINT BIT(6)
#define INT1_SIBIRQNEGINT BIT(5)
/* Interrupt Status Register 2 at offset 104 */
#define INT2_UARTARXINT BIT(31)
#define INT2_UARTARXOVERRUN BIT(30)
#define INT2_UARTAFRAMEINT BIT(29)
#define INT2_UARTABREAKINT BIT(28)
#define INT2_UARTATXINT BIT(26)
#define INT2_UARTATXOVERRUN BIT(25)
#define INT2_UARTAEMPTY BIT(24)
#define INT2_UARTBRXINT BIT(21)
#define INT2_UARTBRXOVERRUN BIT(20)
#define INT2_UARTBFRAMEINT BIT(29)
#define INT2_UARTBBREAKINT BIT(18)
#define INT2_UARTBTXINT BIT(16)
#define INT2_UARTBTXOVERRUN BIT(15)
#define INT2_UARTBEMPTY BIT(14)
#define INT2_UARTA_RX (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27))
#define INT2_UARTA_TX (BIT(26) | BIT(25) | BIT(24))
#define INT2_UARTA_DMA (BIT(23) | BIT(22))
#define INT2_UARTB_RX (BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17))
#define INT2_UARTB_TX (BIT(16) | BIT(15) | BIT(14))
#define INT2_UARTB_DMA (BIT(13) | BIT(12))
/* Interrupt Status Register 5 */
#define INT5_RTCINT BIT(31)
#define INT5_ALARMINT BIT(30)
#define INT5_PERIODICINT BIT(29)
#define INT5_POSPWRINT BIT(27)
#define INT5_NEGPWRINT BIT(26)
#define INT5_POSPWROKINT BIT(25)
#define INT5_NEGPWROKINT BIT(24)
#define INT5_POSONBUTINT BIT(23)
#define INT5_NEGONBUTINT BIT(22)
#define INT5_SPIAVAILINT BIT(21) /* 0x0020 0000 */
#define INT5_SPIERRINT BIT(20) /* 0x0010 0000 */
#define INT5_SPIRCVINT BIT(19) /* 0x0008 0000 */
#define INT5_SPIEMPTYINT BIT(18) /* 0x0004 0000 */
#define INT5_IOPOSINT6 BIT(13)
#define INT5_IOPOSINT5 BIT(12)
#define INT5_IOPOSINT4 BIT(11)
#define INT5_IOPOSINT3 BIT(10)
#define INT5_IOPOSINT2 BIT(9)
#define INT5_IOPOSINT1 BIT(8)
#define INT5_IOPOSINT0 BIT(7)
#define INT5_IONEGINT6 BIT(6)
#define INT5_IONEGINT5 BIT(5)
#define INT5_IONEGINT4 BIT(4)
#define INT5_IONEGINT3 BIT(3)
#define INT5_IONEGINT2 BIT(2)
#define INT5_IONEGINT1 BIT(1)
#define INT5_IONEGINT0 BIT(0)
#define INT5_IONEGINT_SHIFT 0
#define INT5_IONEGINT_MASK (0x7F<<INT5_IONEGINT_SHIFT)
#define INT5_IOPOSINT_SHIFT 7
#define INT5_IOPOSINT_MASK (0x7F<<INT5_IOPOSINT_SHIFT)
/* Interrupt Status Register 6 */
#define INT6_IRQHIGH BIT(31)
#define INT6_IRQLOW BIT(30)
#define INT6_INTVECT (BIT(5) | BIT(4) | BIT(3) | BIT(2))
/* Interrupt Enable Register 6 */
#define INT6_GLOBALEN BIT(18)
#define INT6_PWROKINT BIT(15)
#define INT6_ALARMINT BIT(14)
#define INT6_PERIODICINT BIT(13)
#define INT6_MBUSINT BIT(12)
#define INT6_UARTARXINT BIT(11)
#define INT6_UARTBRXINT BIT(10)
#define INT6_MFIOPOSINT1619 BIT(9)
#define INT6_IOPOSINT56 BIT(8)
#define INT6_MFIONEGINT1619 BIT(7)
#define INT6_IONEGINT56 BIT(6)
#define INT6_MBUSDMAFULLINT BIT(5)
#define INT6_SNDDMACNTINT BIT(4)
#define INT6_TELDMACNTINT BIT(3)
#define INT6_CHIDMACNTINT BIT(2)
#define INT6_IOPOSNEGINT0 BIT(1)
/******************************************************************************
*
* 09 GPIO and MFIO modules
*
******************************************************************************/
#define IOControl REG_AT(0x180)
#define MFIOOutput REG_AT(0x184)
#define MFIODirection REG_AT(0x188)
#define MFIOInput REG_AT(0x18c)
#define MFIOSelect REG_AT(0x190)
#define IOPowerDown REG_AT(0x194)
#define MFIOPowerDown REG_AT(0x198)
#define IODIN_MASK 0x0000007f
#define IODIN_SHIFT 0
#define IODOUT_MASK 0x00007f00
#define IODOUT_SHIFT 8
#define IODIREC_MASK 0x007f0000
#define IODIREC_SHIFT 16
#define IODEBSEL_MASK 0x7f000000
#define IODEBSEL_SHIFT 24
/******************************************************************************
*
* 10 IR module
*
******************************************************************************/
#define IRControl1 REG_AT(0x0a0)
#define IRControl2 REG_AT(0x0a4)
/* IR Control 1 Register */
#define IR_CARDRET BIT(24)
#define IR_BAUDVAL_MASK 0x00ff0000
#define IR_BAUDVAL_SHIFT 16
#define IR_TESTIR BIT(4)
#define IR_DTINVERT BIT(3)
#define IR_RXPWR BIT(2)
#define IR_ENSTATE BIT(1)
#define IR_ENCONSM BIT(0)
/* IR Control 2 Register */
#define IR_PER_MASK 0xff000000
#define IR_PER_SHIFT 24
#define IR_ONTIME_MASK 0x00ff0000
#define IR_ONTIME_SHIFT 16
#define IR_DELAYVAL_MASK 0x0000ff00
#define IR_DELAYVAL_SHIFT 8
#define IR_WAITVAL_MASK 0x000000ff
#define IR_WAITVAL_SHIFT 0
/******************************************************************************
*
* 11 Magicbus Module
*
******************************************************************************/
#define MbusCntrl1 REG_AT(0x0e0)
#define MbusCntrl2 REG_AT(0x0e4)
#define MbusDMACntrl1 REG_AT(0x0e8)
#define MbusDMACntrl2 REG_AT(0x0ec)
#define MbusDMACount REG_AT(0x0f0)
#define MbusTxReg REG_AT(0x0f4)
#define MbusRxReg REG_AT(0x0f8)
#define MBUS_CLKPOL BIT(4)
#define MBUS_SLAVE BIT(3)
#define MBUS_FSLAVE BIT(2)
#define MBUS_LONG BIT(1)
#define MBUS_ENMBUS BIT(0)
/******************************************************************************
*
* 12 Power module
*
******************************************************************************/
#define PowerControl REG_AT(0x1C4)
#define PWR_ONBUTN BIT(31)
#define PWR_PWRINT BIT(30)
#define PWR_PWROK BIT(29)
#define PWR_VIDRF_MASK (BIT(28) | BIT(27))
#define PWR_VIDRF_SHIFT 27
#define PWR_SLOWBUS BIT(26)
#define PWR_DIVMOD BIT(25)
#define PWR_STPTIMERVAL_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
#define PWR_STPTIMERVAL_SHIFT 12
#define PWR_ENSTPTIMER BIT(11)
#define PWR_ENFORCESHUTDWN BIT(10)
#define PWR_FORCESHUTDWN BIT(9)
#define PWR_FORCESHUTDWNOCC BIT(8)
#define PWR_SELC2MS BIT(7)
#define PWR_BPDBVCC3 BIT(5)
#define PWR_STOPCPU BIT(4)
#define PWR_DBNCONBUTN BIT(3)
#define PWR_COLDSTART BIT(2)
#define PWR_PWRCS BIT(1)
#define PWR_VCCON BIT(0)
/******************************************************************************
*
* 13 SIB (Serial Interconnect Bus) Module
*
******************************************************************************/
/* Register locations */
#define SIBSize REG_AT(0x060)
#define SIBSoundRXStart REG_AT(0x064)
#define SIBSoundTXStart REG_AT(0x068)
#define SIBTelecomRXStart REG_AT(0x06C)
#define SIBTelecomTXStart REG_AT(0x070)
#define SIBControl REG_AT(0x074)
#define SIBSoundTXRXHolding REG_AT(0x078)
#define SIBTelecomTXRXHolding REG_AT(0x07C)
#define SIBSubFrame0Control REG_AT(0x080)
#define SIBSubFrame1Control REG_AT(0x084)
#define SIBSubFrame0Status REG_AT(0x088)
#define SIBSubFrame1Status REG_AT(0x08C)
#define SIBDMAControl REG_AT(0x090)
/* SIB Size Register */
#define SIB_SNDSIZE_MASK 0x3ffc0000
#define SIB_SNDSIZE_SHIFT 18
#define SIB_TELSIZE_MASK 0x00003ffc
#define SIB_TELSIZE_SHIFT 2
/* SIB Control Register */
#define SIB_SIBIRQ BIT(31)
#define SIB_ENCNTTEST BIT(30)
#define SIB_ENDMATEST BIT(29)
#define SIB_SNDMONO BIT(28)
#define SIB_RMONOSNDIN BIT(27)
#define SIB_SIBSCLKDIV_MASK (BIT(26) | BIT(25) | BIT(24))
#define SIB_SIBSCLKDIV_SHIFT 24
#define SIB_TEL16 BIT(23)
#define SIB_TELFSDIV_MASK 0x007f0000
#define SIB_TELFSDIV_SHIFT 16
#define SIB_SND16 BIT(15)
#define SIB_SNDFSDIV_MASK 0x00007f00
#define SIB_SNDFSDIV_SHIFT 8
#define SIB_SELTELSF1 BIT(7)
#define SIB_SELSNDSF1 BIT(6)
#define SIB_ENTEL BIT(5)
#define SIB_ENSND BIT(4)
#define SIB_SIBLOOP BIT(3)
#define SIB_ENSF1 BIT(2)
#define SIB_ENSF0 BIT(1)
#define SIB_ENSIB BIT(0)
/* SIB Frame Format (SIBSubFrame0Status and SIBSubFrame1Status) */
#define SIB_REGISTER_EXT BIT(31) /* Must be zero */
#define SIB_ADDRESS_MASK 0x78000000
#define SIB_ADDRESS_SHIFT 27
#define SIB_WRITE BIT(26)
#define SIB_AUD_VALID BIT(17)
#define SIB_TEL_VALID BIT(16)
#define SIB_DATA_MASK 0x00ff
#define SIB_DATA_SHIFT 0
/* SIB DMA Control Register */
#define SIB_SNDBUFF1TIME BIT(31)
#define SIB_SNDDMALOOP BIT(30)
#define SIB_SNDDMAPTR_MASK 0x3ffc0000
#define SIB_SNDDMAPTR_SHIFT 18
#define SIB_ENDMARXSND BIT(17)
#define SIB_ENDMATXSND BIT(16)
#define SIB_TELBUFF1TIME BIT(15)
#define SIB_TELDMALOOP BIT(14)
#define SIB_TELDMAPTR_MASK 0x00003ffc
#define SIB_TELDMAPTR_SHIFT 2
#define SIB_ENDMARXTEL BIT(1)
#define SIB_ENDMATXTEL BIT(0)
/******************************************************************************
*
* 14 SPI module
*
******************************************************************************/
#define SPIControl REG_AT(0x160)
#define SPITransmit REG_AT(0x164)
#define SPIReceive REG_AT(0x164)
#define SPI_SPION BIT(17)
#define SPI_EMPTY BIT(16)
#define SPI_DELAYVAL_MASK (BIT(12) | BIT(13) | BIT(14) | BIT(15))
#define SPI_DELAYVAL_SHIFT 12
#define SPI_BAUDRATE_MASK (BIT(8) | BIT(9) | BIT(10) | BIT(11))
#define SPI_BAUDRATE_SHIFT 8
#define SPI_PHAPOL BIT(5)
#define SPI_CLKPOL BIT(4)
#define SPI_WORD BIT(2)
#define SPI_LSB BIT(1)
#define SPI_ENSPI BIT(0)
/******************************************************************************
*
* 15 Timer module
*
******************************************************************************/
#define RTChigh REG_AT(0x140)
#define RTClow REG_AT(0x144)
#define RTCalarmHigh REG_AT(0x148)
#define RTCalarmLow REG_AT(0x14c)
#define RTCtimerControl REG_AT(0x150)
#define RTCperiodTimer REG_AT(0x154)
/* RTC Timer Control */
#define TIM_FREEZEPRE BIT(7)
#define TIM_FREEZERTC BIT(6)
#define TIM_FREEZETIMER BIT(5)
#define TIM_ENPERTIMER BIT(4)
#define TIM_RTCCLEAR BIT(3)
#define RTC_HIGHMASK (0xFF)
/* RTC Periodic Timer */ /*
#define TIM_PERCNT 0xFFFF0000 * Interrupt 6 status register values
#define TIM_PERVAL 0x0000FFFF */
#define TX3912_INT6_STATUS_IRQHIGH 0x80000000
#define TX3912_INT6_STATUS_IRQLOW 0x40000000
#define TX3912_INT6_STATUS_reserved6 0x3fffffc0
#define TX3912_INT6_STATUS_INTVEC_POSNEGPWROKINT 0x0000003c
#define TX3912_INT6_STATUS_INTVEC_ALARMINT 0x00000038
#define TX3912_INT6_STATUS_INTVEC_PERINT 0x00000034
#define TX3912_INT6_STATUS_INTVEC_reserved5 0x00000030
#define TX3912_INT6_STATUS_INTVEC_UARTARXINT 0x0000002c
#define TX3912_INT6_STATUS_INTVEC_UARTBRXINT 0x00000028
#define TX3912_INT6_STATUS_INTVEC_reserved4 0x00000024
#define TX3912_INT6_STATUS_INTVEC_IOPOSINT65 0x00000020
#define TX3912_INT6_STATUS_INTVEC_reserved3 0x0000001c
#define TX3912_INT6_STATUS_INTVEC_IONEGINT65 0x00000018
#define TX3912_INT6_STATUS_INTVEC_reserved2 0x00000014
#define TX3912_INT6_STATUS_INTVEC_SNDDMACNTINT 0x00000010
#define TX3912_INT6_STATUS_INTVEC_TELDMACNTINT 0x0000000c
#define TX3912_INT6_STATUS_INTVEC_CHIDMACNTINT 0x00000008
#define TX3912_INT6_STATUS_INTVEC_IOPOSNEGINT0 0x00000004
#define TX3912_INT6_STATUS_INTVEC_STDHANDLER 0x00000000
#define TX3912_INT6_STATUS_reserved1 0x00000003
/* For a system clock frequency of 36.864MHz, the timer counts at one tick /*
every 868nS (ie CLK/32). Therefore 11520 counts gives a 10mS interval * Interrupt 6 enable register values
*/ */
#define PER_TIMER_COUNT (1152000/HZ) #define TX3912_INT6_ENABLE_reserved5 0xfff80000
#define TX3912_INT6_ENABLE_GLOBALEN 0x00040000
#define TX3912_INT6_ENABLE_IRQPRITEST 0x00020000
#define TX3912_INT6_ENABLE_IRQTEST 0x00010000
#define TX3912_INT6_ENABLE_PRIORITYMASK_POSNEGPWROKINT 0x00008000
#define TX3912_INT6_ENABLE_PRIORITYMASK_ALARMINT 0x00004000
#define TX3912_INT6_ENABLE_PRIORITYMASK_PERINT 0x00002000
#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved4 0x00001000
#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTARXINT 0x00000800
#define TX3912_INT6_ENABLE_PRIORITYMASK_UARTBRXINT 0x00000400
#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved3 0x00000200
#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSINT65 0x00000100
#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved2 0x00000080
#define TX3912_INT6_ENABLE_PRIORITYMASK_IONEGINT65 0x00000040
#define TX3912_INT6_ENABLE_PRIORITYMASK_reserved1 0x00000020
#define TX3912_INT6_ENABLE_PRIORITYMASK_SNDDMACNTINT 0x00000010
#define TX3912_INT6_ENABLE_PRIORITYMASK_TELDMACNTINT 0x00000008
#define TX3912_INT6_ENABLE_PRIORITYMASK_CHIDMACNTINT 0x00000004
#define TX3912_INT6_ENABLE_PRIORITYMASK_IOPOSNEGINT0 0x00000002
#define TX3912_INT6_ENABLE_PRIORITYMASK_STDHANDLER 0x00000001
#define TX3912_INT6_ENABLE_HIGH_PRIORITY 0x0000ffff
/*****************************************************************************
* Power Subsystem *
* --------------- *
* Chapter 11 in Philips PR31700 User Manual *
* Chapter 12 in Toshiba TMPR3905/12 User Manual *
*****************************************************************************/
#define TX3912_POWER_CTRL 0x01c4
/* /*
*********************************************************************** * Power control register values
* *
* 15 UART Module *
* *
***********************************************************************
*/ */
#define TX3912_UARTA_BASE (REGISTER_BASE + 0x0b0) #define TX3912_POWER_CTRL_ONBUTN 0x80000000
#define TX3912_UARTB_BASE (REGISTER_BASE + 0x0c8) #define TX3912_POWER_CTRL_PWRINT 0x40000000
#define TX3912_POWER_CTRL_PWROK 0x20000000
#define TX3912_POWER_CTRL_VIDRF_MASK 0x18000000
#define TX3912_POWER_CTRL_SLOWBUS 0x04000000
#define TX3912_POWER_CTRL_DIVMOD 0x02000000
#define TX3912_POWER_CTRL_reserved2 0x01ff0000
#define TX3912_POWER_CTRL_STPTIMERVAL_MASK 0x0000f000
#define TX3912_POWER_CTRL_ENSTPTIMER 0x00000800
#define TX3912_POWER_CTRL_ENFORCESHUTDWN 0x00000400
#define TX3912_POWER_CTRL_FORCESHUTDWN 0x00000200
#define TX3912_POWER_CTRL_FORCESHUTDWNOCC 0x00000100
#define TX3912_POWER_CTRL_SELC2MS 0x00000080
#define TX3912_POWER_CTRL_reserved1 0x00000040
#define TX3912_POWER_CTRL_BPDBVCC3 0x00000020
#define TX3912_POWER_CTRL_STOPCPU 0x00000010
#define TX3912_POWER_CTRL_DBNCONBUTN 0x00000008
#define TX3912_POWER_CTRL_COLDSTART 0x00000004
#define TX3912_POWER_CTRL_PWRCS 0x00000002
#define TX3912_POWER_CTRL_VCCON 0x00000001
/*****************************************************************************
* Timer Subsystem *
* --------------- *
* Chapter 14 in Philips PR31700 User Manual *
* Chapter 15 in Toshiba TMPR3905/12 User Manual *
*****************************************************************************/
#define TX3912_RTC_HIGH 0x0140
#define TX3912_RTC_LOW 0x0144
#define TX3912_RTC_ALARM_HIGH 0x0148
#define TX3912_RTC_ALARM_LOW 0x014c
#define TX3912_TIMER_CTRL 0x0150
#define TX3912_TIMER_PERIOD 0x0154
/* /*
* TX3912 UART register offsets * Timer control register values
*/ */
#define TX3912_UART_CTRL1 0x00 #define TX3912_TIMER_CTRL_FREEZEPRE 0x00000080
#define TX3912_UART_CTRL2 0x04 #define TX3912_TIMER_CTRL_FREEZERTC 0x00000040
#define TX3912_UART_DMA_CTRL1 0x08 #define TX3912_TIMER_CTRL_FREEZETIMER 0x00000020
#define TX3912_UART_DMA_CTRL2 0x0c #define TX3912_TIMER_CTRL_ENPERTIMER 0x00000010
#define TX3912_UART_DMA_CNT 0x10 #define TX3912_TIMER_CTRL_RTCCLEAR 0x00000008
#define TX3912_UART_DATA 0x14 #define TX3912_TIMER_CTRL_TESTC8MS 0x00000004
#define TX3912_TIMER_CTRL_ENTESTCLK 0x00000002
#define TX3912_TIMER_CTRL_ENRTCTST 0x00000001
#define UartA_Ctrl1 REG_AT(0x0b0) /*
#define UartA_Data REG_AT(0x0c4) * The periodic timer has granularity of 868 nanoseconds which
* results in a count of (1.152 x 10^6 / 100) in order to achieve
* a 10 millisecond periodic system clock.
*/
#define TX3912_SYS_TIMER_VALUE (1152000/HZ)
/*****************************************************************************
* UART Subsystem *
* -------------- *
* Chapter 15 in Philips PR31700 User Manual *
* Chapter 16 in Toshiba TMPR3905/12 User Manual *
*****************************************************************************/
#define TX3912_UARTA_CTRL1 0x00b0
#define TX3912_UARTA_CTRL2 0x00b4
#define TX3912_UARTA_DMA_CTRL1 0x00b8
#define TX3912_UARTA_DMA_CTRL2 0x00bc
#define TX3912_UARTA_DMA_CNT 0x00c0
#define TX3912_UARTA_DATA 0x00c4
#define TX3912_UARTB_CTRL1 0x00c8
#define TX3912_UARTB_CTRL2 0x00cc
#define TX3912_UARTB_DMA_CTRL1 0x00d0
#define TX3912_UARTB_DMA_CTRL2 0x00d4
#define TX3912_UARTB_DMA_CNT 0x00d8
#define TX3912_UARTB_DATA 0x00dc
/* /*
* Defines for UART Control Register 1 * UART Control Register 1 values
*/ */
#define TX3912_UART_CTRL1_UARTON 0x80000000 #define TX3912_UART_CTRL1_UARTON 0x80000000
#define UART_TX_EMPTY BIT(30) #define TX3912_UART_CTRL1_EMPTY 0x40000000
#define UART_PRX_HOLD_FULL BIT(29) #define TX3912_UART_CTRL1_PRXHOLDFULL 0x20000000
#define UART_RX_HOLD_FULL BIT(28) #define TX3912_UART_CTRL1_RXHOLDFULL 0x10000000
#define UART_EN_DMA_RX BIT(15) #define TX3912_UART_CTRL1_reserved1 0x0fff0000
#define UART_EN_DMA_TX BIT(14) #define TX3912_UART_CTRL1_ENDMARX 0x00008000
#define UART_BREAK_HALT BIT(12) #define TX3912_UART_CTRL1_ENDMATX 0x00004000
#define UART_DMA_LOOP BIT(10) #define TX3912_UART_CTRL1_TESTMODE 0x00002000
#define UART_PULSE_THREE BIT(9) #define TX3912_UART_CTRL1_ENBREAKHALT 0x00001000
#define UART_PULSE_SIX BIT(8) #define TX3912_UART_CTRL1_ENDMATEST 0x00000800
#define UART_DT_INVERT BIT(7) #define TX3912_UART_CTRL1_ENDMALOOP 0x00000400
#define UART_DIS_TXD BIT(6) #define TX3912_UART_CTRL1_PULSEOPT1 0x00000200
#define UART_LOOPBACK BIT(4) #define TX3912_UART_CTRL1_PULSEOPT1 0x00000100
#define TX3912_UART_CTRL1_DTINVERT 0x00000080
#define TX3912_UART_CTRL1_DISTXD 0x00000040
#define TX3912_UART_CTRL1_TWOSTOP 0x00000020
#define TX3912_UART_CTRL1_LOOPBACK 0x00000010
#define TX3912_UART_CTRL1_BIT_7 0x00000008
#define TX3912_UART_CTRL1_EVENPARITY 0x00000004
#define TX3912_UART_CTRL1_ENPARITY 0x00000002
#define TX3912_UART_CTRL1_ENUART 0x00000001 #define TX3912_UART_CTRL1_ENUART 0x00000001
#define SER_SEVEN_BIT BIT(3)
#define SER_EIGHT_BIT 0
#define SER_EVEN_PARITY (BIT(2) | BIT(1))
#define SER_ODD_PARITY BIT(1)
#define SER_NO_PARITY 0
#define SER_TWO_STOP BIT(5)
#define SER_ONE_STOP 0
/* /*
* Defines for UART Control Register 2 * UART Control Register 2 values
*
* 3.6864MHz
* divisors = ----------- - 1
* (baud * 16)
*/ */
#define TX3912_UART_CTRL2_B230400 0x000 /* 0 */ #define TX3912_UART_CTRL2_B230400 0x0000 /* 0 */
#define TX3912_UART_CTRL2_B115200 0x001 /* 1 */ #define TX3912_UART_CTRL2_B115200 0x0001 /* 1 */
#define TX3912_UART_CTRL2_B76800 0x002 /* 2 */ #define TX3912_UART_CTRL2_B76800 0x0002 /* 2 */
#define TX3912_UART_CTRL2_B57600 0x003 /* 3 */ #define TX3912_UART_CTRL2_B57600 0x0003 /* 3 */
#define TX3912_UART_CTRL2_B38400 0x005 /* 5 */ #define TX3912_UART_CTRL2_B38400 0x0005 /* 5 */
#define TX3912_UART_CTRL2_B19200 0x00b /* 11 */ #define TX3912_UART_CTRL2_B19200 0x000b /* 11 */
#define TX3912_UART_CTRL2_B9600 0x016 /* 22 */ #define TX3912_UART_CTRL2_B9600 0x0016 /* 22 */
#define TX3912_UART_CTRL2_B4800 0x02f /* 47 */ #define TX3912_UART_CTRL2_B4800 0x002f /* 47 */
#define TX3912_UART_CTRL2_B2400 0x05f /* 95 */ #define TX3912_UART_CTRL2_B2400 0x005f /* 95 */
#define TX3912_UART_CTRL2_B1200 0x0bf /* 191 */ #define TX3912_UART_CTRL2_B1200 0x00bf /* 191 */
#define TX3912_UART_CTRL2_B600 0x17f /* 383 */ #define TX3912_UART_CTRL2_B600 0x017f /* 383 */
#define TX3912_UART_CTRL2_B300 0x2ff /* 767 */ #define TX3912_UART_CTRL2_B300 0x02ff /* 767 */
/*****************************************************************************
* Video Subsystem *
* --------------- *
* Chapter 16 in Philips PR31700 User Manual *
* Chapter 17 in Toshiba TMPR3905/12 User Manual *
*****************************************************************************/
#define TX3912_VIDEO_CTRL1 0x0028
#define TX3912_VIDEO_CTRL2 0x002c
#define TX3912_VIDEO_CTRL3 0x0030
#define TX3912_VIDEO_CTRL4 0x0034
#define TX3912_VIDEO_CTRL5 0x0038
#define TX3912_VIDEO_CTRL6 0x003c
#define TX3912_VIDEO_CTRL7 0x0040
#define TX3912_VIDEO_CTRL8 0x0044
#define TX3912_VIDEO_CTRL9 0x0048
#define TX3912_VIDEO_CTRL10 0x004c
#define TX3912_VIDEO_CTRL11 0x0050
#define TX3912_VIDEO_CTRL12 0x0054
#define TX3912_VIDEO_CTRL13 0x0058
#define TX3912_VIDEO_CTRL14 0x005c
#endif /* __TX3912_H__ */ /*
* Video Control Register 1 values
*/
#define TX3912_VIDEO_CTRL1_LINECNT 0xffc00000
#define TX3912_VIDEO_CTRL1_LOADDLY 0x00200000
#define TX3912_VIDEO_CTRL1_BAUDVAL 0x001f0000
#define TX3912_VIDEO_CTRL1_VIDDONEVAL 0x0000fe00
#define TX3912_VIDEO_CTRL1_ENFREEZEFRAME 0x00000100
#define TX3912_VIDEO_CTRL1_BITSEL_MASK 0x000000c0
#define TX3912_VIDEO_CTRL1_BITSEL_8BIT_COLOR 0x000000c0
#define TX3912_VIDEO_CTRL1_BITSEL_4BIT_GRAY 0x00000080
#define TX3912_VIDEO_CTRL1_BITSEL_2BIT_GRAY 0x00000040
#define TX3912_VIDEO_CTRL1_DISPSPLIT 0x00000020
#define TX3912_VIDEO_CTRL1_DISP8 0x00000010
#define TX3912_VIDEO_CTRL1_DFMODE 0x00000008
#define TX3912_VIDEO_CTRL1_INVVID 0x00000004
#define TX3912_VIDEO_CTRL1_DISPON 0x00000002
#define TX3912_VIDEO_CTRL1_ENVID 0x00000001
#endif /* _TX3912_H_ */
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