Commit eb40c469 authored by Paul Mundt's avatar Paul Mundt Committed by Stephen Lord

[PATCH] shwdt update

This patch includes quite a few changes and updates for the shwdt driver (which
brings it in sync with LinuxSH CVS HEAD). This fixes up support for the SH-2,
and also fixes up some timer brain-damage.
parent 9889cc77
......@@ -3,7 +3,7 @@
*
* Watchdog driver for integrated watchdog in the SuperH processors.
*
* Copyright (C) 2001, 2002 Paul Mundt <lethal@0xd6.org>
* Copyright (C) 2001, 2002, 2003 Paul Mundt <lethal@linux-sh.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -12,6 +12,10 @@
*
* 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
*
* 19-Apr-2002 Rob Radez <rob@osinvestor.com>
* Added expect close support, made emulated timeout runtime changeable
* general cleanups, add some ioctls
*/
#include <linux/config.h>
#include <linux/module.h>
......@@ -22,76 +26,50 @@
#include <linux/reboot.h>
#include <linux/notifier.h>
#include <linux/ioport.h>
#include <linux/fs.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#if defined(CONFIG_CPU_SH5)
#define WTCNT CPRC_BASE + 0x10
#define WTCSR CPRC_BASE + 0x18
#elif defined(CONFIG_CPU_SH4)
#define WTCNT 0xffc00008
#define WTCSR 0xffc0000c
#elif defined(CONFIG_CPU_SH3)
#define WTCNT 0xffffff84
#define WTCSR 0xffffff86
#else
#error "Can't use SuperH watchdog on this platform"
#endif
#define WTCNT_HIGH 0x5a00
#define WTCSR_HIGH 0xa500
#define WTCSR_TME 0x80
#define WTCSR_WT 0x40
#define WTCSR_RSTS 0x20
#define WTCSR_WOVF 0x10
#define WTCSR_IOVF 0x08
#define WTCSR_CKS2 0x04
#define WTCSR_CKS1 0x02
#define WTCSR_CKS0 0x01
#include <asm/watchdog.h>
/*
* CKS0-2 supports a number of clock division ratios. At the time the watchdog
* is enabled, it defaults to a 41 usec overflow period .. we overload this to
* something a little more reasonable, and really can't deal with anything
* lower than WTCSR_CKS_1024, else we drop back into the usec range.
* Default clock division ratio is 5.25 msecs. For an additional table of
* values, consult the asm-sh/watchdog.h. Overload this at module load
* time.
*
* Clock Division Ratio Overflow Period
* --------------------------------------------
* 1/32 (initial value) 41 usecs
* 1/64 82 usecs
* 1/128 164 usecs
* 1/256 328 usecs
* 1/512 656 usecs
* 1/1024 1.31 msecs
* 1/2048 2.62 msecs
* 1/4096 5.25 msecs
*/
#define WTCSR_CKS_32 0x00
#define WTCSR_CKS_64 0x01
#define WTCSR_CKS_128 0x02
#define WTCSR_CKS_256 0x03
#define WTCSR_CKS_512 0x04
#define WTCSR_CKS_1024 0x05
#define WTCSR_CKS_2048 0x06
#define WTCSR_CKS_4096 0x07
/*
* Default clock division ratio is 5.25 msecs. Overload this at module load
* time. Any value not in the msec range will default to a timeout of one
* jiffy, which exceeds the usec overflow periods.
* In order for this to work reliably we need to have HZ set to 1000 or
* something quite higher than 100 (or we need a proper high-res timer
* implementation that will deal with this properly), otherwise the 10ms
* resolution of a jiffy is enough to trigger the overflow. For things like
* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
* necssary.
*
* As a result of this timing problem, the only modes that are particularly
* feasible are the 4096 and the 2048 divisors, which yeild 5.25 and 2.62ms
* overflow periods respectively.
*
* Also, since we can't really expect userspace to be responsive enough
* before the overflow happens, we maintain two seperate timers .. One in
* the kernel for clearing out WOVF every 2ms or so (again, this depends on
* HZ == 1000), and another for monitoring userspace writes to the WDT device.
*
* As such, we currently use a configurable heartbeat interval which defaults
* to 30s. In this case, the userspace daemon is only responsible for periodic
* writes to the device before the next heartbeat is scheduled. If the daemon
* misses its deadline, the kernel timer will allow the WDT to overflow.
*/
static int clock_division_ratio = WTCSR_CKS_4096;
#define msecs_to_jiffies(msecs) (jiffies + ((HZ * msecs + 999) / 1000))
#define msecs_to_jiffies(msecs) (jiffies + (HZ * msecs + 9999) / 10000)
#define next_ping_period(cks) msecs_to_jiffies(cks - 4)
#define user_ping_period(cks) (next_ping_period(cks) * 10)
static unsigned long sh_is_open = 0;
static unsigned long shwdt_is_open;
static struct watchdog_info sh_wdt_info;
static char shwdt_expect_close;
static struct timer_list timer;
static unsigned long next_heartbeat;
static int heartbeat = 30;
#ifdef CONFIG_WATCHDOG_NOWAYOUT
static int nowayout = 1;
......@@ -99,35 +77,6 @@ static int nowayout = 1;
static int nowayout = 0;
#endif
MODULE_PARM(nowayout,"i");
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
/**
* sh_wdt_write_cnt - Write to Counter
*
* @val: Value to write
*
* Writes the given value @val to the lower byte of the timer counter.
* The upper byte is set manually on each write.
*/
static void sh_wdt_write_cnt(__u8 val)
{
ctrl_outw(WTCNT_HIGH | (__u16)val, WTCNT);
}
/**
* sh_wdt_write_csr - Write to Control/Status Register
*
* @val: Value to write
*
* Writes the given value @val to the lower byte of the control/status
* register. The upper byte is set manually on each write.
*/
static void sh_wdt_write_csr(__u8 val)
{
ctrl_outw(WTCSR_HIGH | (__u16)val, WTCSR);
}
/**
* sh_wdt_start - Start the Watchdog
*
......@@ -135,13 +84,44 @@ static void sh_wdt_write_csr(__u8 val)
*/
static void sh_wdt_start(void)
{
timer.expires = next_ping_period(clock_division_ratio);
next_heartbeat = user_ping_period(clock_division_ratio);
add_timer(&timer);
__u8 csr;
mod_timer(&timer, next_ping_period(clock_division_ratio));
next_heartbeat = jiffies + (heartbeat * HZ);
csr = sh_wdt_read_csr();
csr |= WTCSR_WT | clock_division_ratio;
sh_wdt_write_csr(csr);
sh_wdt_write_csr(WTCSR_WT | WTCSR_CKS_4096);
sh_wdt_write_cnt(0);
sh_wdt_write_csr((ctrl_inb(WTCSR) | WTCSR_TME));
/*
* These processors have a bit of an inconsistent initialization
* process.. starting with SH-3, RSTS was moved to WTCSR, and the
* RSTCSR register was removed.
*
* On the SH-2 however, in addition with bits being in different
* locations, we must deal with RSTCSR outright..
*/
csr = sh_wdt_read_csr();
csr |= WTCSR_TME;
csr &= ~WTCSR_RSTS;
sh_wdt_write_csr(csr);
#ifdef CONFIG_CPU_SH2
/*
* Whoever came up with the RSTCSR semantics must've been smoking
* some of the good stuff, since in addition to the WTCSR/WTCNT write
* brain-damage, it's managed to fuck things up one step further..
*
* If we need to clear the WOVF bit, the upper byte has to be 0xa5..
* but if we want to touch RSTE or RSTS, the upper byte has to be
* 0x5a..
*/
csr = sh_wdt_read_rstcsr();
csr &= ~RSTCSR_RSTS;
sh_wdt_write_rstcsr(csr);
#endif
}
/**
......@@ -151,9 +131,13 @@ static void sh_wdt_start(void)
*/
static void sh_wdt_stop(void)
{
__u8 csr;
del_timer(&timer);
sh_wdt_write_csr((ctrl_inb(WTCSR) & ~WTCSR_TME));
csr = sh_wdt_read_csr();
csr &= ~WTCSR_TME;
sh_wdt_write_csr(csr);
}
/**
......@@ -166,11 +150,15 @@ static void sh_wdt_stop(void)
static void sh_wdt_ping(unsigned long data)
{
if (time_before(jiffies, next_heartbeat)) {
sh_wdt_write_csr((ctrl_inb(WTCSR) & ~WTCSR_IOVF));
__u8 csr;
csr = sh_wdt_read_csr();
csr &= ~WTCSR_IOVF;
sh_wdt_write_csr(csr);
sh_wdt_write_cnt(0);
timer.expires = next_ping_period(clock_division_ratio);
add_timer(&timer);
mod_timer(&timer, next_ping_period(clock_division_ratio));
}
}
......@@ -184,22 +172,13 @@ static void sh_wdt_ping(unsigned long data)
*/
static int sh_wdt_open(struct inode *inode, struct file *file)
{
switch (minor(inode->i_rdev)) {
case WATCHDOG_MINOR:
if (test_and_set_bit(0, &sh_is_open))
if (test_and_set_bit(0, &shwdt_is_open))
return -EBUSY;
if (nowayout) {
if (nowayout)
MOD_INC_USE_COUNT;
}
sh_wdt_start();
break;
default:
return -ENODEV;
}
return 0;
}
......@@ -213,30 +192,17 @@ static int sh_wdt_open(struct inode *inode, struct file *file)
*/
static int sh_wdt_close(struct inode *inode, struct file *file)
{
if (minor(inode->i_rdev) == WATCHDOG_MINOR) {
if (!nowayout) {
if (!nowayout && shwdt_expect_close == 42) {
sh_wdt_stop();
}
clear_bit(0, &sh_is_open);
} else {
printk(KERN_CRIT "shwdt: Unexpected close, not stopping watchdog!\n");
next_heartbeat = jiffies + (heartbeat * HZ);
}
return 0;
}
clear_bit(0, &shwdt_is_open);
shwdt_expect_close = 0;
/**
* sh_wdt_read - Read from Device
*
* @file: file handle of device
* @buf: buffer to write to
* @count: length of buffer
* @ppos: offset
*
* Unsupported.
*/
static ssize_t sh_wdt_read(struct file *file, char *buf,
size_t count, loff_t *ppos)
{
return -EINVAL;
return 0;
}
/**
......@@ -257,11 +223,21 @@ static ssize_t sh_wdt_write(struct file *file, const char *buf,
return -ESPIPE;
if (count) {
next_heartbeat = user_ping_period(clock_division_ratio);
return 1;
size_t i;
shwdt_expect_close = 0;
for (i = 0; i != count; i++) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
if (c == 'V')
shwdt_expect_close = 42;
}
next_heartbeat = jiffies + (heartbeat * HZ);
}
return 0;
return count;
}
/**
......@@ -278,6 +254,8 @@ static ssize_t sh_wdt_write(struct file *file, const char *buf,
static int sh_wdt_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
int new_timeout;
switch (cmd) {
case WDIOC_GETSUPPORT:
if (copy_to_user((struct watchdog_info *)arg,
......@@ -288,17 +266,41 @@ static int sh_wdt_ioctl(struct inode *inode, struct file *file,
break;
case WDIOC_GETSTATUS:
if (copy_to_user((int *)arg,
&sh_is_open,
sizeof(int))) {
case WDIOC_GETBOOTSTATUS:
return put_user(0, (int *)arg);
case WDIOC_KEEPALIVE:
next_heartbeat = jiffies + (heartbeat * HZ);
break;
case WDIOC_SETTIMEOUT:
if (get_user(new_timeout, (int *)arg))
return -EFAULT;
if (new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */
return -EINVAL;
heartbeat = new_timeout;
next_heartbeat = jiffies + (heartbeat * HZ);
/* Fall */
case WDIOC_GETTIMEOUT:
return put_user(heartbeat, (int *)arg);
case WDIOC_SETOPTIONS:
{
int options, retval = -EINVAL;
if (get_user(options, (int *)arg))
return -EFAULT;
if (options & WDIOS_DISABLECARD) {
sh_wdt_stop();
retval = 0;
}
break;
case WDIOC_KEEPALIVE:
next_heartbeat = user_ping_period(clock_division_ratio);
if (options & WDIOS_ENABLECARD) {
sh_wdt_start();
retval = 0;
}
break;
return retval;
}
default:
return -ENOTTY;
}
......@@ -328,7 +330,7 @@ static int sh_wdt_notify_sys(struct notifier_block *this,
static struct file_operations sh_wdt_fops = {
.owner = THIS_MODULE,
.read = sh_wdt_read,
.llseek = no_llseek,
.write = sh_wdt_write,
.ioctl = sh_wdt_ioctl,
.open = sh_wdt_open,
......@@ -343,14 +345,13 @@ static struct watchdog_info sh_wdt_info = {
static struct notifier_block sh_wdt_notifier = {
.notifier_call = sh_wdt_notify_sys,
.next = NULL,
.priority = 0
.priority = 0,
};
static struct miscdevice sh_wdt_miscdev = {
.minor = WATCHDOG_MINOR,
.name = "watchdog",
.fops &sh_wdt_fops,
.fops = &sh_wdt_fops,
};
/**
......@@ -366,23 +367,8 @@ static int __init sh_wdt_init(void)
return -EINVAL;
}
if (!request_region(WTCNT, 1, "shwdt")) {
printk(KERN_ERR "shwdt: Can't request WTCNT region\n");
misc_deregister(&sh_wdt_miscdev);
return -ENXIO;
}
if (!request_region(WTCSR, 1, "shwdt")) {
printk(KERN_ERR "shwdt: Can't request WTCSR region\n");
release_region(WTCNT, 1);
misc_deregister(&sh_wdt_miscdev);
return -ENXIO;
}
if (register_reboot_notifier(&sh_wdt_notifier)) {
printk(KERN_ERR "shwdt: Can't register reboot notifier\n");
release_region(WTCSR, 1);
release_region(WTCNT, 1);
misc_deregister(&sh_wdt_miscdev);
return -EINVAL;
}
......@@ -403,16 +389,16 @@ static int __init sh_wdt_init(void)
static void __exit sh_wdt_exit(void)
{
unregister_reboot_notifier(&sh_wdt_notifier);
release_region(WTCSR, 1);
release_region(WTCNT, 1);
misc_deregister(&sh_wdt_miscdev);
}
MODULE_AUTHOR("Paul Mundt <lethal@0xd6.org>");
MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
MODULE_DESCRIPTION("SuperH watchdog driver");
MODULE_LICENSE("GPL");
MODULE_PARM(clock_division_ratio, "i");
MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). Defaults to 0x7.");
MODULE_PARM(nowayout,"i");
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
module_init(sh_wdt_init);
module_exit(sh_wdt_exit);
......
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