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Commit ed21e007 authored by James Hogan's avatar James Hogan
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MIPS: VZ: Pass GC0 register names in $n format 

Now that we are using assembler macros to implement VZ instructions on
toolchains which don't support them, pass VZ guest Cop0 register names
to the __{read,write}_{32bit,ulong,64bit}_gc0_register macros in $n
format rather than register numbers. This is to make them consistent
with the normal root Cop0 register access macros which they were
originally based on.
Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17773/
parent 00b4eb40
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Showing with 188 additions and 188 deletions
arch/mips/include/asm/mipsregs.h
View file @ ed21e007
......@@ -1964,10 +1964,10 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
".set\tpush\n\t" \
".set\tmips32r2\n\t" \
_ASM_SET_VIRT \
"mfgc0\t%0, $%1, %2\n\t" \
"mfgc0\t%0, " #source ", %1\n\t" \
".set\tpop" \
: "=r" (__res) \
: "i" (source), "i" (sel)); \
: "i" (sel)); \
__res; \
})
......@@ -1977,10 +1977,10 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
".set\tpush\n\t" \
".set\tmips64r2\n\t" \
_ASM_SET_VIRT \
"dmfgc0\t%0, $%1, %2\n\t" \
"dmfgc0\t%0, " #source ", %1\n\t" \
".set\tpop" \
: "=r" (__res) \
: "i" (source), "i" (sel)); \
: "i" (sel)); \
__res; \
})
......@@ -1990,10 +1990,10 @@ do { \
".set\tpush\n\t" \
".set\tmips32r2\n\t" \
_ASM_SET_VIRT \
"mtgc0\t%z0, $%1, %2\n\t" \
"mtgc0\t%z0, " #register ", %1\n\t" \
".set\tpop" \
: : "Jr" ((unsigned int)(value)), \
"i" (register), "i" (sel)); \
"i" (sel)); \
} while (0)
#define __write_64bit_gc0_register(register, sel, value) \
......@@ -2002,10 +2002,10 @@ do { \
".set\tpush\n\t" \
".set\tmips64r2\n\t" \
_ASM_SET_VIRT \
"dmtgc0\t%z0, $%1, %2\n\t" \
"dmtgc0\t%z0, " #register ", %1\n\t" \
".set\tpop" \
: : "Jr" (value), \
"i" (register), "i" (sel)); \
"i" (sel)); \
} while (0)
#define __read_ulong_gc0_register(reg, sel) \
......@@ -2021,207 +2021,207 @@ do { \
__write_64bit_gc0_register(reg, sel, val); \
} while (0)
#define read_gc0_index() __read_32bit_gc0_register(0, 0)
#define write_gc0_index(val) __write_32bit_gc0_register(0, 0, val)
#define read_gc0_index() __read_32bit_gc0_register($0, 0)
#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
#define read_gc0_entrylo0() __read_ulong_gc0_register(2, 0)
#define write_gc0_entrylo0(val) __write_ulong_gc0_register(2, 0, val)
#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
#define read_gc0_entrylo1() __read_ulong_gc0_register(3, 0)
#define write_gc0_entrylo1(val) __write_ulong_gc0_register(3, 0, val)
#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
#define read_gc0_context() __read_ulong_gc0_register(4, 0)
#define write_gc0_context(val) __write_ulong_gc0_register(4, 0, val)
#define read_gc0_context() __read_ulong_gc0_register($4, 0)
#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
#define read_gc0_contextconfig() __read_32bit_gc0_register(4, 1)
#define write_gc0_contextconfig(val) __write_32bit_gc0_register(4, 1, val)
#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
#define read_gc0_userlocal() __read_ulong_gc0_register(4, 2)
#define write_gc0_userlocal(val) __write_ulong_gc0_register(4, 2, val)
#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
#define read_gc0_xcontextconfig() __read_ulong_gc0_register(4, 3)
#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register(4, 3, val)
#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
#define read_gc0_pagemask() __read_32bit_gc0_register(5, 0)
#define write_gc0_pagemask(val) __write_32bit_gc0_register(5, 0, val)
#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
#define read_gc0_pagegrain() __read_32bit_gc0_register(5, 1)
#define write_gc0_pagegrain(val) __write_32bit_gc0_register(5, 1, val)
#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
#define read_gc0_segctl0() __read_ulong_gc0_register(5, 2)
#define write_gc0_segctl0(val) __write_ulong_gc0_register(5, 2, val)
#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
#define read_gc0_segctl1() __read_ulong_gc0_register(5, 3)
#define write_gc0_segctl1(val) __write_ulong_gc0_register(5, 3, val)
#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
#define read_gc0_segctl2() __read_ulong_gc0_register(5, 4)
#define write_gc0_segctl2(val) __write_ulong_gc0_register(5, 4, val)
#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
#define read_gc0_pwbase() __read_ulong_gc0_register(5, 5)
#define write_gc0_pwbase(val) __write_ulong_gc0_register(5, 5, val)
#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
#define read_gc0_pwfield() __read_ulong_gc0_register(5, 6)
#define write_gc0_pwfield(val) __write_ulong_gc0_register(5, 6, val)
#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
#define read_gc0_pwsize() __read_ulong_gc0_register(5, 7)
#define write_gc0_pwsize(val) __write_ulong_gc0_register(5, 7, val)
#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
#define read_gc0_wired() __read_32bit_gc0_register(6, 0)
#define write_gc0_wired(val) __write_32bit_gc0_register(6, 0, val)
#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
#define read_gc0_pwctl() __read_32bit_gc0_register(6, 6)
#define write_gc0_pwctl(val) __write_32bit_gc0_register(6, 6, val)
#define read_gc0_hwrena() __read_32bit_gc0_register(7, 0)
#define write_gc0_hwrena(val) __write_32bit_gc0_register(7, 0, val)
#define read_gc0_badvaddr() __read_ulong_gc0_register(8, 0)
#define write_gc0_badvaddr(val) __write_ulong_gc0_register(8, 0, val)
#define read_gc0_badinstr() __read_32bit_gc0_register(8, 1)
#define write_gc0_badinstr(val) __write_32bit_gc0_register(8, 1, val)
#define read_gc0_badinstrp() __read_32bit_gc0_register(8, 2)
#define write_gc0_badinstrp(val) __write_32bit_gc0_register(8, 2, val)
#define read_gc0_count() __read_32bit_gc0_register(9, 0)
#define read_gc0_entryhi() __read_ulong_gc0_register(10, 0)
#define write_gc0_entryhi(val) __write_ulong_gc0_register(10, 0, val)
#define read_gc0_compare() __read_32bit_gc0_register(11, 0)
#define write_gc0_compare(val) __write_32bit_gc0_register(11, 0, val)
#define read_gc0_status() __read_32bit_gc0_register(12, 0)
#define write_gc0_status(val) __write_32bit_gc0_register(12, 0, val)
#define read_gc0_intctl() __read_32bit_gc0_register(12, 1)
#define write_gc0_intctl(val) __write_32bit_gc0_register(12, 1, val)
#define read_gc0_cause() __read_32bit_gc0_register(13, 0)
#define write_gc0_cause(val) __write_32bit_gc0_register(13, 0, val)
#define read_gc0_epc() __read_ulong_gc0_register(14, 0)
#define write_gc0_epc(val) __write_ulong_gc0_register(14, 0, val)
#define read_gc0_prid() __read_32bit_gc0_register(15, 0)
#define read_gc0_ebase() __read_32bit_gc0_register(15, 1)
#define write_gc0_ebase(val) __write_32bit_gc0_register(15, 1, val)
#define read_gc0_ebase_64() __read_64bit_gc0_register(15, 1)
#define write_gc0_ebase_64(val) __write_64bit_gc0_register(15, 1, val)
#define read_gc0_config() __read_32bit_gc0_register(16, 0)
#define read_gc0_config1() __read_32bit_gc0_register(16, 1)
#define read_gc0_config2() __read_32bit_gc0_register(16, 2)
#define read_gc0_config3() __read_32bit_gc0_register(16, 3)
#define read_gc0_config4() __read_32bit_gc0_register(16, 4)
#define read_gc0_config5() __read_32bit_gc0_register(16, 5)
#define read_gc0_config6() __read_32bit_gc0_register(16, 6)
#define read_gc0_config7() __read_32bit_gc0_register(16, 7)
#define write_gc0_config(val) __write_32bit_gc0_register(16, 0, val)
#define write_gc0_config1(val) __write_32bit_gc0_register(16, 1, val)
#define write_gc0_config2(val) __write_32bit_gc0_register(16, 2, val)
#define write_gc0_config3(val) __write_32bit_gc0_register(16, 3, val)
#define write_gc0_config4(val) __write_32bit_gc0_register(16, 4, val)
#define write_gc0_config5(val) __write_32bit_gc0_register(16, 5, val)
#define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val)
#define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val)
#define read_gc0_lladdr() __read_ulong_gc0_register(17, 0)
#define write_gc0_lladdr(val) __write_ulong_gc0_register(17, 0, val)
#define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0)
#define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1)
#define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2)
#define read_gc0_watchlo3() __read_ulong_gc0_register(18, 3)
#define read_gc0_watchlo4() __read_ulong_gc0_register(18, 4)
#define read_gc0_watchlo5() __read_ulong_gc0_register(18, 5)
#define read_gc0_watchlo6() __read_ulong_gc0_register(18, 6)
#define read_gc0_watchlo7() __read_ulong_gc0_register(18, 7)
#define write_gc0_watchlo0(val) __write_ulong_gc0_register(18, 0, val)
#define write_gc0_watchlo1(val) __write_ulong_gc0_register(18, 1, val)
#define write_gc0_watchlo2(val) __write_ulong_gc0_register(18, 2, val)
#define write_gc0_watchlo3(val) __write_ulong_gc0_register(18, 3, val)
#define write_gc0_watchlo4(val) __write_ulong_gc0_register(18, 4, val)
#define write_gc0_watchlo5(val) __write_ulong_gc0_register(18, 5, val)
#define write_gc0_watchlo6(val) __write_ulong_gc0_register(18, 6, val)
#define write_gc0_watchlo7(val) __write_ulong_gc0_register(18, 7, val)
#define read_gc0_watchhi0() __read_32bit_gc0_register(19, 0)
#define read_gc0_watchhi1() __read_32bit_gc0_register(19, 1)
#define read_gc0_watchhi2() __read_32bit_gc0_register(19, 2)
#define read_gc0_watchhi3() __read_32bit_gc0_register(19, 3)
#define read_gc0_watchhi4() __read_32bit_gc0_register(19, 4)
#define read_gc0_watchhi5() __read_32bit_gc0_register(19, 5)
#define read_gc0_watchhi6() __read_32bit_gc0_register(19, 6)
#define read_gc0_watchhi7() __read_32bit_gc0_register(19, 7)
#define write_gc0_watchhi0(val) __write_32bit_gc0_register(19, 0, val)
#define write_gc0_watchhi1(val) __write_32bit_gc0_register(19, 1, val)
#define write_gc0_watchhi2(val) __write_32bit_gc0_register(19, 2, val)
#define write_gc0_watchhi3(val) __write_32bit_gc0_register(19, 3, val)
#define write_gc0_watchhi4(val) __write_32bit_gc0_register(19, 4, val)
#define write_gc0_watchhi5(val) __write_32bit_gc0_register(19, 5, val)
#define write_gc0_watchhi6(val) __write_32bit_gc0_register(19, 6, val)
#define write_gc0_watchhi7(val) __write_32bit_gc0_register(19, 7, val)
#define read_gc0_xcontext() __read_ulong_gc0_register(20, 0)
#define write_gc0_xcontext(val) __write_ulong_gc0_register(20, 0, val)
#define read_gc0_perfctrl0() __read_32bit_gc0_register(25, 0)
#define write_gc0_perfctrl0(val) __write_32bit_gc0_register(25, 0, val)
#define read_gc0_perfcntr0() __read_32bit_gc0_register(25, 1)
#define write_gc0_perfcntr0(val) __write_32bit_gc0_register(25, 1, val)
#define read_gc0_perfcntr0_64() __read_64bit_gc0_register(25, 1)
#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register(25, 1, val)
#define read_gc0_perfctrl1() __read_32bit_gc0_register(25, 2)
#define write_gc0_perfctrl1(val) __write_32bit_gc0_register(25, 2, val)
#define read_gc0_perfcntr1() __read_32bit_gc0_register(25, 3)
#define write_gc0_perfcntr1(val) __write_32bit_gc0_register(25, 3, val)
#define read_gc0_perfcntr1_64() __read_64bit_gc0_register(25, 3)
#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register(25, 3, val)
#define read_gc0_perfctrl2() __read_32bit_gc0_register(25, 4)
#define write_gc0_perfctrl2(val) __write_32bit_gc0_register(25, 4, val)
#define read_gc0_perfcntr2() __read_32bit_gc0_register(25, 5)
#define write_gc0_perfcntr2(val) __write_32bit_gc0_register(25, 5, val)
#define read_gc0_perfcntr2_64() __read_64bit_gc0_register(25, 5)
#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register(25, 5, val)
#define read_gc0_perfctrl3() __read_32bit_gc0_register(25, 6)
#define write_gc0_perfctrl3(val) __write_32bit_gc0_register(25, 6, val)
#define read_gc0_perfcntr3() __read_32bit_gc0_register(25, 7)
#define write_gc0_perfcntr3(val) __write_32bit_gc0_register(25, 7, val)
#define read_gc0_perfcntr3_64() __read_64bit_gc0_register(25, 7)
#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register(25, 7, val)
#define read_gc0_errorepc() __read_ulong_gc0_register(30, 0)
#define write_gc0_errorepc(val) __write_ulong_gc0_register(30, 0, val)
#define read_gc0_kscratch1() __read_ulong_gc0_register(31, 2)
#define read_gc0_kscratch2() __read_ulong_gc0_register(31, 3)
#define read_gc0_kscratch3() __read_ulong_gc0_register(31, 4)
#define read_gc0_kscratch4() __read_ulong_gc0_register(31, 5)
#define read_gc0_kscratch5() __read_ulong_gc0_register(31, 6)
#define read_gc0_kscratch6() __read_ulong_gc0_register(31, 7)
#define write_gc0_kscratch1(val) __write_ulong_gc0_register(31, 2, val)
#define write_gc0_kscratch2(val) __write_ulong_gc0_register(31, 3, val)
#define write_gc0_kscratch3(val) __write_ulong_gc0_register(31, 4, val)
#define write_gc0_kscratch4(val) __write_ulong_gc0_register(31, 5, val)
#define write_gc0_kscratch5(val) __write_ulong_gc0_register(31, 6, val)
#define write_gc0_kscratch6(val) __write_ulong_gc0_register(31, 7, val)
#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
#define read_gc0_count() __read_32bit_gc0_register($9, 0)
#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
#define read_gc0_status() __read_32bit_gc0_register($12, 0)
#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
#define read_gc0_config() __read_32bit_gc0_register($16, 0)
#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
/* Cavium OCTEON (cnMIPS) */
#define read_gc0_cvmcount() __read_ulong_gc0_register(9, 6)
#define write_gc0_cvmcount(val) __write_ulong_gc0_register(9, 6, val)
#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
#define read_gc0_cvmctl() __read_64bit_gc0_register(9, 7)
#define write_gc0_cvmctl(val) __write_64bit_gc0_register(9, 7, val)
#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
#define read_gc0_cvmmemctl() __read_64bit_gc0_register(11, 7)
#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register(11, 7, val)
#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
#define read_gc0_cvmmemctl2() __read_64bit_gc0_register(16, 6)
#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register(16, 6, val)
#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
/*
* Macros to access the floating point coprocessor control registers
......
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