Commit f317e689 authored by Gabriel FERNANDEZ's avatar Gabriel FERNANDEZ Committed by Maxime Coquelin

ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12

Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: default avatarPankaj Dev <pankaj.dev@st.com>
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarMaxime Coquelin <maxime.coquelin@st.com>
parent d0128b7d
...@@ -5,8 +5,15 @@ ...@@ -5,8 +5,15 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <dt-bindings/clock/stih415-clks.h>
/ { / {
clocks { clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* /*
* Fixed 30MHz oscillator input to SoC * Fixed 30MHz oscillator input to SoC
*/ */
...@@ -48,5 +55,473 @@ CLKS_ETH1_PHY: clockgenA0@7 { ...@@ -48,5 +55,473 @@ CLKS_ETH1_PHY: clockgenA0@7 {
clock-frequency = <25000000>; clock-frequency = <25000000>;
clock-output-names = "CLKS_ETH1_PHY"; clock-output-names = "CLKS_ETH1_PHY";
}; };
/*
* ClockGenAs on SASG1
*/
clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};
clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a0-osc-prediv";
};
clk_s_a0_hs: clk-s-a0-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 0>, /* PLL0 HS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* Fourth output unused */
};
clk_s_a0_ls: clk-s-a0-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a0_osc_prediv>,
<&clk_s_a0_pll 1>, /* PLL0 LS */
<&clk_s_a0_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-reg-0",
"clk-s-icn-if-0",
"clk-s-icn-reg-lp-0",
"clk-s-emiss",
"clk-s-eth1-phy",
"clk-s-mii-ref-out";
/* Remaining outputs unused */
};
};
clockgen-a@fee81000 {
reg = <0xfee81000 0xb48>;
clk_s_a1_pll: clk-s-a1-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-pll0-hs",
"clk-s-a1-pll0-ls",
"clk-s-a1-pll1";
};
clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-s-a1-osc-prediv";
};
clk_s_a1_hs: clk-s-a1-hs {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 0>, /* PLL0 HS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "", /* Reserved */
"", /* Reserved */
"clk-s-stac-phy",
"clk-s-vtac-tx-phy";
};
clk_s_a1_ls: clk-s-a1-ls {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-ls",
"st,clkgena-divmux";
clocks = <&clk_s_a1_osc_prediv>,
<&clk_s_a1_pll 1>, /* PLL0 LS */
<&clk_s_a1_pll 2>; /* PLL1 */
clock-output-names = "clk-s-icn-if-2",
"clk-s-card-mmc",
"clk-s-icn-if-1",
"clk-s-gmac0-phy",
"clk-s-nand-ctrl",
"", /* Reserved */
"clk-s-mii0-ref-out",
""; /* clk-s-stac-sys */
/* Remaining outputs unused */
};
};
/*
* ClockGenAs on MPE41
*/
clockgen-a@fde12000 {
reg = <0xfde12000 0xb50>;
clk_m_a0_pll0: clk-m-a0-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll0-phi0",
"clk-m-a0-pll0-phi1",
"clk-m-a0-pll0-phi2",
"clk-m-a0-pll0-phi3";
};
clk_m_a0_pll1: clk-m-a0-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-pll1-phi0",
"clk-m-a0-pll1-phi1",
"clk-m-a0-pll1-phi2",
"clk-m-a0-pll1-phi3";
};
clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a0-osc-prediv";
};
clk_m_a0_div0: clk-m-a0-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-apb-pm", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"clk-m-pp-dmu-0",
"clk-m-pp-dmu-1",
"clk-m-icm-disp",
""; /* Unused */
};
clk_m_a0_div1: clk-m-a0-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "", /* Unused */
"", /* Unused */
"clk-m-a9-ext2f",
"clk-m-st40rt",
"clk-m-st231-dmu-0",
"clk-m-st231-dmu-1",
"clk-m-st231-aud",
"clk-m-st231-gp-0";
};
clk_m_a0_div2: clk-m-a0-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-st231-gp-1",
"clk-m-icn-cpu",
"clk-m-icn-stac",
"clk-m-icn-dmu-0",
"clk-m-icn-dmu-1",
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
clk_m_a0_div3: clk-m-a0-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a0_osc_prediv>,
<&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"clk-m-icn-eram",
"clk-m-a9-trace";
};
};
clockgen-a@fd6db000 {
reg = <0xfd6db000 0xb50>;
clk_m_a1_pll0: clk-m-a1-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll0-phi0",
"clk-m-a1-pll0-phi1",
"clk-m-a1-pll0-phi2",
"clk-m-a1-pll0-phi3";
};
clk_m_a1_pll1: clk-m-a1-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-pll1-phi0",
"clk-m-a1-pll1-phi1",
"clk-m-a1-pll1-phi2",
"clk-m-a1-pll1-phi3";
};
clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a1-osc-prediv";
};
clk_m_a1_div0: clk-m-a1-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-fdma-12",
"clk-m-fdma-10",
"clk-m-fdma-11",
"clk-m-hva-lmi",
"clk-m-proc-sc",
"clk-m-tp",
"clk-m-icn-gpu",
"clk-m-icn-vdp-0";
};
clk_m_a1_div1: clk-m-a1-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "clk-m-icn-vdp-1",
"clk-m-icn-vdp-2",
"clk-m-icn-vdp-3",
"clk-m-prv-t1-bus",
"clk-m-icn-vdp-4",
"clk-m-icn-reg-10",
"", /* Unused */
""; /* clk-m-icn-st231 */
};
clk_m_a1_div2: clk-m-a1-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "clk-m-fvdp-proc-alt",
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
clk_m_a1_div3: clk-m-a1-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a1_osc_prediv>,
<&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
clock-output-names = "", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
"", /* Unused */
""; /* Unused */
};
};
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a0_div1 2>;
clock-div = <2>;
clock-mult = <1>;
};
clockgen-a@fd345000 {
reg = <0xfd345000 0xb50>;
clk_m_a2_pll0: clk-m-a2-pll0 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll0-phi0",
"clk-m-a2-pll0-phi1",
"clk-m-a2-pll0-phi2",
"clk-m-a2-pll0-phi3";
};
clk_m_a2_pll1: clk-m-a2-pll1 {
#clock-cells = <1>;
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-pll1-phi0",
"clk-m-a2-pll1-phi1",
"clk-m-a2-pll1-phi2",
"clk-m-a2-pll1-phi3";
};
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c32",
"st,clkgena-prediv";
clocks = <&clk_sysin>;
clock-output-names = "clk-m-a2-osc-prediv";
};
clk_m_a2_div0: clk-m-a2-div0 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf0",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
<&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
clock-output-names = "clk-m-vtac-main-phy",
"clk-m-vtac-aux-phy",
"clk-m-stac-phy",
"clk-m-stac-sys",
"", /* clk-m-mpestac-pg */
"", /* clk-m-mpestac-wc */
"", /* clk-m-mpevtacaux-pg*/
""; /* clk-m-mpevtacmain-pg*/
};
clk_m_a2_div1: clk-m-a2-div1 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf1",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
<&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
clock-output-names = "", /* clk-m-mpevtacrx0-wc */
"", /* clk-m-mpevtacrx1-wc */
"clk-m-compo-main",
"clk-m-compo-aux",
"clk-m-bdisp-0",
"clk-m-bdisp-1",
"clk-m-icn-bdisp-0",
"clk-m-icn-bdisp-1";
};
clk_m_a2_div2: clk-m-a2-div2 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf2",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
<&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
clock-output-names = "", /* clk-m-icn-hqvdp0 */
"", /* clk-m-icn-hqvdp1 */
"clk-m-icn-compo",
"", /* clk-m-icn-vdpaux */
"clk-m-icn-ts",
"clk-m-icn-reg-lp-10",
"clk-m-dcephy-impctrl",
""; /* Unused */
};
clk_m_a2_div3: clk-m-a2-div3 {
#clock-cells = <1>;
compatible = "st,clkgena-divmux-c32-odf3",
"st,clkgena-divmux";
clocks = <&clk_m_a2_osc_prediv>,
<&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
<&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
clock-output-names = ""; /* Unused */
/* Remaining outputs unused */
};
};
}; };
}; };
...@@ -82,7 +82,7 @@ serial2: serial@fed32000 { ...@@ -82,7 +82,7 @@ serial2: serial@fed32000 {
interrupts = <0 197 0>; interrupts = <0 197 0>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2>; pinctrl-0 = <&pinctrl_serial2>;
clocks = <&CLKS_ICN_REG_0>; clocks = <&clk_s_a0_ls CLK_ICN_REG>;
}; };
/* SBC comms block ASCs in SASG1 */ /* SBC comms block ASCs in SASG1 */
...@@ -100,7 +100,7 @@ i2c@fed40000 { ...@@ -100,7 +100,7 @@ i2c@fed40000 {
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>; reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLKS_ICN_REG_0>; clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -113,7 +113,7 @@ i2c@fed41000 { ...@@ -113,7 +113,7 @@ i2c@fed41000 {
compatible = "st,comms-ssc4-i2c"; compatible = "st,comms-ssc4-i2c";
reg = <0xfed41000 0x110>; reg = <0xfed41000 0x110>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CLKS_ICN_REG_0>; clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc"; clock-names = "ssc";
clock-frequency = <400000>; clock-frequency = <400000>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -170,7 +170,7 @@ ethernet0: dwmac@fe810000 { ...@@ -170,7 +170,7 @@ ethernet0: dwmac@fe810000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii0>; pinctrl-0 = <&pinctrl_mii0>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";
clocks = <&CLKS_GMAC0_PHY>; clocks = <&clk_s_a1_ls CLK_GMAC0_PHY>;
}; };
ethernet1: dwmac@fef08000 { ethernet1: dwmac@fef08000 {
...@@ -193,7 +193,7 @@ ethernet1: dwmac@fef08000 { ...@@ -193,7 +193,7 @@ ethernet1: dwmac@fef08000 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mii1>; pinctrl-0 = <&pinctrl_mii1>;
clock-names = "stmmaceth"; clock-names = "stmmaceth";
clocks = <&CLKS_ETH1_PHY>; clocks = <&clk_s_a0_ls CLK_ETH1_PHY>;
}; };
rc: rc@fe518000 { rc: rc@fe518000 {
......
/*
* This header provides constants clk index STMicroelectronics
* STiH415 SoC.
*/
#ifndef _CLK_STIH415
#define _CLK_STIH415
/* CLOCKGEN A0 */
#define CLK_ICN_REG 0
#define CLK_ETH1_PHY 4
/* CLOCKGEN A1 */
#define CLK_GMAC0_PHY 3
#endif
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