Commit f75e0c2e authored by Dave Kleikamp's avatar Dave Kleikamp

Merge kleikamp.austin.ibm.com:/home/shaggy/bk/linus-2.5

into kleikamp.austin.ibm.com:/home/shaggy/bk/jfs-2.5
parents 01b1df28 c0a01355
......@@ -128,16 +128,6 @@ MODULE PARAMETERS:
programs that expect RGB data (e.g. gqcam) to work with this driver. If
your colors look VERY wrong, you may want to change this.
NAME: buf_timeout (Temporarily disabled. Memory is deallocated immediately)
TYPE: integer
DEFAULT: 5 (seconds)
DESC: Number of seconds before unused frame buffers are deallocated.
Previously, memory was allocated upon open() and deallocated upon
close(). Deallocation now occurs only if the driver is closed and this
timeout is reached. If you are capturing frames less frequently than
the default timeout, increase this. This will not make any difference
with programs that capture multiple frames during an open/close cycle.
NAME: cams
TYPE: integer (1-4 for OV511, 1-31 for OV511+)
DEFAULT: 1
......@@ -161,13 +151,6 @@ MODULE PARAMETERS:
DESC: This configures the camera's sensor to transmit a colored test-pattern
instead of an image. This does not work correctly yet.
NAME: sensor_gbr (*** TEMPORARILY DISABLED ***)
TYPE: integer (Boolean)
DEFAULT: 0
DESC: This makes the sensor output GBR422 instead of YUV420. This saves the
driver the trouble of converting YUV to RGB, but it currently does not
work very well (the colors are not quite right)
NAME: dumppix
TYPE: integer (0-2)
DEFAULT: 0
......@@ -259,14 +242,6 @@ MODULE PARAMETERS:
13 VIDEO_PALETTE_YUV422P (YUV 4:2:2 Planar)
15 VIDEO_PALETTE_YUV420P (YUV 4:2:0 Planar, same as 10)
NAME: tuner
TYPE: integer
DEFAULT: -1 (autodetect)
DESC: This sets the exact type of the tuner module in a device. This is set
automatically based on the custom ID of the OV511 device. In cases
where this fails, you can override this auto-detection. Please see
linux/drivers/media/video/tuner.h for a complete list.
NAME: backlight
TYPE: integer (Boolean)
DEFAULT: 0 (off)
......
CONFIG_AGP
AGP (Accelerated Graphics Port) is a bus system mainly used to
connect graphics cards to the rest of the system.
If you have an AGP system and you say Y here, it will be possible to
use the AGP features of your 3D rendering video card. This code acts
as a sort of "AGP driver" for the motherboard's chipset.
If you need more texture memory than you can get with the AGP GART
(theoretically up to 256 MB, but in practice usually 64 or 128 MB
due to kernel allocation issues), you could use PCI accesses
and have up to a couple gigs of texture space.
Note that this is the only means to have XFree4/GLX use
write-combining with MTRR support on the AGP bus. Without it, OpenGL
direct rendering will be a lot slower but still faster than PIO.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
This driver is available as a module. If you want to compile it as
a module, say M here and read <file:Documentation/modules.txt>. The
module will be called agpgart.o.
CONFIG_AGP_INTEL
This option gives you AGP support for the GLX component of the
XFree86 4.x on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850 and 860 chipsets.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
CONFIG_AGP_I810
This option gives you AGP support for the Xserver on the Intel 810
815 and 830m chipset boards for their on-board integrated graphics. This
is required to do any useful video modes with these boards.
CONFIG_AGP_I460
This option gives you AGP GART support for the Intel 460GX chipset
for IA64 processors.
CONFIG_AGP_VIA
This option gives you AGP support for the GLX component of the
XFree86 4.x on VIA MPV3/Apollo Pro chipsets.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
CONFIG_AGP_AMD
This option gives you AGP support for the GLX component of the
XFree86 4.x on AMD Irongate, 761, and 762 chipsets.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
CONFIG_AGP_SIS
This option gives you AGP support for the GLX component of the "soon
to be released" XFree86 4.x on Silicon Integrated Systems [SiS]
chipsets.
Note that 5591/5592 AGP chipsets are NOT supported.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
CONFIG_AGP_SWORKS
Say Y here to support the Serverworks AGP card. See
<http://www.serverworks.com/> for product descriptions and images.
CONFIG_AGP_ALI
This option gives you AGP support for the GLX component of the
XFree86 4.x on the following ALi chipsets. The supported chipsets
include M1541, M1621, M1631, M1632, M1641,M1647,and M1651.
For the ALi-chipset question, ALi suggests you refer to
<http://www.ali.com.tw/eng/support/index.shtml>.
The M1541 chipset can do AGP 1x and 2x, but note that there is an
acknowledged incompatibility with Matrox G200 cards. Due to
timing issues, this chipset cannot do AGP 2x with the G200.
This is a hardware limitation. AGP 1x seems to be fine, though.
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
CONFIG_AGP_HP_ZX1
This option gives you AGP GART support for the HP ZX1 chipset
for IA64 processors.
dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
if [ "$CONFIG_AGP" != "n" ]; then
bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
bool ' VIA chipset support' CONFIG_AGP_VIA
bool ' AMD Irongate, 761, and 762 support' CONFIG_AGP_AMD
bool ' Generic SiS support' CONFIG_AGP_SIS
bool ' ALI chipset support' CONFIG_AGP_ALI
bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
if [ "$CONFIG_IA64" = "y" ]; then
bool ' Intel 460GX support' CONFIG_AGP_I460
bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
fi
fi
......@@ -3,9 +3,20 @@
# space ioctl interface to use agp memory. It also adds a kernel interface
# that other drivers could use to manipulate agp memory.
export-objs := agpgart_be.o
export-objs := agp.o
agpgart-objs := agpgart_fe.o agpgart_be.o
agpgart-y := agp.o frontend.o
agpgart-$(CONFIG_AGP_INTEL) += i8x0-agp.o
agpgart-$(CONFIG_AGP_I810) += i810-agp.o
agpgart-$(CONFIG_AGP_VIA) += via-agp.o
agpgart-$(CONFIG_AGP_AMD) += amd-agp.o
agpgart-$(CONFIG_AGP_SIS) += sis-agp.o
agpgart-$(CONFIG_AGP_ALI) += ali-agp.o
agpgart-$(CONFIG_AGP_SWORKS) += sworks-agp.o
agpgart-$(CONFIG_AGP_I460) += i460-agp.o
agpgart-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
agpgart-objs := $(agpgart-y)
obj-$(CONFIG_AGP) += agpgart.o
......
This diff is collapsed.
......@@ -27,6 +27,67 @@
#ifndef _AGP_BACKEND_PRIV_H
#define _AGP_BACKEND_PRIV_H 1
#include <asm/agp.h> /* for flush_agp_cache() */
extern struct agp_bridge_data agp_bridge;
/* Generic routines. */
void agp_generic_agp_enable(u32 mode);
int agp_generic_create_gatt_table(void);
int agp_generic_free_gatt_table(void);
agp_memory *agp_create_memory(int scratch_pages);
int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type);
int agp_generic_remove_memory(agp_memory * mem, off_t pg_start, int type);
agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
void agp_generic_free_by_type(agp_memory * curr);
void *agp_generic_alloc_page(void);
void agp_generic_destroy_page(void *addr);
int agp_generic_suspend(void);
void agp_generic_resume(void);
void agp_free_key(int key);
/* chipset specific init routines. */
int __init ali_generic_setup (struct pci_dev *pdev);
int __init amd_irongate_setup (struct pci_dev *pdev);
int __init hp_zx1_setup (struct pci_dev *pdev);
int __init intel_i460_setup (struct pci_dev *pdev);
int __init intel_generic_setup (struct pci_dev *pdev);
int __init intel_i810_setup(struct pci_dev *i810_dev);
int __init intel_815_setup(struct pci_dev *pdev);
int __init intel_i830_setup(struct pci_dev *i830_dev);
int __init intel_820_setup (struct pci_dev *pdev);
int __init intel_830mp_setup (struct pci_dev *pdev);
int __init intel_840_setup (struct pci_dev *pdev);
int __init intel_845_setup (struct pci_dev *pdev);
int __init intel_850_setup (struct pci_dev *pdev);
int __init intel_860_setup (struct pci_dev *pdev);
int __init serverworks_setup (struct pci_dev *pdev);
int __init sis_generic_setup (struct pci_dev *pdev);
int __init via_generic_setup (struct pci_dev *pdev);
#define AGPGART_MODULE_NAME "agpgart"
#define PFX AGPGART_MODULE_NAME ": "
#ifdef CONFIG_SMP
static void ipi_handler(void *null)
{
flush_agp_cache();
}
static void __attribute__((unused)) global_cache_flush(void)
{
if (smp_call_function(ipi_handler, NULL, 1, 1) != 0)
panic(PFX "timed out waiting for the other CPUs!\n");
flush_agp_cache();
}
#else
static void global_cache_flush(void)
{
flush_agp_cache();
}
#endif /* !CONFIG_SMP */
enum aper_size_type {
U8_APER_SIZE,
U16_APER_SIZE,
......@@ -35,55 +96,55 @@ enum aper_size_type {
FIXED_APER_SIZE
};
typedef struct _gatt_mask {
struct gatt_mask {
unsigned long mask;
u32 type;
/* totally device specific, for integrated chipsets that
* might have different types of memory masks. For other
* devices this will probably be ignored */
} gatt_mask;
};
typedef struct _aper_size_info_8 {
struct aper_size_info_8 {
int size;
int num_entries;
int page_order;
u8 size_value;
} aper_size_info_8;
};
typedef struct _aper_size_info_16 {
struct aper_size_info_16 {
int size;
int num_entries;
int page_order;
u16 size_value;
} aper_size_info_16;
};
typedef struct _aper_size_info_32 {
struct aper_size_info_32 {
int size;
int num_entries;
int page_order;
u32 size_value;
} aper_size_info_32;
};
typedef struct _aper_size_info_lvl2 {
struct aper_size_info_lvl2 {
int size;
int num_entries;
u32 size_value;
} aper_size_info_lvl2;
};
typedef struct _aper_size_info_fixed {
struct aper_size_info_fixed {
int size;
int num_entries;
int page_order;
} aper_size_info_fixed;
};
struct agp_bridge_data {
agp_version *version;
struct agp_version *version;
void *aperture_sizes;
void *previous_size;
void *current_size;
void *dev_private_data;
struct pci_dev *dev;
gatt_mask *masks;
struct gatt_mask *masks;
unsigned long *gatt_table;
unsigned long *gatt_table_real;
unsigned long scratch_page;
......@@ -140,11 +201,11 @@ struct agp_bridge_data {
#define GB(x) (MB (KB (x)))
#define CACHE_FLUSH agp_bridge.cache_flush
#define A_SIZE_8(x) ((aper_size_info_8 *) x)
#define A_SIZE_16(x) ((aper_size_info_16 *) x)
#define A_SIZE_32(x) ((aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((aper_size_info_fixed *) x)
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
#define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i)
#define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i)
#define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i)
......@@ -152,9 +213,6 @@ struct agp_bridge_data {
#define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
#define MAXKEY (4096 * 32)
#define AGPGART_MODULE_NAME "agpgart"
#define PFX AGPGART_MODULE_NAME ": "
#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
#ifndef PCI_DEVICE_ID_VIA_82C691_0
......@@ -305,6 +363,10 @@ struct agp_bridge_data {
/* This one is for I830MP w. an external graphic card */
#define INTEL_I830_ERRSTS 0x92
/* intel 815 register */
#define INTEL_815_APCONT 0x51
#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
/* intel i820 registers */
#define INTEL_I820_RDCR 0x51
#define INTEL_I820_ERRSTS 0xc8
......
This diff is collapsed.
/*
* AGPGART module version 0.99
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* TODO:
* - Allocate more than order 0 pages to avoid too much linear map splitting.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"
static int ali_fetch_size(void)
{
int i;
u32 temp;
struct aper_size_info_32 *values;
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
temp &= ~(0xfffffff0);
values = A_SIZE_32(agp_bridge.aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static void ali_tlbflush(agp_memory * mem)
{
u32 temp;
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
// clear tag
pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
((temp & 0xfffffff0) | 0x00000001|0x00000002));
}
static void ali_cleanup(void)
{
struct aper_size_info_32 *previous_size;
u32 temp;
previous_size = A_SIZE_32(agp_bridge.previous_size);
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
// clear tag
pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
((temp & 0xffffff00) | 0x00000001|0x00000002));
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
((temp & 0x00000ff0) | previous_size->size_value));
}
static int ali_configure(void)
{
u32 temp;
struct aper_size_info_32 *current_size;
current_size = A_SIZE_32(agp_bridge.current_size);
/* aperture size and gatt addr */
pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000))
| (current_size->size_value & 0xf));
pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp);
/* tlb control */
/*
* Question: Jeff, ALi's patch deletes this:
*
* pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
* pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL,
* ((temp & 0xffffff00) | 0x00000010));
*
* and replaces it with the following, which seems to duplicate the
* next couple of lines below it. I suspect this was an oversight,
* but you might want to check up on this?
*/
pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* address to map to */
pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
#if 0
if (agp_bridge.type == ALI_M1541) {
u32 nlvm_addr = 0;
switch (current_size->size_value) {
case 0: break;
case 1: nlvm_addr = 0x100000;break;
case 2: nlvm_addr = 0x200000;break;
case 3: nlvm_addr = 0x400000;break;
case 4: nlvm_addr = 0x800000;break;
case 6: nlvm_addr = 0x1000000;break;
case 7: nlvm_addr = 0x2000000;break;
case 8: nlvm_addr = 0x4000000;break;
case 9: nlvm_addr = 0x8000000;break;
case 10: nlvm_addr = 0x10000000;break;
default: break;
}
nlvm_addr--;
nlvm_addr&=0xfff00000;
nlvm_addr+= agp_bridge.gart_bus_addr;
nlvm_addr|=(agp_bridge.gart_bus_addr>>12);
printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr);
}
#endif
pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
temp &= 0xffffff7f; //enable TLB
pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp);
return 0;
}
static unsigned long ali_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
}
static void ali_cache_flush(void)
{
global_cache_flush();
if (agp_bridge.type == ALI_M1541) {
int i, page_count;
u32 temp;
page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order;
for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
(agp_bridge.gatt_bus_addr + i)) |
ALI_CACHE_FLUSH_EN));
}
}
}
static void *ali_alloc_page(void)
{
void *adr = agp_generic_alloc_page();
u32 temp;
if (adr == 0)
return 0;
if (agp_bridge.type == ALI_M1541) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(adr)) |
ALI_CACHE_FLUSH_EN ));
}
return adr;
}
static void ali_destroy_page(void * addr)
{
u32 temp;
if (addr == NULL)
return;
global_cache_flush();
if (agp_bridge.type == ALI_M1541) {
pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(addr)) |
ALI_CACHE_FLUSH_EN));
}
agp_generic_destroy_page(addr);
}
/* Setup function */
static struct gatt_mask ali_generic_masks[] =
{
{mask: 0x00000000, type: 0}
};
static struct aper_size_info_32 ali_generic_sizes[7] =
{
{256, 65536, 6, 10},
{128, 32768, 5, 9},
{64, 16384, 4, 8},
{32, 8192, 3, 7},
{16, 4096, 2, 6},
{8, 2048, 1, 4},
{4, 1024, 0, 3}
};
int __init ali_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = ali_generic_masks;
agp_bridge.num_of_masks = 1;
agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
agp_bridge.size_type = U32_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = ali_configure;
agp_bridge.fetch_size = ali_fetch_size;
agp_bridge.cleanup = ali_cleanup;
agp_bridge.tlb_flush = ali_tlbflush;
agp_bridge.mask_memory = ali_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = ali_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = ali_alloc_page;
agp_bridge.agp_destroy_page = ali_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
return 0;
(void) pdev; /* unused */
}
This diff is collapsed.
......@@ -24,29 +24,16 @@
*
*/
#define __NO_VERSION__
#include <linux/version.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/mman.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/pagemap.h>
#include <linux/miscdevice.h>
#include <linux/agp_backend.h>
#include <linux/agpgart.h>
#include <linux/smp_lock.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/mman.h>
#include "agp.h"
......
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/*
* AGPGART module version 0.99
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* TODO:
* - Allocate more than order 0 pages to avoid too much linear map splitting.
*/
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"
static int sis_fetch_size(void)
{
u8 temp_size;
int i;
struct aper_size_info_8 *values;
pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
values = A_SIZE_8(agp_bridge.aperture_sizes);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
if ((temp_size == values[i].size_value) ||
((temp_size & ~(0x03)) ==
(values[i].size_value & ~(0x03)))) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static void sis_tlbflush(agp_memory * mem)
{
pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
}
static int sis_configure(void)
{
u32 temp;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
agp_bridge.gatt_bus_addr);
pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
current_size->size_value);
return 0;
}
static void sis_cleanup(void)
{
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
(previous_size->size_value & ~(0x03)));
}
static unsigned long sis_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
}
static struct aper_size_info_8 sis_generic_sizes[7] =
{
{256, 65536, 6, 99},
{128, 32768, 5, 83},
{64, 16384, 4, 67},
{32, 8192, 3, 51},
{16, 4096, 2, 35},
{8, 2048, 1, 19},
{4, 1024, 0, 3}
};
static struct gatt_mask sis_generic_masks[] =
{
{mask: 0x00000000, type: 0}
};
int __init sis_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = sis_generic_masks;
agp_bridge.num_of_masks = 1;
agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = sis_configure;
agp_bridge.fetch_size = sis_fetch_size;
agp_bridge.cleanup = sis_cleanup;
agp_bridge.tlb_flush = sis_tlbflush;
agp_bridge.mask_memory = sis_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
return 0;
}
This diff is collapsed.
/*
* AGPGART module version 0.99
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* TODO:
* - Allocate more than order 0 pages to avoid too much linear map splitting.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include "agp.h"
static int via_fetch_size(void)
{
int i;
u8 temp;
struct aper_size_info_8 *values;
values = A_SIZE_8(agp_bridge.aperture_sizes);
pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp);
for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
agp_bridge.previous_size =
agp_bridge.current_size = (void *) (values + i);
agp_bridge.aperture_size_idx = i;
return values[i].size;
}
}
return 0;
}
static int via_configure(void)
{
u32 temp;
struct aper_size_info_8 *current_size;
current_size = A_SIZE_8(agp_bridge.current_size);
/* aperture size */
pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
current_size->size_value);
/* address to map too */
pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* GART control register */
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
/* attbase - aperture GATT base */
pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE,
(agp_bridge.gatt_bus_addr & 0xfffff000) | 3);
return 0;
}
static void via_cleanup(void)
{
struct aper_size_info_8 *previous_size;
previous_size = A_SIZE_8(agp_bridge.previous_size);
pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
previous_size->size_value);
/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
* during reinitialization.
*/
}
static void via_tlbflush(agp_memory * mem)
{
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f);
pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
}
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
return addr | agp_bridge.masks[0].mask;
}
static struct aper_size_info_8 via_generic_sizes[7] =
{
{256, 65536, 6, 0},
{128, 32768, 5, 128},
{64, 16384, 4, 192},
{32, 8192, 3, 224},
{16, 4096, 2, 240},
{8, 2048, 1, 248},
{4, 1024, 0, 252}
};
static struct gatt_mask via_generic_masks[] =
{
{mask: 0x00000000, type: 0}
};
int __init via_generic_setup (struct pci_dev *pdev)
{
agp_bridge.masks = via_generic_masks;
agp_bridge.num_of_masks = 1;
agp_bridge.aperture_sizes = (void *) via_generic_sizes;
agp_bridge.size_type = U8_APER_SIZE;
agp_bridge.num_aperture_sizes = 7;
agp_bridge.dev_private_data = NULL;
agp_bridge.needs_scratch_page = FALSE;
agp_bridge.configure = via_configure;
agp_bridge.fetch_size = via_fetch_size;
agp_bridge.cleanup = via_cleanup;
agp_bridge.tlb_flush = via_tlbflush;
agp_bridge.mask_memory = via_mask_memory;
agp_bridge.agp_enable = agp_generic_agp_enable;
agp_bridge.cache_flush = global_cache_flush;
agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
agp_bridge.insert_memory = agp_generic_insert_memory;
agp_bridge.remove_memory = agp_generic_remove_memory;
agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
agp_bridge.free_by_type = agp_generic_free_by_type;
agp_bridge.agp_alloc_page = agp_generic_alloc_page;
agp_bridge.agp_destroy_page = agp_generic_destroy_page;
agp_bridge.suspend = agp_generic_suspend;
agp_bridge.resume = agp_generic_resume;
agp_bridge.cant_use_aperture = 0;
return 0;
(void) pdev; /* unused */
}
......@@ -708,7 +708,14 @@ CONFIG_BLK_DEV_IDE_TCQ
Digital drives in the Expert series (by nature of really being IBM
drives).
If you have such a drive, say Y here.
However, please, note that there are host chip controllers which will
not cooperate properly if TCQ is enabled. This may cause serious
data loss!
Since enabling TCQ doesn't appear to have any noticeable performance
impact on Linux: [feel free to correct me if you wish too please]
Generally say N here.
CONFIG_BLK_DEV_IDE_TCQ_DEPTH
Maximum size of commands to enable per-drive. Any value between 1
......
......@@ -34,7 +34,7 @@ if [ "$CONFIG_BLK_DEV_IDE" != "n" ]; then
dep_bool ' Use PCI DMA by default when available' CONFIG_IDEDMA_PCI_AUTO $CONFIG_BLK_DEV_IDEDMA_PCI
dep_bool ' Enable DMA only for disks ' CONFIG_IDEDMA_ONLYDISK $CONFIG_IDEDMA_PCI_AUTO
define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PCI
dep_bool ' ATA tagged command queueing (EXPERIMENTAL)' CONFIG_BLK_DEV_IDE_TCQ $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_EXPERIMENTAL
dep_bool ' ATA tagged command queueing (DANGEROUS)' CONFIG_BLK_DEV_IDE_TCQ $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_EXPERIMENTAL
dep_bool ' TCQ on by default' CONFIG_BLK_DEV_IDE_TCQ_DEFAULT $CONFIG_BLK_DEV_IDE_TCQ
if [ "$CONFIG_BLK_DEV_IDE_TCQ" != "n" ]; then
int ' Default queue depth' CONFIG_BLK_DEV_IDE_TCQ_DEPTH 32
......
......@@ -61,15 +61,18 @@
#define AEC_CABLEPINS_INPUT 0x10
static unsigned char aec_cyc2udma[9] = { 5, 5, 5, 4, 3, 2, 2, 1, 1 };
static unsigned char aec_cyc2act[16] = { 1, 1, 2, 3, 4, 5, 6, 0, 0, 7, 7, 7, 7, 7, 7, 7 };
static unsigned char aec_cyc2rec[16] = { 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 12, 13, 14 };
static unsigned char aec_cyc2act[16] =
{ 1, 1, 2, 3, 4, 5, 6, 0, 0, 7, 7, 7, 7, 7, 7, 7 };
static unsigned char aec_cyc2rec[16] =
{ 1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 0, 12, 13, 14 };
/*
* aec_set_speed_old() writes timing values to
* the chipset registers for ATP850UF
*/
static void aec_set_speed_old(struct pci_dev *dev, unsigned char dn, struct ata_timing *timing)
static void aec_set_speed_old(struct pci_dev *dev, unsigned char dn,
struct ata_timing *timing)
{
unsigned char t;
......@@ -90,19 +93,22 @@ static void aec_set_speed_old(struct pci_dev *dev, unsigned char dn, struct ata_
* other Artop chips
*/
static void aec_set_speed_new(struct pci_dev *dev, unsigned char dn, struct ata_timing *timing)
static void aec_set_speed_new(struct pci_dev *dev, unsigned char dn,
struct ata_timing *timing)
{
unsigned char t;
pci_write_config_byte(dev, AEC_DRIVE_TIMING + dn,
(aec_cyc2act[FIT(timing->active, 0, 15)] << 4)
(aec_cyc2act[FIT(timing->active, 0, 15)] <<
4)
| aec_cyc2rec[FIT(timing->recover, 0, 15)]);
pci_read_config_byte(dev, AEC_UDMA_NEW + (dn >> 1), &t);
t &= ~(0xf << ((dn & 1) << 2));
if (timing->udma) {
if (timing->udma >= 2)
t |= aec_cyc2udma[FIT(timing->udma, 2, 8)] << ((dn & 1) << 2);
t |= aec_cyc2udma[FIT(timing->udma, 2, 8)] <<
((dn & 1) << 2);
if (timing->mode == XFER_UDMA_5)
t |= 6;
if (timing->mode == XFER_UDMA_6)
......@@ -123,11 +129,14 @@ static int aec_set_drive(struct ata_device *drive, unsigned char speed)
int T, UT;
int aec_old;
aec_old = (drive->channel->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF);
aec_old =
(drive->channel->pci_dev->device ==
PCI_DEVICE_ID_ARTOP_ATP850UF);
if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
if (ide_config_drive_speed(drive, speed))
printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
printk(KERN_WARNING
"ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
drive->dn >> 1, drive->dn & 1);
T = 1000000000 / system_bus_speed;
......@@ -152,7 +161,9 @@ static int aec_set_drive(struct ata_device *drive, unsigned char speed)
static void aec62xx_tune_drive(struct ata_device *drive, unsigned char pio)
{
if (pio == 255) {
aec_set_drive(drive, ata_timing_mode(drive, XFER_PIO | XFER_EPIO));
aec_set_drive(drive,
ata_timing_mode(drive,
XFER_PIO | XFER_EPIO));
return;
}
......@@ -173,7 +184,10 @@ static int __init aec62xx_modes_map(struct ata_channel *ch)
case PCI_DEVICE_ID_ARTOP_ATP865:
/* Can't use these modes simultaneously,
based on which PLL clock was chosen. */
map |= inb (bmide + AEC_BM_STAT_PCH) & AEC_PLLCLK_ATA133 ? XFER_UDMA_133 : XFER_UDMA_100;
map |=
inb(bmide +
AEC_BM_STAT_PCH) & AEC_PLLCLK_ATA133 ?
XFER_UDMA_133 : XFER_UDMA_100;
case PCI_DEVICE_ID_ARTOP_ATP860R:
case PCI_DEVICE_ID_ARTOP_ATP860:
map |= XFER_UDMA_66;
......@@ -220,7 +234,8 @@ static unsigned int __init aec62xx_init_chipset(struct pci_dev *dev)
pci_write_config_byte(dev, AEC_IDE_ENABLE, t | 0x80);
#endif
/* switch cable detection pins to input-only. */
outb (inb (bmide + AEC_BM_STAT_SCH) | AEC_CABLEPINS_INPUT, bmide + AEC_BM_STAT_SCH);
outb(inb(bmide + AEC_BM_STAT_SCH) | AEC_CABLEPINS_INPUT,
bmide + AEC_BM_STAT_SCH);
}
/*
......@@ -274,7 +289,8 @@ static void __init aec62xx_init_channel(struct ata_channel *ch)
/*
* We allow the BM-DMA driver only work on enabled interfaces.
*/
static void __init aec62xx_init_dma(struct ata_channel *ch, unsigned long dmabase)
static void __init aec62xx_init_dma(struct ata_channel *ch,
unsigned long dmabase)
{
unsigned char t;
......@@ -286,50 +302,49 @@ static void __init aec62xx_init_dma(struct ata_channel *ch, unsigned long dmabas
/* module data table */
static struct ata_pci_device chipsets[] __initdata = {
{
vendor: PCI_VENDOR_ID_ARTOP,
device: PCI_DEVICE_ID_ARTOP_ATP850UF,
init_chipset: aec62xx_init_chipset,
init_channel: aec62xx_init_channel,
init_dma: aec62xx_init_dma,
enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
bootable: OFF_BOARD,
flags: ATA_F_SER | ATA_F_IRQ | ATA_F_DMA
.vendor = PCI_VENDOR_ID_ARTOP,
.device = PCI_DEVICE_ID_ARTOP_ATP850UF,
.init_chipset = aec62xx_init_chipset,
.init_channel = aec62xx_init_channel,
.init_dma = aec62xx_init_dma,
.enablebits = {{0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04}},
.bootable = OFF_BOARD,
.flags = ATA_F_SER | ATA_F_IRQ | ATA_F_DMA
},
{
vendor: PCI_VENDOR_ID_ARTOP,
device: PCI_DEVICE_ID_ARTOP_ATP860,
init_chipset: aec62xx_init_chipset,
init_channel: aec62xx_init_channel,
enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
bootable: NEVER_BOARD,
flags: ATA_F_IRQ | ATA_F_DMA
.vendor = PCI_VENDOR_ID_ARTOP,
.device = PCI_DEVICE_ID_ARTOP_ATP860,
.init_chipset = aec62xx_init_chipset,
.init_channel = aec62xx_init_channel,
.enablebits = {{0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04}},
.bootable = NEVER_BOARD,
.flags = ATA_F_IRQ | ATA_F_DMA
},
{
vendor: PCI_VENDOR_ID_ARTOP,
device: PCI_DEVICE_ID_ARTOP_ATP860R,
init_chipset: aec62xx_init_chipset,
init_channel: aec62xx_init_channel,
enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
bootable: OFF_BOARD,
flags: ATA_F_IRQ | ATA_F_DMA
},
.vendor = PCI_VENDOR_ID_ARTOP,
.device = PCI_DEVICE_ID_ARTOP_ATP860R,
.init_chipset = aec62xx_init_chipset,
.init_channel = aec62xx_init_channel,
.enablebits = {{0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04}},
.bootable = OFF_BOARD,
.flags = ATA_F_IRQ | ATA_F_DMA},
{
vendor: PCI_VENDOR_ID_ARTOP,
device: PCI_DEVICE_ID_ARTOP_ATP865,
init_chipset: aec62xx_init_chipset,
init_channel: aec62xx_init_channel,
enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
bootable: NEVER_BOARD,
flags: ATA_F_IRQ | ATA_F_DMA
.vendor = PCI_VENDOR_ID_ARTOP,
.device = PCI_DEVICE_ID_ARTOP_ATP865,
.init_chipset = aec62xx_init_chipset,
.init_channel = aec62xx_init_channel,
.enablebits = {{0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04}},
.bootable = NEVER_BOARD,
.flags = ATA_F_IRQ | ATA_F_DMA
},
{
vendor: PCI_VENDOR_ID_ARTOP,
device: PCI_DEVICE_ID_ARTOP_ATP865R,
init_chipset: aec62xx_init_chipset,
init_channel: aec62xx_init_channel,
enablebits: { {0x4a,0x02,0x02}, {0x4a,0x04,0x04} },
bootable: OFF_BOARD,
flags: ATA_F_IRQ | ATA_F_DMA
.vendor = PCI_VENDOR_ID_ARTOP,
.device = PCI_DEVICE_ID_ARTOP_ATP865R,
.init_chipset = aec62xx_init_chipset,
.init_channel = aec62xx_init_channel,
.enablebits = {{0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04}},
.bootable = OFF_BOARD,
.flags = ATA_F_IRQ | ATA_F_DMA
}
};
......
......@@ -46,7 +46,8 @@
/* port addresses for auto-detection */
#define ALI_NUM_PORTS 4
static int ports[ALI_NUM_PORTS] __initdata = { 0x074, 0x0f4, 0x034, 0x0e4 };
static int ports[ALI_NUM_PORTS] __initdata =
{ 0x074, 0x0f4, 0x034, 0x0e4 };
/* register initialization data */
struct reg_initializer {
......@@ -67,10 +68,14 @@ static struct reg_initializer init_data[] __initdata = {
static struct {
u8 reg1, reg2, reg3, reg4;
} reg_tab[4] = {
{ 0x03, 0x26, 0x04, 0x27 }, /* drive 0 */
{ 0x05, 0x28, 0x06, 0x29 }, /* drive 1 */
{ 0x2b, 0x30, 0x2c, 0x31 }, /* drive 2 */
{ 0x2d, 0x32, 0x2e, 0x33 }, /* drive 3 */
{
0x03, 0x26, 0x04, 0x27}, /* drive 0 */
{
0x05, 0x28, 0x06, 0x29}, /* drive 1 */
{
0x2b, 0x30, 0x2c, 0x31}, /* drive 2 */
{
0x2d, 0x32, 0x2e, 0x33}, /* drive 3 */
};
static int base_port; /* base port address */
......@@ -121,13 +126,16 @@ static void ali14xx_tune_drive(struct ata_device *drive, u8 pio)
time1 = t->cycle;
time2 = t->active;
param3 = param1 = (time2 * system_bus_speed + 999999) / 1000000;
param4 = param2 = (time1 * system_bus_speed + 999999) / 1000000 - param1;
param4 = param2 =
(time1 * system_bus_speed + 999999) / 1000000 - param1;
if (pio < XFER_PIO_3) {
param3 += 8;
param4 += 8;
}
printk(KERN_DEBUG "%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
drive->name, pio - XFER_PIO_0, time1, time2, param1, param2, param3, param4);
printk(KERN_DEBUG
"%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
drive->name, pio - XFER_PIO_0, time1, time2, param1, param2,
param3, param4);
/* stuff timing parameters into controller registers */
drive_num = (drive->channel->index << 1) + drive->select.b.unit;
......@@ -150,8 +158,7 @@ static int __init find_port(void)
int i;
unsigned long flags;
__save_flags(flags); /* local CPU only */
__cli(); /* local CPU only */
local_irq_save(flags);
for (i = 0; i < ALI_NUM_PORTS; i++) {
base_port = ports[i];
reg_off = inb(base_port);
......@@ -163,7 +170,7 @@ static int __init find_port(void)
data_port = base_port + 8;
t = in_reg(0) & 0xf0;
outb_p(reg_off, base_port);
__restore_flags(flags); /* local CPU only */
local_irq_restore(flags);
if (t != 0x50)
return 0;
return 1; /* success */
......@@ -171,7 +178,8 @@ static int __init find_port(void)
}
outb_p(reg_off, base_port);
}
__restore_flags(flags); /* local CPU only */
local_irq_restore(flags);
return 0;
}
......@@ -184,15 +192,15 @@ static int __init init_registers(void)
unsigned long flags;
u8 t;
__save_flags(flags); /* local CPU only */
__cli(); /* local CPU only */
local_irq_save(flags);
outb_p(reg_on, base_port);
for (p = init_data; p->reg != 0; ++p)
out_reg(p->data, p->reg);
outb_p(0x01, reg_port);
t = inb(reg_port) & 0x01;
outb_p(reg_off, base_port);
__restore_flags(flags); /* local CPU only */
local_irq_restore(flags);
return t;
}
......
......@@ -73,8 +73,8 @@ static void ali15x3_tune_drive(struct ata_device *drive, byte pio)
if (r_clc >= 16)
r_clc = 0;
}
__save_flags(flags);
__cli();
local_irq_save(flags);
/*
* PIO mode => ATA FIFO on, ATAPI FIFO off
......@@ -96,7 +96,8 @@ static void ali15x3_tune_drive(struct ata_device *drive, byte pio)
pci_write_config_byte(dev, port, s_clc);
pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
__restore_flags(flags);
local_irq_restore(flags);
}
static int ali15x3_tune_chipset(struct ata_device *drive, byte speed)
......@@ -216,8 +217,7 @@ static unsigned int __init ali15x3_ata66_check(struct ata_channel *hwif)
unsigned long flags;
byte tmpbyte;
__save_flags(flags);
__cli();
local_irq_save(flags);
if (m5229_revision >= 0xC2) {
/*
......@@ -297,9 +297,9 @@ static unsigned int __init ali15x3_ata66_check(struct ata_channel *hwif)
pci_write_config_byte(dev, 0x53, tmpbyte);
__restore_flags(flags);
local_irq_restore(flags);
return(ata66);
return (ata66);
}
static void __init ali15x3_init_channel(struct ata_channel *hwif)
......@@ -374,22 +374,22 @@ static void __init ali15x3_init_dma(struct ata_channel *ch, unsigned long dmabas
/* module data table */
static struct ata_pci_device chipsets[] __initdata = {
{
vendor: PCI_VENDOR_ID_AL,
device: PCI_DEVICE_ID_AL_M5219,
.vendor = PCI_VENDOR_ID_AL,
.device = PCI_DEVICE_ID_AL_M5219,
/* FIXME: Perhaps we should use the same init routines
* as below here. */
enablebits: { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
bootable: ON_BOARD,
flags: ATA_F_SIMPLEX
.enablebits = { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
.bootable = ON_BOARD,
.flags = ATA_F_SIMPLEX
},
{
vendor: PCI_VENDOR_ID_AL,
device: PCI_DEVICE_ID_AL_M5229,
init_chipset: ali15x3_init_chipset,
init_channel: ali15x3_init_channel,
init_dma: ali15x3_init_dma,
enablebits: { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
bootable: ON_BOARD
.vendor = PCI_VENDOR_ID_AL,
.device = PCI_DEVICE_ID_AL_M5229,
.init_chipset = ali15x3_init_chipset,
.init_channel = ali15x3_init_channel,
.init_dma = ali15x3_init_dma,
.enablebits = { {0x00,0x00,0x00}, {0x00,0x00,0x00} },
.bootable = ON_BOARD
}
};
......@@ -397,9 +397,8 @@ int __init init_ali15x3(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(chipsets); ++i) {
for (i = 0; i < ARRAY_SIZE(chipsets); ++i)
ata_register_chipset(&chipsets[i]);
}
return 0;
}
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......@@ -314,12 +314,12 @@ static void __init ide_init_cs5530(struct ata_channel *hwif)
/* module data table */
static struct ata_pci_device chipset __initdata = {
vendor: PCI_VENDOR_ID_CYRIX,
device: PCI_DEVICE_ID_CYRIX_5530_IDE,
init_chipset: pci_init_cs5530,
init_channel: ide_init_cs5530,
bootable: ON_BOARD,
flags: ATA_F_DMA
.vendor = PCI_VENDOR_ID_CYRIX,
.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
.init_chipset = pci_init_cs5530,
.init_channel = ide_init_cs5530,
.bootable = ON_BOARD,
.flags = ATA_F_DMA
};
int __init init_cs5530(void)
......
......@@ -426,12 +426,12 @@ static void __init ide_init_cy82c693(struct ata_channel *hwif)
/* module data table */
static struct ata_pci_device chipset __initdata = {
vendor: PCI_VENDOR_ID_CONTAQ,
device: PCI_DEVICE_ID_CONTAQ_82C693,
init_chipset: pci_init_cy82c693,
init_channel: ide_init_cy82c693,
bootable: ON_BOARD,
flags: ATA_F_DMA
.vendor = PCI_VENDOR_ID_CONTAQ,
.device = PCI_DEVICE_ID_CONTAQ_82C693,
.init_chipset = pci_init_cy82c693,
.init_channel = ide_init_cy82c693,
.bootable = ON_BOARD,
.flags = ATA_F_DMA
};
int __init init_cy82c693(void)
......
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