Commit f81f88f4 authored by Tom Rini's avatar Tom Rini

PPC32: Add and make use of ppc_md.rtc_{read,write}_val.

We can then fix IBM PReP machines and their RTCs.
parent 2130835d
......@@ -49,6 +49,7 @@
#include <asm/cache.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mc146818rtc.h>
#include <asm/mk48t59.h>
#include <asm/prep_nvram.h>
#include <asm/raven.h>
......@@ -1023,8 +1024,10 @@ prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.time_init = todc_time_init;
if (_prep_type == _PREP_IBM) {
TODC_INIT(TODC_TYPE_MC146818, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.rtc_read_val = todc_mc146818_read_val;
ppc_md.rtc_write_val = todc_mc146818_write_val;
TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1),
8);
} else {
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
......
......@@ -7,7 +7,7 @@
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -31,15 +31,13 @@
* 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
* 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
* set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
* address of the upper byte (leave NULL if using mv146818), and set
* address of the upper byte (leave NULL if using mc146818), and set
* 'nvram_data' to the address of the 8-bit data register.
*
* You also need to set 'ppc_md.nvram_read_val' and 'ppc_md.nvram_write_val' to
* the proper routines. There are standard ones defined further down in
* this file that you can use.
*
* There is a built in assumption that the RTC and NVRAM are accessed by the
* same mechanism (i.e., ppc_md.nvram_read_val, etc works for both).
* In order to break the assumption that the RTC and NVRAM are accessed by
* the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
* 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
* and 'ppc_md.rtc_write_val' will be used.
*
* Note: Even though the documentation for the various RTC chips say that it
* take up to a second before it starts updating once the 'R' bit is
......@@ -116,16 +114,15 @@ todc_m48txx_write_val(int addr, unsigned char val)
u_char
todc_mc146818_read_val(int addr)
{
outb(addr, todc_info->nvram_as0);
return inb(todc_info->nvram_data);
outb_p(addr, todc_info->nvram_as0);
return inb_p(todc_info->nvram_data);
}
void
todc_mc146818_write_val(int addr, unsigned char val)
{
outb(addr, todc_info->nvram_as0);
outb(val, todc_info->nvram_data);
return;
outb_p(addr, todc_info->nvram_as0);
outb_p(val, todc_info->nvram_data);
}
......@@ -143,16 +140,16 @@ todc_read_val(int addr)
if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
if (addr < todc_info->nvram_size) { /* NVRAM */
ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
val = ppc_md.nvram_read_val(todc_info->nvram_data_reg);
ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
}
else { /* Clock Reg */
addr -= todc_info->nvram_size;
val = ppc_md.nvram_read_val(addr);
val = ppc_md.rtc_read_val(addr);
}
}
else {
val = ppc_md.nvram_read_val(addr);
val = ppc_md.rtc_read_val(addr);
}
return val;
......@@ -163,16 +160,16 @@ todc_write_val(int addr, u_char val)
{
if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
if (addr < todc_info->nvram_size) { /* NVRAM */
ppc_md.nvram_write_val(todc_info->nvram_addr_reg, addr);
ppc_md.nvram_write_val(todc_info->nvram_data_reg, val);
ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
}
else { /* Clock Reg */
addr -= todc_info->nvram_size;
ppc_md.nvram_write_val(addr, val);
ppc_md.rtc_write_val(addr, val);
}
}
else {
ppc_md.nvram_write_val(addr, val);
ppc_md.rtc_write_val(addr, val);
}
}
......@@ -192,12 +189,13 @@ todc_write_val(int addr, u_char val)
long __init
todc_time_init(void)
{
static u_char not_initialized = 1;
/* Make sure clocks are running */
if (not_initialized) {
u_char cntl_b;
if (!ppc_md.rtc_read_val)
ppc_md.rtc_read_val = ppc_md.nvram_read_val;
if (!ppc_md.rtc_write_val)
ppc_md.rtc_write_val = ppc_md.nvram_write_val;
cntl_b = todc_read_val(todc_info->control_b);
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
......@@ -210,8 +208,7 @@ todc_time_init(void)
}
todc_write_val(todc_info->control_b, cntl_b);
}
else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
} else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
u_char mode;
mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
......@@ -221,8 +218,7 @@ todc_time_init(void)
mode |= 0x30;
todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
}
else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
} else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
u_char month;
todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
......@@ -240,8 +236,7 @@ todc_time_init(void)
cntl_b &= ~TODC_DS1501_CNTL_B_TE;
todc_write_val(todc_info->control_b, cntl_b);
}
else { /* must be a m48txx type */
} else { /* must be a m48txx type */
u_char cntl_a;
todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
......@@ -268,10 +263,6 @@ todc_time_init(void)
todc_write_val(todc_info->control_a, cntl_a);
}
not_initialized = 0;
}
return 0;
}
......
......@@ -43,6 +43,8 @@ struct machdep_calls {
long (*time_init)(void); /* Optional, may be NULL */
int (*set_rtc_time)(unsigned long nowtime);
unsigned long (*get_rtc_time)(void);
unsigned char (*rtc_read_val)(int addr);
void (*rtc_write_val)(int addr, unsigned char val);
void (*calibrate_decr)(void);
void (*heartbeat)(void);
......
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