Skip to content

L
linux
Commit f85f19de authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
  PCI: remove printks about disabled bridge windows
  PCI: fold pci_calc_resource_flags() into decode_bar()
  PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
  PCI: correct pcie_set_readrq write size
  PCI: pciehp: change wait time for valid configuration access
  x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
  PCI: ARI is a PCIe v2 feature
  x86/PCI: quirks: Use pci_dev->revision
  PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
  PCI hotplug: cpqphp: use pci_dev->vendor
  PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
  x86/PCI: config space accessor functions should not ignore the segment argument
  PCI: Assign values to 'pci_obff_signal_type' enumeration constants
  x86/PCI: reduce severity of host bridge window conflict warnings
  PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
  PCI: PCIe AER: add aer_recover_queue
  x86/PCI: select direct access mode for mmconfig option
  PCI hotplug: Rename is_ejectable which also exists in dock.c
parents b993fdbc 7b87c9df
Hide whitespace changes
Inline Side-by-side
Showing with 294 additions and 215 deletions
arch/alpha/kernel/sys_alcor.c
View file @ f85f19de
......@@ -183,7 +183,7 @@ alcor_init_irq(void)
*/
static int __init
alcor_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
alcor_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[7][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_cabriolet.c
View file @ f85f19de
......@@ -175,7 +175,7 @@ pc164_init_irq(void)
*/
static inline int __init
eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[5][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -205,7 +205,7 @@ eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
*/
static inline int __init
cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[5][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -289,7 +289,7 @@ cia_cab_init_pci(void)
*/
static inline int __init
alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[7][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_dp264.c
View file @ f85f19de
......@@ -382,7 +382,7 @@ isa_irq_fixup(struct pci_dev *dev, int irq)
}
static int __init
dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[6][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -404,7 +404,7 @@ dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
static int __init
monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[13][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -466,7 +466,7 @@ monet_swizzle(struct pci_dev *dev, u8 *pinp)
}
static int __init
webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[13][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -488,7 +488,7 @@ webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
static int __init
clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[7][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_eb64p.c
View file @ f85f19de
......@@ -169,7 +169,7 @@ eb64p_init_irq(void)
*/
static int __init
eb64p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
eb64p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[5][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_eiger.c
View file @ f85f19de
......@@ -144,7 +144,7 @@ eiger_init_irq(void)
}
static int __init
eiger_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u8 irq_orig;
......
arch/alpha/kernel/sys_marvel.c
View file @ f85f19de
......@@ -318,7 +318,7 @@ marvel_init_irq(void)
}
static int
marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pci_controller *hose = dev->sysdata;
struct io7_port *io7_port = hose->sysdata;
......
arch/alpha/kernel/sys_miata.c
View file @ f85f19de
......@@ -151,7 +151,7 @@ miata_init_irq(void)
*/
static int __init
miata_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
miata_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[18][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_mikasa.c
View file @ f85f19de
......@@ -146,7 +146,7 @@ mikasa_init_irq(void)
*/
static int __init
mikasa_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
mikasa_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[8][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_nautilus.c
View file @ f85f19de
......@@ -65,7 +65,7 @@ nautilus_init_irq(void)
}
static int __init
nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
/* Preserve the IRQ set up by the console. */
......
arch/alpha/kernel/sys_noritake.c
View file @ f85f19de
......@@ -194,7 +194,7 @@ noritake_init_irq(void)
*/
static int __init
noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
noritake_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[15][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_rawhide.c
View file @ f85f19de
......@@ -223,7 +223,7 @@ rawhide_init_irq(void)
*/
static int __init
rawhide_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
rawhide_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[5][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_ruffian.c
View file @ f85f19de
......@@ -119,7 +119,7 @@ ruffian_kill_arch (int mode)
*/
static int __init
ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[11][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_rx164.c
View file @ f85f19de
......@@ -144,7 +144,7 @@ rx164_init_irq(void)
*/
static int __init
rx164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
rx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
#if 0
static char irq_tab_pass1[6][5] __initdata = {
......
arch/alpha/kernel/sys_sable.c
View file @ f85f19de
......@@ -194,7 +194,7 @@ sable_init_irq(void)
*/
static int __init
sable_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[9][5] __initdata = {
/*INT INTA INTB INTC INTD */
......@@ -376,7 +376,7 @@ lynx_init_irq(void)
*/
static int __init
lynx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[19][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_sio.c
View file @ f85f19de
......@@ -146,7 +146,7 @@ sio_fixup_irq_levels(unsigned int level_bits)
}
static inline int __init
noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
/*
* The Noname board has 5 PCI slots with each of the 4
......@@ -185,7 +185,7 @@ noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
}
static inline int __init
p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[][5] __initdata = {
/*INT A B C D */
......
arch/alpha/kernel/sys_sx164.c
View file @ f85f19de
......@@ -95,7 +95,7 @@ sx164_init_irq(void)
*/
static int __init
sx164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
sx164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[5][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/alpha/kernel/sys_takara.c
View file @ f85f19de
......@@ -157,7 +157,7 @@ takara_init_irq(void)
*/
static int __init
takara_map_irq_srm(struct pci_dev *dev, u8 slot, u8 pin)
takara_map_irq_srm(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[15][5] __initdata = {
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
......@@ -188,7 +188,7 @@ takara_map_irq_srm(struct pci_dev *dev, u8 slot, u8 pin)
}
static int __init
takara_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
takara_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[15][5] __initdata = {
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
......
arch/alpha/kernel/sys_titan.c
View file @ f85f19de
......@@ -305,7 +305,7 @@ titan_late_init(void)
}
static int __devinit
titan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
titan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u8 intline;
int irq;
......
arch/alpha/kernel/sys_wildfire.c
View file @ f85f19de
......@@ -290,7 +290,7 @@ wildfire_device_interrupt(unsigned long vector)
*/
static int __init
wildfire_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
wildfire_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static char irq_tab[8][5] __initdata = {
/*INT INTA INTB INTC INTD */
......
arch/arm/common/it8152.c
View file @ f85f19de
......@@ -144,7 +144,7 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
}
/* mapping for on-chip devices */
int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
(dev->device == PCI_DEVICE_ID_ITE_8152)) {
......
arch/arm/include/asm/hardware/it8152.h
View file @ f85f19de
......@@ -105,7 +105,7 @@ struct pci_sys_data;
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
extern void it8152_init_irq(void);
extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
......
arch/arm/include/asm/mach/pci.h
View file @ f85f19de
......@@ -25,7 +25,7 @@ struct hw_pci {
void (*preinit)(void);
void (*postinit)(void);
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
};
/*
......@@ -44,7 +44,7 @@ struct pci_sys_data {
/* Bridge swizzling */
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
int (*map_irq)(struct pci_dev *, u8, u8);
int (*map_irq)(const struct pci_dev *, u8, u8);
struct hw_pci *hw;
void *private_data; /* platform controller private data */
};
......
arch/arm/kernel/bios32.c
View file @ f85f19de
......@@ -476,7 +476,7 @@ static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
/*
* Map a slot/pin to an IRQ.
*/
static int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pci_sys_data *sys = dev->sysdata;
int irq = -1;
......
arch/arm/mach-cns3xxx/pcie.c
View file @ f85f19de
......@@ -172,7 +172,7 @@ static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
}
static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
int irq = cnspci->irqs[slot];
......
arch/arm/mach-dove/pcie.c
View file @ f85f19de
......@@ -193,7 +193,7 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
return bus;
}
static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pcie_port *pp = bus_to_port(dev->bus->number);
......
arch/arm/mach-footbridge/cats-pci.c
View file @ f85f19de
......@@ -16,7 +16,7 @@
/* cats host-specific stuff */
static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
static int __init cats_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->irq >= 255)
return -1; /* not a valid interrupt. */
......
arch/arm/mach-footbridge/ebsa285-pci.c
View file @ f85f19de
......@@ -15,7 +15,7 @@
static int irqmap_ebsa285[] __initdata = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI };
static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
......
arch/arm/mach-footbridge/netwinder-pci.c
View file @ f85f19de
......@@ -17,7 +17,7 @@
* We now use the slot ID instead of the device identifiers to select
* which interrupt is routed where.
*/
static int __init netwinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
switch (slot) {
case 0: /* host bridge */
......
arch/arm/mach-footbridge/personal-pci.c
View file @ f85f19de
......@@ -18,7 +18,8 @@ static int irqmap_personal_server[] __initdata = {
IRQ_DOORBELLHOST, IRQ_DMA1, IRQ_DMA2, IRQ_PCI
};
static int __init personal_server_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
unsigned char line;
......
arch/arm/mach-integrator/pci.c
View file @ f85f19de
......@@ -95,7 +95,7 @@ static int irq_tab[4] __initdata = {
* map the specified device/slot/pin to an IRQ. This works out such
* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
*/
static int __init integrator_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int intnr = ((slot - 9) + (pin - 1)) & 3;
......
arch/arm/mach-iop13xx/iq81340mc.c
View file @ f85f19de
......@@ -30,7 +30,7 @@
extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
static int __init
iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
{
switch (idsel) {
case 1:
......
arch/arm/mach-iop13xx/pci.c
View file @ f85f19de
......@@ -388,7 +388,7 @@ static int iop13xx_atue_pci_status(int clear)
}
static int
iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel != 0);
......
arch/arm/mach-iop32x/em7210.c
View file @ f85f19de
......@@ -81,7 +81,7 @@ void __init em7210_map_io(void)
#define INTD IRQ_IOP32X_XINT3
static int __init
em7210_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[][4] = {
/*
......
arch/arm/mach-iop32x/glantank.c
View file @ f85f19de
......@@ -77,7 +77,7 @@ void __init glantank_map_io(void)
#define INTD IRQ_IOP32X_XINT3
static int __init
glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[][4] = {
/*
......
arch/arm/mach-iop32x/iq31244.c
View file @ f85f19de
......@@ -103,7 +103,7 @@ void __init iq31244_map_io(void)
* EP80219/IQ31244 PCI.
*/
static int __init
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......@@ -139,7 +139,7 @@ static struct hw_pci ep80219_pci __initdata = {
};
static int __init
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-iop32x/iq80321.c
View file @ f85f19de
......@@ -71,7 +71,7 @@ void __init iq80321_map_io(void)
* IQ80321 PCI.
*/
static int __init
iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-iop32x/n2100.c
View file @ f85f19de
......@@ -78,7 +78,7 @@ void __init n2100_map_io(void)
* N2100 PCI.
*/
static int __init
n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-iop33x/iq80331.c
View file @ f85f19de
......@@ -54,7 +54,7 @@ static struct sys_timer iq80331_timer = {
* IQ80331 PCI.
*/
static int __init
iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-iop33x/iq80332.c
View file @ f85f19de
......@@ -54,7 +54,7 @@ static struct sys_timer iq80332_timer = {
* IQ80332 PCI.
*/
static int __init
iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-ixp2000/enp2611.c
View file @ f85f19de
......@@ -148,7 +148,8 @@ static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys);
}
static int __init enp2611_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-ixp2000/ixdp2400.c
View file @ f85f19de
......@@ -78,7 +78,8 @@ int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys)
return 1;
}
static int __init ixdp2400_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
if (ixdp2x00_master_npu()) {
......
arch/arm/mach-ixp2000/ixdp2800.c
View file @ f85f19de
......@@ -161,7 +161,8 @@ static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
return 1;
}
static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
if (ixdp2x00_master_npu()) {
......
arch/arm/mach-ixp2000/ixdp2x01.c
View file @ f85f19de
......@@ -252,7 +252,8 @@ void __init ixdp2x01_pci_preinit(void)
#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
u8 bus = dev->bus->number;
u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
......
arch/arm/mach-ixp23xx/ixdp2351.c
View file @ f85f19de
......@@ -168,7 +168,7 @@ void __init ixdp2351_init_irq(void)
*/
#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u8 bus = dev->bus->number;
u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
......
arch/arm/mach-ixp23xx/roadrunner.c
View file @ f85f19de
......@@ -56,7 +56,8 @@
#define INTC_PIN IXP23XX_GPIO_PIN_11
#define INTD_PIN IXP23XX_GPIO_PIN_12
static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel,
u8 pin)
{
static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
......
arch/arm/mach-ixp4xx/avila-pci.c
View file @ f85f19de
......@@ -46,7 +46,7 @@ void __init avila_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init avila_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
......
arch/arm/mach-ixp4xx/coyote-pci.c
View file @ f85f19de
......@@ -37,7 +37,7 @@ void __init coyote_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init coyote_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == SLOT0_DEVID)
return IXP4XX_GPIO_IRQ(SLOT0_INTA);
......
arch/arm/mach-ixp4xx/dsmg600-pci.c
View file @ f85f19de
......@@ -44,7 +44,7 @@ void __init dsmg600_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
......
arch/arm/mach-ixp4xx/fsg-pci.c
View file @ f85f19de
......@@ -38,7 +38,7 @@ void __init fsg_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTC),
......
arch/arm/mach-ixp4xx/gateway7001-pci.c
View file @ f85f19de
......@@ -35,7 +35,8 @@ void __init gateway7001_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init gateway7001_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
if (slot == 1)
return IRQ_IXP4XX_GPIO11;
......
arch/arm/mach-ixp4xx/goramo_mlr.c
View file @ f85f19de
......@@ -462,7 +462,7 @@ static void __init gmlr_pci_postinit(void)
}
}
static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
switch(slot) {
case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
......
arch/arm/mach-ixp4xx/gtwx5715-pci.c
View file @ f85f19de
......@@ -49,7 +49,7 @@ void __init gtwx5715_pci_preinit(void)
}
static int __init gtwx5715_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int rc = -1;
......
arch/arm/mach-ixp4xx/ixdp425-pci.c
View file @ f85f19de
......@@ -43,7 +43,7 @@ void __init ixdp425_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init ixdp425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
......
arch/arm/mach-ixp4xx/ixdpg425-pci.c
View file @ f85f19de
......@@ -31,7 +31,7 @@ void __init ixdpg425_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init ixdpg425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 12 || slot == 13)
return IRQ_IXP4XX_GPIO7;
......
arch/arm/mach-ixp4xx/nas100d-pci.c
View file @ f85f19de
......@@ -41,7 +41,7 @@ void __init nas100d_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
......
arch/arm/mach-ixp4xx/nslu2-pci.c
View file @ f85f19de
......@@ -38,7 +38,7 @@ void __init nslu2_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[IRQ_LINES] = {
IXP4XX_GPIO_IRQ(INTA),
......
arch/arm/mach-ixp4xx/vulcan-pci.c
View file @ f85f19de
......@@ -43,7 +43,7 @@ void __init vulcan_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init vulcan_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 1)
return IXP4XX_GPIO_IRQ(INTA);
......
arch/arm/mach-ixp4xx/wg302v2-pci.c
View file @ f85f19de
......@@ -35,7 +35,7 @@ void __init wg302v2_pci_preinit(void)
ixp4xx_pci_preinit();
}
static int __init wg302v2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (slot == 1)
return IRQ_IXP4XX_GPIO8;
......
arch/arm/mach-kirkwood/pcie.c
View file @ f85f19de
......@@ -245,7 +245,8 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
return bus;
}
static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
struct pcie_port *pp = bus_to_port(dev->bus);
......
arch/arm/mach-ks8695/board-dsm320.c
View file @ f85f19de
......@@ -34,7 +34,7 @@
#include "generic.h"
#ifdef CONFIG_PCI
static int dsm320_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int dsm320_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
switch (slot) {
case 0:
......
arch/arm/mach-ks8695/board-micrel.c
View file @ f85f19de
......@@ -24,7 +24,7 @@
#include "generic.h"
#ifdef CONFIG_PCI
static int micrel_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int micrel_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return KS8695_IRQ_EXTERN0;
}
......
arch/arm/mach-ks8695/include/mach/devices.h
View file @ f85f19de
......@@ -30,7 +30,7 @@ extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
struct ks8695_pci_cfg {
short mode;
int (*map_irq)(struct pci_dev *, u8, u8);
int (*map_irq)(const struct pci_dev *, u8, u8);
};
extern __init void ks8695_init_pci(struct ks8695_pci_cfg *);
......
arch/arm/mach-mv78xx0/pcie.c
View file @ f85f19de
......@@ -260,7 +260,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
return bus;
}
static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
struct pcie_port *pp = bus_to_port(dev->bus->number);
......
arch/arm/mach-orion5x/common.h
View file @ f85f19de
......@@ -51,7 +51,7 @@ void orion5x_pci_disable(void);
void orion5x_pci_set_cardbus_mode(void);
int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
struct machine_desc;
struct meminfo;
......
arch/arm/mach-orion5x/db88f5281-setup.c
View file @ f85f19de
......@@ -237,7 +237,8 @@ void __init db88f5281_pci_preinit(void)
}
}
static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/dns323-setup.c
View file @ f85f19de
......@@ -70,14 +70,14 @@ enum {
* PCI setup
*/
static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
/*
* Check for devices with hard-wired IRQs.
*/
irq = orion5x_pci_map_irq(dev, slot, pin);
irq = orion5x_pci_map_irq(const dev, slot, pin);
if (irq != -1)
return irq;
......
arch/arm/mach-orion5x/kurobox_pro-setup.c
View file @ f85f19de
......@@ -119,7 +119,8 @@ static struct platform_device kurobox_pro_nor_flash = {
* PCI
****************************************************************************/
static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/mss2-setup.c
View file @ f85f19de
......@@ -73,7 +73,7 @@ static struct platform_device mss2_nor_flash = {
/****************************************************************************
* PCI setup
****************************************************************************/
static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/pci.c
View file @ f85f19de
......@@ -589,7 +589,7 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
return bus;
}
int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int bus = dev->bus->number;
......
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
View file @ f85f19de
......@@ -131,7 +131,7 @@ static void __init rd88f5181l_fxo_init(void)
}
static int __init
rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
View file @ f85f19de
......@@ -140,7 +140,7 @@ static void __init rd88f5181l_ge_init(void)
}
static int __init
rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/rd88f5182-setup.c
View file @ f85f19de
......@@ -172,7 +172,8 @@ void __init rd88f5182_pci_preinit(void)
}
}
static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/terastation_pro2-setup.c
View file @ f85f19de
......@@ -100,7 +100,7 @@ void __init tsp2_pci_preinit(void)
}
}
static int __init tsp2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/ts209-setup.c
View file @ f85f19de
......@@ -143,7 +143,8 @@ void __init qnap_ts209_pci_preinit(void)
}
}
static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/ts409-setup.c
View file @ f85f19de
......@@ -121,7 +121,8 @@ static struct platform_device qnap_ts409_nor_flash = {
* PCI
****************************************************************************/
static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/wnr854t-setup.c
View file @ f85f19de
......@@ -133,7 +133,8 @@ static void __init wnr854t_init(void)
platform_device_register(&wnr854t_nor_flash);
}
static int __init wnr854t_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-orion5x/wrt350n-v2-setup.c
View file @ f85f19de
......@@ -221,7 +221,8 @@ static void __init wrt350n_v2_init(void)
platform_device_register(&wrt350n_v2_button_device);
}
static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
int irq;
......
arch/arm/mach-pxa/cm-x2xx-pci.c
View file @ f85f19de
......@@ -77,7 +77,7 @@ void cmx2xx_pci_resume(void) {}
#endif
/* PCI IRQ mapping*/
static int __init cmx2xx_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init cmx2xx_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/arm/mach-sa1100/pci-nanoengine.c
View file @ f85f19de
......@@ -122,7 +122,8 @@ static struct pci_ops pci_nano_ops = {
.write = nanoengine_write_config,
};
static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
return NANOENGINE_IRQ_GPIO_PCI;
}
......
arch/arm/mach-shark/pci.c
View file @ f85f19de
......@@ -14,7 +14,7 @@
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
static int __init shark_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->bus->number == 0)
if (dev->devfn == 0)
......
arch/arm/mach-tegra/pcie.c
View file @ f85f19de
......@@ -449,7 +449,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
return 1;
}
static int tegra_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
return INT_PCIE_INTR;
}
......
arch/arm/mach-versatile/pci.c
View file @ f85f19de
......@@ -328,7 +328,7 @@ void __init pci_versatile_preinit(void)
/*
* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
*/
static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
int devslot = PCI_SLOT(dev->devfn);
......
arch/sh/drivers/pci/fixups-cayman.c
View file @ f85f19de
......@@ -5,7 +5,7 @@
#include <cpu/irq.h>
#include "pci-sh5.h"
int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int result = -1;
......
arch/sh/drivers/pci/fixups-dreamcast.c
View file @ f85f19de
......@@ -64,7 +64,7 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, gapspci_fixup_resources);
int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
/*
* The interrupt routing semantics here are quite trivial.
......
arch/sh/drivers/pci/fixups-landisk.c
View file @ f85f19de
......@@ -19,7 +19,7 @@
#define PCIMCR_MRSET_OFF 0xBFFFFFFF
#define PCIMCR_RFSH_OFF 0xFFFFFFFB
int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
/*
* slot0: pin1-4 = irq5,6,7,8
......
arch/sh/drivers/pci/fixups-r7780rp.c
View file @ f85f19de
......@@ -18,7 +18,7 @@ static char irq_tab[] __initdata = {
65, 66, 67, 68,
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
return irq_tab[slot];
}
arch/sh/drivers/pci/fixups-rts7751r2d.c
View file @ f85f19de
......@@ -31,7 +31,7 @@ static char lboxre2_irq_tab[] __initdata = {
IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
if (mach_is_lboxre2())
return lboxre2_irq_tab[slot];
......
arch/sh/drivers/pci/fixups-sdk7780.c
View file @ f85f19de
......@@ -27,7 +27,7 @@ static char sdk7780_irq_tab[4][16] __initdata = {
{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
return sdk7780_irq_tab[pin-1][slot];
}
arch/sh/drivers/pci/fixups-se7751.c
View file @ f85f19de
......@@ -6,7 +6,7 @@
#include <linux/io.h>
#include "pci-sh4.h"
int __init pcibios_map_platform_irq(struct pci_dev *, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *, u8 slot, u8 pin)
{
switch (slot) {
case 0: return 13;
......
arch/sh/drivers/pci/fixups-sh03.c
View file @ f85f19de
......@@ -3,7 +3,7 @@
#include <linux/types.h>
#include <linux/pci.h>
int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
......
arch/sh/drivers/pci/fixups-snapgear.c
View file @ f85f19de
......@@ -18,7 +18,7 @@
#include <linux/pci.h>
#include "pci-sh4.h"
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
int irq = -1;
......
arch/sh/drivers/pci/fixups-titan.c
View file @ f85f19de
......@@ -27,7 +27,7 @@ static char titan_irq_tab[] __initdata = {
TITAN_IRQ_USB,
};
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
int irq = titan_irq_tab[slot];
......
arch/sh/drivers/pci/pcie-sh7786.c
View file @ f85f19de
......@@ -466,7 +466,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
return 0;
}
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
{
return 71;
}
......
arch/sh/include/asm/pci.h
View file @ f85f19de
......@@ -112,7 +112,7 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
#endif
/* Board-specific fixup routines. */
int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern void pcibios_resource_to_bus(struct pci_dev *dev,
struct pci_bus_region *region, struct resource *res);
......
arch/sparc/include/asm/leon_pci.h
View file @ f85f19de
......@@ -12,7 +12,7 @@ struct leon_pci_info {
struct pci_ops *ops;
struct resource io_space;
struct resource mem_space;
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
};
extern void leon_pci_init(struct platform_device *ofdev,
......
arch/sparc/kernel/leon_pci_grpci2.c
View file @ f85f19de
......@@ -215,7 +215,7 @@ struct grpci2_priv {
DEFINE_SPINLOCK(grpci2_dev_lock);
struct grpci2_priv *grpci2priv;
int grpci2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct grpci2_priv *priv = dev->bus->sysdata;
int irq_group;
......
arch/tile/kernel/pci.c
View file @ f85f19de
......@@ -228,7 +228,7 @@ int __devinit tile_pci_init(void)
* (pin - 1) converts from the PCI standard's [1:4] convention to
* a normal [0:3] range.
*/
static int tile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct pci_controller *controller =
(struct pci_controller *)dev->sysdata;
......
arch/unicore32/kernel/pci.c
View file @ f85f19de
......@@ -102,7 +102,7 @@ void pci_puv3_preinit(void)
writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
}
static int __init pci_puv3_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->bus->number == 0) {
#ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
......
arch/x86/Kconfig
View file @ f85f19de
......@@ -1905,7 +1905,7 @@ config PCI_BIOS
# x86-64 doesn't support PCI BIOS access from long mode so always go direct.
config PCI_DIRECT
def_bool y
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC))
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC || PCI_GOMMCONFIG))
config PCI_MMCONFIG
def_bool y
......
arch/x86/pci/acpi.c
View file @ f85f19de
......@@ -246,10 +246,9 @@ static void add_resources(struct pci_root_info *info)
conflict = insert_resource_conflict(root, res);
if (conflict)
dev_err(&info->bridge->dev,
"address space collision: host bridge window %pR "
"conflicts with %s %pR\n",
res, conflict->name, conflict);
dev_info(&info->bridge->dev,
"ignoring host bridge window %pR (conflicts with %s %pR)\n",
res, conflict->name, conflict);
else
pci_bus_add_resource(info->bus, res, 0);
}
......
arch/x86/pci/ce4100.c
View file @ f85f19de
......@@ -257,6 +257,7 @@ static int ce4100_conf_read(unsigned int seg, unsigned int bus,
{
int i;
WARN_ON(seg);
if (bus == 1) {
for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
if (bus1_fixups[i].dev_func == devfn &&
......@@ -282,6 +283,7 @@ static int ce4100_conf_write(unsigned int seg, unsigned int bus,
{
int i;
WARN_ON(seg);
if (bus == 1) {
for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
if (bus1_fixups[i].dev_func == devfn &&
......
arch/x86/pci/common.c
View file @ f85f19de
......@@ -246,13 +246,6 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
},
},
#endif /* __i386__ */
{
.callback = find_sort_method,
.ident = "Dell System",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
},
},
{
.callback = set_bf_sort,
.ident = "Dell PowerEdge 1950",
......@@ -293,6 +286,13 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
},
},
{
.callback = find_sort_method,
.ident = "Dell System",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
},
},
{
.callback = set_bf_sort,
.ident = "HP ProLiant BL20p G3",
......
arch/x86/pci/direct.c
View file @ f85f19de
......@@ -22,7 +22,7 @@ static int pci_conf1_read(unsigned int seg, unsigned int bus,
{
unsigned long flags;
if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
*value = -1;
return -EINVAL;
}
......@@ -53,7 +53,7 @@ static int pci_conf1_write(unsigned int seg, unsigned int bus,
{
unsigned long flags;
if ((bus > 255) || (devfn > 255) || (reg > 4095))
if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
return -EINVAL;
raw_spin_lock_irqsave(&pci_config_lock, flags);
......@@ -97,6 +97,7 @@ static int pci_conf2_read(unsigned int seg, unsigned int bus,
unsigned long flags;
int dev, fn;
WARN_ON(seg);
if ((bus > 255) || (devfn > 255) || (reg > 255)) {
*value = -1;
return -EINVAL;
......@@ -138,6 +139,7 @@ static int pci_conf2_write(unsigned int seg, unsigned int bus,
unsigned long flags;
int dev, fn;
WARN_ON(seg);
if ((bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
......
arch/x86/pci/numaq_32.c
View file @ f85f19de
......@@ -34,6 +34,7 @@ static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
unsigned long flags;
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
WARN_ON(seg);
if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
return -EINVAL;
......@@ -73,6 +74,7 @@ static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
unsigned long flags;
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
WARN_ON(seg);
if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
return -EINVAL;
......
arch/x86/pci/olpc.c
View file @ f85f19de
......@@ -206,6 +206,8 @@ static int pci_olpc_read(unsigned int seg, unsigned int bus,
{
uint32_t *addr;
WARN_ON(seg);
/* Use the hardware mechanism for non-simulated devices */
if (!is_simulated(bus, devfn))
return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
......@@ -264,6 +266,8 @@ static int pci_olpc_read(unsigned int seg, unsigned int bus,
static int pci_olpc_write(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, uint32_t value)
{
WARN_ON(seg);
/* Use the hardware mechanism for non-simulated devices */
if (!is_simulated(bus, devfn))
return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
......
arch/x86/pci/pcbios.c
View file @ f85f19de
......@@ -181,6 +181,7 @@ static int pci_bios_read(unsigned int seg, unsigned int bus,
unsigned long flags;
unsigned long bx = (bus << 8) | devfn;
WARN_ON(seg);
if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
......@@ -247,6 +248,7 @@ static int pci_bios_write(unsigned int seg, unsigned int bus,
unsigned long flags;
unsigned long bx = (bus << 8) | devfn;
WARN_ON(seg);
if ((bus > 255) || (devfn > 255) || (reg > 255))
return -EINVAL;
......
arch/x86/pci/visws.c
View file @ f85f19de
......@@ -24,7 +24,7 @@ static void pci_visws_disable_irq(struct pci_dev *dev) { }
unsigned int pci_bus0, pci_bus1;
static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq, bus = dev->bus->number;
......
drivers/pci/hotplug/acpi_pcihp.c
View file @ f85f19de
......@@ -408,7 +408,7 @@ int acpi_get_hp_hw_control_from_firmware(struct pci_dev *pdev, u32 flags)
}
EXPORT_SYMBOL(acpi_get_hp_hw_control_from_firmware);
static int is_ejectable(acpi_handle handle)
static int pcihp_is_ejectable(acpi_handle handle)
{
acpi_status status;
acpi_handle tmp;
......@@ -442,7 +442,7 @@ int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle)
return 0;
if (bridge_handle != parent_handle)
return 0;
return is_ejectable(handle);
return pcihp_is_ejectable(handle);
}
EXPORT_SYMBOL_GPL(acpi_pci_check_ejectable);
......@@ -450,7 +450,7 @@ static acpi_status
check_hotplug(acpi_handle handle, u32 lvl, void *context, void **rv)
{
int *found = (int *)context;
if (is_ejectable(handle)) {
if (pcihp_is_ejectable(handle)) {
*found = 1;
return AE_CTRL_TERMINATE;
}
......
drivers/pci/hotplug/cpqphp_core.c
View file @ f85f19de
......@@ -840,8 +840,9 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
/* Need to read VID early b/c it's used to differentiate CPQ and INTC
* discovery
*/
rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
if (rc || ((vendor_id != PCI_VENDOR_ID_COMPAQ) && (vendor_id != PCI_VENDOR_ID_INTEL))) {
vendor_id = pdev->vendor;
if ((vendor_id != PCI_VENDOR_ID_COMPAQ) &&
(vendor_id != PCI_VENDOR_ID_INTEL)) {
err(msg_HPC_non_compaq_or_intel);
rc = -ENODEV;
goto err_disable_device;
......@@ -868,11 +869,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
/* TODO: This code can be made to support non-Compaq or Intel
* subsystem IDs
*/
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
if (rc) {
err("%s : pci_read_config_word failed\n", __func__);
goto err_disable_device;
}
subsystem_vid = pdev->subsystem_vendor;
dbg("Subsystem Vendor ID: %x\n", subsystem_vid);
if ((subsystem_vid != PCI_VENDOR_ID_COMPAQ) && (subsystem_vid != PCI_VENDOR_ID_INTEL)) {
err(msg_HPC_non_compaq_or_intel);
......@@ -887,11 +884,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_disable_device;
}
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsystem_deviceid);
if (rc) {
err("%s : pci_read_config_word failed\n", __func__);
goto err_free_ctrl;
}
subsystem_deviceid = pdev->subsystem_device;
info("Hot Plug Subsystem Device ID: %x\n", subsystem_deviceid);
......
drivers/pci/hotplug/pciehp_ctrl.c
View file @ f85f19de
......@@ -213,6 +213,9 @@ static int board_added(struct slot *p_slot)
goto err_exit;
}
/* Wait for 1 second after checking link training status */
msleep(1000);
/* Check for a power fault */
if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
......
drivers/pci/hotplug/pciehp_hpc.c
View file @ f85f19de
......@@ -275,16 +275,9 @@ int pciehp_check_link_status(struct controller *ctrl)
* hot-plug capable downstream port. But old controller might
* not implement it. In this case, we wait for 1000 ms.
*/
if (ctrl->link_active_reporting){
/* Wait for Data Link Layer Link Active bit to be set */
if (ctrl->link_active_reporting)
pcie_wait_link_active(ctrl);
/*
* We must wait for 100 ms after the Data Link Layer
* Link Active bit reads 1b before initiating a
* configuration access to the hot added device.
*/
msleep(100);
} else
else
msleep(1000);
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
......
drivers/pci/pci.c
View file @ f85f19de
......@@ -1905,7 +1905,7 @@ void pci_enable_ari(struct pci_dev *dev)
{
int pos;
u32 cap;
u16 ctrl;
u16 flags, ctrl;
struct pci_dev *bridge;
if (!pci_is_pcie(dev) || dev->devfn)
......@@ -1923,6 +1923,11 @@ void pci_enable_ari(struct pci_dev *dev)
if (!pos)
return;
/* ARI is a PCIe v2 feature */
pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
if ((flags & PCI_EXP_FLAGS_VERS) < 2)
return;
pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
if (!(cap & PCI_EXP_DEVCAP2_ARI))
return;
......@@ -3186,7 +3191,7 @@ EXPORT_SYMBOL(pcie_get_readrq);
* @rq: maximum memory read count in bytes
* valid values are 128, 256, 512, 1024, 2048, 4096
*
* If possible sets maximum read byte count
* If possible sets maximum memory read request in bytes
*/
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
......@@ -3209,7 +3214,7 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
ctl &= ~PCI_EXP_DEVCTL_READRQ;
ctl |= v;
err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
}
out:
......
drivers/pci/pcie/aer/aerdrv_core.c
View file @ f85f19de
......@@ -24,6 +24,7 @@
#include <linux/suspend.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/kfifo.h>
#include "aerdrv.h"
static int forceload;
......@@ -445,8 +446,7 @@ static struct pcie_port_service_driver *find_aer_service(struct pci_dev *dev)
return drv;
}
static pci_ers_result_t reset_link(struct pcie_device *aerdev,
struct pci_dev *dev)
static pci_ers_result_t reset_link(struct pci_dev *dev)
{
struct pci_dev *udev;
pci_ers_result_t status;
......@@ -486,7 +486,6 @@ static pci_ers_result_t reset_link(struct pcie_device *aerdev,
/**
* do_recovery - handle nonfatal/fatal error recovery process
* @aerdev: pointer to a pcie_device data structure of root port
* @dev: pointer to a pci_dev data structure of agent detecting an error
* @severity: error severity type
*
......@@ -494,8 +493,7 @@ static pci_ers_result_t reset_link(struct pcie_device *aerdev,
* error detected message to all downstream drivers within a hierarchy in
* question and return the returned code.
*/
static void do_recovery(struct pcie_device *aerdev, struct pci_dev *dev,
int severity)
static void do_recovery(struct pci_dev *dev, int severity)
{
pci_ers_result_t status, result = PCI_ERS_RESULT_RECOVERED;
enum pci_channel_state state;
......@@ -511,7 +509,7 @@ static void do_recovery(struct pcie_device *aerdev, struct pci_dev *dev,
report_error_detected);
if (severity == AER_FATAL) {
result = reset_link(aerdev, dev);
result = reset_link(dev);
if (result != PCI_ERS_RESULT_RECOVERED)
goto failed;
}
......@@ -576,9 +574,73 @@ static void handle_error_source(struct pcie_device *aerdev,
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
info->status);
} else
do_recovery(aerdev, dev, info->severity);
do_recovery(dev, info->severity);
}
#ifdef CONFIG_ACPI_APEI_PCIEAER
static void aer_recover_work_func(struct work_struct *work);
#define AER_RECOVER_RING_ORDER 4
#define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
struct aer_recover_entry
{
u8 bus;
u8 devfn;
u16 domain;
int severity;
};
static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
AER_RECOVER_RING_SIZE);
/*
* Mutual exclusion for writers of aer_recover_ring, reader side don't
* need lock, because there is only one reader and lock is not needed
* between reader and writer.
*/
static DEFINE_SPINLOCK(aer_recover_ring_lock);
static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
int severity)
{
unsigned long flags;
struct aer_recover_entry entry = {
.bus = bus,
.devfn = devfn,
.domain = domain,
.severity = severity,
};
spin_lock_irqsave(&aer_recover_ring_lock, flags);
if (kfifo_put(&aer_recover_ring, &entry))
schedule_work(&aer_recover_work);
else
pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
spin_unlock_irqrestore(&aer_recover_ring_lock, flags);
}
EXPORT_SYMBOL_GPL(aer_recover_queue);
static void aer_recover_work_func(struct work_struct *work)
{
struct aer_recover_entry entry;
struct pci_dev *pdev;
while (kfifo_get(&aer_recover_ring, &entry)) {
pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
entry.devfn);
if (!pdev) {
pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
entry.domain, entry.bus,
PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
continue;
}
do_recovery(pdev, entry.severity);
}
}
#endif
/**
* get_device_error_info - read error status from dev and store it to info
* @dev: pointer to the device expected to have a error record
......
drivers/pci/pcie/aer/aerdrv_errprint.c
View file @ f85f19de
......@@ -204,7 +204,7 @@ void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
}
#ifdef CONFIG_ACPI_APEI_PCIEAER
static int cper_severity_to_aer(int cper_severity)
int cper_severity_to_aer(int cper_severity)
{
switch (cper_severity) {
case CPER_SEV_RECOVERABLE:
......@@ -215,6 +215,7 @@ static int cper_severity_to_aer(int cper_severity)
return AER_CORRECTABLE;
}
}
EXPORT_SYMBOL_GPL(cper_severity_to_aer);
void cper_print_aer(const char *prefix, int cper_severity,
struct aer_capability_regs *aer)
......
drivers/pci/probe.c
View file @ f85f19de
......@@ -68,21 +68,6 @@ static int __init pcibus_class_init(void)
}
postcore_initcall(pcibus_class_init);
/*
* Translate the low bits of the PCI base
* to the resource type
*/
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
{
if (flags & PCI_BASE_ADDRESS_SPACE_IO)
return IORESOURCE_IO;
if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
return IORESOURCE_MEM | IORESOURCE_PREFETCH;
return IORESOURCE_MEM;
}
static u64 pci_size(u64 base, u64 maxbase, u64 mask)
{
u64 size = mask & maxbase; /* Find the significant bits */
......@@ -101,18 +86,39 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
return size;
}
static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
{
u32 mem_type;
unsigned long flags;
if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
return pci_bar_io;
flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
flags |= IORESOURCE_IO;
return flags;
}
res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
flags |= IORESOURCE_MEM;
if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
flags |= IORESOURCE_PREFETCH;
if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
return pci_bar_mem64;
return pci_bar_mem32;
mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
switch (mem_type) {
case PCI_BASE_ADDRESS_MEM_TYPE_32:
break;
case PCI_BASE_ADDRESS_MEM_TYPE_1M:
dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
break;
case PCI_BASE_ADDRESS_MEM_TYPE_64:
flags |= IORESOURCE_MEM_64;
break;
default:
dev_warn(&dev->dev,
"mem unknown type %x treated as 32-bit BAR\n",
mem_type);
break;
}
return flags;
}
/**
......@@ -165,9 +171,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
l = 0;
if (type == pci_bar_unknown) {
type = decode_bar(res, l);
res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
if (type == pci_bar_io) {
res->flags = decode_bar(dev, l);
res->flags |= IORESOURCE_SIZEALIGN;
if (res->flags & IORESOURCE_IO) {
l &= PCI_BASE_ADDRESS_IO_MASK;
mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
} else {
......@@ -180,7 +186,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
mask = (u32)PCI_ROM_ADDRESS_MASK;
}
if (type == pci_bar_mem64) {
if (res->flags & IORESOURCE_MEM_64) {
u64 l64 = l;
u64 sz64 = sz;
u64 mask64 = mask | (u64)~0 << 32;
......@@ -204,7 +210,6 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
goto fail;
}
res->flags |= IORESOURCE_MEM_64;
if ((sizeof(resource_size_t) < 8) && l) {
/* Address above 32-bit boundary; disable the BAR */
pci_write_config_dword(dev, pos, 0);
......@@ -230,7 +235,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
}
out:
return (type == pci_bar_mem64) ? 1 : 0;
return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
fail:
res->flags = 0;
goto out;
......@@ -284,10 +289,6 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child)
if (!res->end)
res->end = limit + 0xfff;
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
} else {
dev_printk(KERN_DEBUG, &dev->dev,
" bridge window [io %#06lx-%#06lx] (disabled)\n",
base, limit);
}
}
......@@ -308,10 +309,6 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
res->start = base;
res->end = limit + 0xfffff;
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
} else {
dev_printk(KERN_DEBUG, &dev->dev,
" bridge window [mem %#010lx-%#010lx] (disabled)\n",
base, limit + 0xfffff);
}
}
......@@ -359,10 +356,6 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
res->start = base;
res->end = limit + 0xfffff;
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
} else {
dev_printk(KERN_DEBUG, &dev->dev,
" bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
base, limit + 0xfffff);
}
}
......@@ -725,12 +718,14 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
pci_write_config_word(dev, PCI_STATUS, 0xffff);
/* Prevent assigning a bus number that already exists.
* This can happen when a bridge is hot-plugged */
if (pci_find_bus(pci_domain_nr(bus), max+1))
goto out;
child = pci_add_new_bus(bus, dev, ++max);
if (!child)
goto out;
* This can happen when a bridge is hot-plugged, so in
* this case we only re-scan this bus. */
child = pci_find_bus(pci_domain_nr(bus), max+1);
if (!child) {
child = pci_add_new_bus(bus, dev, ++max);
if (!child)
goto out;
}
buses = (buses & 0xff000000)
| ((unsigned int)(child->primary) << 0)
| ((unsigned int)(child->secondary) << 8)
......
drivers/pci/setup-bus.c
View file @ f85f19de
......@@ -336,7 +336,6 @@ static void pci_setup_bridge_io(struct pci_bus *bus)
/* Clear upper 16 bits of I/O base/limit. */
io_upper16 = 0;
l = 0x00f0;
dev_info(&bridge->dev, " bridge window [io disabled]\n");
}
/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
......@@ -362,7 +361,6 @@ static void pci_setup_bridge_mmio(struct pci_bus *bus)
dev_info(&bridge->dev, " bridge window %pR\n", res);
} else {
l = 0x0000fff0;
dev_info(&bridge->dev, " bridge window [mem disabled]\n");
}
pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
}
......@@ -393,7 +391,6 @@ static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
dev_info(&bridge->dev, " bridge window %pR\n", res);
} else {
l = 0x0000fff0;
dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
}
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
......
drivers/pci/setup-irq.c
View file @ f85f19de
......@@ -21,7 +21,7 @@
static void __init
pdev_fixup_irq(struct pci_dev *dev,
u8 (*swizzle)(struct pci_dev *, u8 *),
int (*map_irq)(struct pci_dev *, u8, u8))
int (*map_irq)(const struct pci_dev *, u8, u8))
{
u8 pin, slot;
int irq = 0;
......@@ -56,7 +56,7 @@ pdev_fixup_irq(struct pci_dev *dev,
void __init
pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
int (*map_irq)(struct pci_dev *, u8, u8))
int (*map_irq)(const struct pci_dev *, u8, u8))
{
struct pci_dev *dev = NULL;
for_each_pci_dev(dev)
......
drivers/pci/setup-res.c
View file @ f85f19de
......@@ -74,8 +74,7 @@ void pci_update_resource(struct pci_dev *dev, int resno)
resno, new, check);
}
if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
if (res->flags & IORESOURCE_MEM_64) {
new = region.start >> 16 >> 16;
pci_write_config_dword(dev, reg + 4, new);
pci_read_config_dword(dev, reg + 4, &check);
......
include/linux/aer.h
View file @ f85f19de
......@@ -51,5 +51,8 @@ static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
extern void cper_print_aer(const char *prefix, int cper_severity,
struct aer_capability_regs *aer);
extern int cper_severity_to_aer(int cper_severity);
extern void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
int severity);
#endif //_AER_H_
include/linux/pci.h
View file @ f85f19de
......@@ -843,8 +843,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type);
void pci_disable_ido(struct pci_dev *dev, unsigned long type);
enum pci_obff_signal_type {
PCI_EXP_OBFF_SIGNAL_L0,
PCI_EXP_OBFF_SIGNAL_ALWAYS,
PCI_EXP_OBFF_SIGNAL_L0 = 0,
PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
};
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
void pci_disable_obff(struct pci_dev *dev);
......@@ -879,7 +879,7 @@ void pdev_enable_device(struct pci_dev *);
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
int pci_enable_resources(struct pci_dev *, int mask);
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
int (*)(struct pci_dev *, u8, u8));
int (*)(const struct pci_dev *, u8, u8));
#define HAVE_PCI_REQ_REGIONS 2
int __must_check pci_request_regions(struct pci_dev *, const char *);
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7