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Commit f8d18d5c authored by Wambui Karuga's avatar Wambui Karuga Committed by Jani Nikula
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drm/i915/pm: use new struct drm_device logging macros. 

This converts various instances of the struct device and printk based
logging macros with the new struct drm_device based logging macros in
i915/intel_pm.c
Signed-off-by: default avatarWambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/8721848f7bcf8b0c3a33969d07e331bb372bd51a.1578409433.git.wambui.karugax@gmail.com
parent 0f69958d
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Showing with 194 additions and 157 deletions
drivers/gpu/drm/i915/intel_pm.c
View file @ f8d18d5c
...@@ -199,8 +199,8 @@ static void ilk_get_mem_freq(struct drm_i915_private *dev_priv) ...@@ -199,8 +199,8 @@ static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
dev_priv->mem_freq = 1600; dev_priv->mem_freq = 1600;
break; break;
default: default:
DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
ddrpll & 0xff); ddrpll & 0xff);
dev_priv->mem_freq = 0; dev_priv->mem_freq = 0;
break; break;
} }
...@@ -228,8 +228,8 @@ static void ilk_get_mem_freq(struct drm_i915_private *dev_priv) ...@@ -228,8 +228,8 @@ static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq = 6400; dev_priv->fsb_freq = 6400;
break; break;
default: default:
DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
csipll & 0x3ff); csipll & 0x3ff);
dev_priv->fsb_freq = 0; dev_priv->fsb_freq = 0;
break; break;
} }
...@@ -314,7 +314,8 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) ...@@ -314,7 +314,8 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); drm_err(&dev_priv->drm,
"timed out waiting for Punit DDR DVFS request\n");
vlv_punit_put(dev_priv); vlv_punit_put(dev_priv);
} }
...@@ -383,9 +384,9 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl ...@@ -383,9 +384,9 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl
trace_intel_memory_cxsr(dev_priv, was_enabled, enable); trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n", drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
enableddisabled(enable), enableddisabled(enable),
enableddisabled(was_enabled)); enableddisabled(was_enabled));
return was_enabled; return was_enabled;
} }
...@@ -510,8 +511,8 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, ...@@ -510,8 +511,8 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
if (i9xx_plane == PLANE_B) if (i9xx_plane == PLANE_B)
size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size); dsparb, plane_name(i9xx_plane), size);
return size; return size;
} }
...@@ -527,8 +528,8 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv, ...@@ -527,8 +528,8 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
size >>= 1; /* Convert to cachelines */ size >>= 1; /* Convert to cachelines */
DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size); dsparb, plane_name(i9xx_plane), size);
return size; return size;
} }
...@@ -542,8 +543,8 @@ static int i845_get_fifo_size(struct drm_i915_private *dev_priv, ...@@ -542,8 +543,8 @@ static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
size = dsparb & 0x7f; size = dsparb & 0x7f;
size >>= 2; /* Convert to cachelines */ size >>= 2; /* Convert to cachelines */
DRM_DEBUG_KMS("FIFO size - (0x%08x) %c: %d\n", drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
dsparb, plane_name(i9xx_plane), size); dsparb, plane_name(i9xx_plane), size);
return size; return size;
} }
...@@ -870,7 +871,8 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc) ...@@ -870,7 +871,8 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
dev_priv->fsb_freq, dev_priv->fsb_freq,
dev_priv->mem_freq); dev_priv->mem_freq);
if (!latency) { if (!latency) {
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); drm_dbg_kms(&dev_priv->drm,
"Unknown FSB/MEM found, disable CxSR\n");
intel_set_memory_cxsr(dev_priv, false); intel_set_memory_cxsr(dev_priv, false);
return; return;
} }
...@@ -892,7 +894,7 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc) ...@@ -892,7 +894,7 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
reg &= ~DSPFW_SR_MASK; reg &= ~DSPFW_SR_MASK;
reg |= FW_WM(wm, SR); reg |= FW_WM(wm, SR);
I915_WRITE(DSPFW1, reg); I915_WRITE(DSPFW1, reg);
DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
/* cursor SR */ /* cursor SR */
wm = intel_calculate_wm(clock, &pnv_cursor_wm, wm = intel_calculate_wm(clock, &pnv_cursor_wm,
...@@ -920,7 +922,7 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc) ...@@ -920,7 +922,7 @@ static void pnv_update_wm(struct intel_crtc *unused_crtc)
reg &= ~DSPFW_HPLL_CURSOR_MASK; reg &= ~DSPFW_HPLL_CURSOR_MASK;
reg |= FW_WM(wm, HPLL_CURSOR); reg |= FW_WM(wm, HPLL_CURSOR);
I915_WRITE(DSPFW3, reg); I915_WRITE(DSPFW3, reg);
DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
intel_set_memory_cxsr(dev_priv, true); intel_set_memory_cxsr(dev_priv, true);
} else { } else {
...@@ -1211,6 +1213,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, ...@@ -1211,6 +1213,7 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state) const struct intel_plane_state *plane_state)
{ {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
enum plane_id plane_id = plane->id; enum plane_id plane_id = plane->id;
bool dirty = false; bool dirty = false;
...@@ -1263,16 +1266,18 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, ...@@ -1263,16 +1266,18 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
out: out:
if (dirty) { if (dirty) {
DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n", drm_dbg_kms(&dev_priv->drm,
plane->base.name, "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], plane->base.name,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
if (plane_id == PLANE_PRIMARY) if (plane_id == PLANE_PRIMARY)
DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n", drm_dbg_kms(&dev_priv->drm,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, "FBC watermarks: SR=%d, HPLL=%d\n",
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
} }
return dirty; return dirty;
...@@ -1790,6 +1795,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, ...@@ -1790,6 +1795,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state) const struct intel_plane_state *plane_state)
{ {
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum plane_id plane_id = plane->id; enum plane_id plane_id = plane->id;
int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
int level; int level;
...@@ -1817,11 +1823,12 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, ...@@ -1817,11 +1823,12 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
out: out:
if (dirty) if (dirty)
DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n", drm_dbg_kms(&dev_priv->drm,
plane->base.name, "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], plane->base.name,
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
return dirty; return dirty;
} }
...@@ -2236,8 +2243,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc) ...@@ -2236,8 +2243,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
if (srwm < 0) if (srwm < 0)
srwm = 1; srwm = 1;
srwm &= 0x1ff; srwm &= 0x1ff;
DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", drm_dbg_kms(&dev_priv->drm,
entries, srwm); "self-refresh entries: %d, wm: %d\n",
entries, srwm);
entries = intel_wm_method2(clock, htotal, entries = intel_wm_method2(clock, htotal,
crtc->base.cursor->state->crtc_w, 4, crtc->base.cursor->state->crtc_w, 4,
...@@ -2250,8 +2258,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc) ...@@ -2250,8 +2258,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
if (cursor_sr > i965_cursor_wm_info.max_wm) if (cursor_sr > i965_cursor_wm_info.max_wm)
cursor_sr = i965_cursor_wm_info.max_wm; cursor_sr = i965_cursor_wm_info.max_wm;
DRM_DEBUG_KMS("self-refresh watermark: display plane %d " drm_dbg_kms(&dev_priv->drm,
"cursor %d\n", srwm, cursor_sr); "self-refresh watermark: display plane %d "
"cursor %d\n", srwm, cursor_sr);
cxsr_enabled = true; cxsr_enabled = true;
} else { } else {
...@@ -2260,8 +2269,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc) ...@@ -2260,8 +2269,9 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
intel_set_memory_cxsr(dev_priv, false); intel_set_memory_cxsr(dev_priv, false);
} }
DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", drm_dbg_kms(&dev_priv->drm,
srwm); "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
srwm);
/* 965 has limitations... */ /* 965 has limitations... */
I915_WRITE(DSPFW1, FW_WM(srwm, SR) | I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
...@@ -2351,7 +2361,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) ...@@ -2351,7 +2361,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
planeb_wm = wm_info->max_wm; planeb_wm = wm_info->max_wm;
} }
DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); drm_dbg_kms(&dev_priv->drm,
"FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
if (IS_I915GM(dev_priv) && enabled) { if (IS_I915GM(dev_priv) && enabled) {
struct drm_i915_gem_object *obj; struct drm_i915_gem_object *obj;
...@@ -2393,7 +2404,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) ...@@ -2393,7 +2404,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
entries = intel_wm_method2(clock, htotal, hdisplay, cpp, entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
sr_latency_ns / 100); sr_latency_ns / 100);
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); drm_dbg_kms(&dev_priv->drm,
"self-refresh entries: %d\n", entries);
srwm = wm_info->fifo_size - entries; srwm = wm_info->fifo_size - entries;
if (srwm < 0) if (srwm < 0)
srwm = 1; srwm = 1;
...@@ -2405,8 +2417,9 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) ...@@ -2405,8 +2417,9 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
I915_WRITE(FW_BLC_SELF, srwm & 0x3f); I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
} }
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", drm_dbg_kms(&dev_priv->drm,
planea_wm, planeb_wm, cwm, srwm); "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
planea_wm, planeb_wm, cwm, srwm);
fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
fwater_hi = (cwm & 0x1f); fwater_hi = (cwm & 0x1f);
...@@ -2442,7 +2455,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc) ...@@ -2442,7 +2455,8 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
fwater_lo = I915_READ(FW_BLC) & ~0xfff; fwater_lo = I915_READ(FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm; fwater_lo |= (3<<8) | planea_wm;
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); drm_dbg_kms(&dev_priv->drm,
"Setting FIFO watermarks - A: %d\n", planea_wm);
I915_WRITE(FW_BLC, fwater_lo); I915_WRITE(FW_BLC, fwater_lo);
} }
...@@ -2841,7 +2855,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, ...@@ -2841,7 +2855,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
&val, NULL); &val, NULL);
if (ret) { if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret); drm_err(&dev_priv->drm,
"SKL Mailbox read error = %d\n", ret);
return; return;
} }
...@@ -2859,7 +2874,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, ...@@ -2859,7 +2874,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
GEN9_PCODE_READ_MEM_LATENCY, GEN9_PCODE_READ_MEM_LATENCY,
&val, NULL); &val, NULL);
if (ret) { if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret); drm_err(&dev_priv->drm,
"SKL Mailbox read error = %d\n", ret);
return; return;
} }
...@@ -2977,8 +2993,9 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, ...@@ -2977,8 +2993,9 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
unsigned int latency = wm[level]; unsigned int latency = wm[level];
if (latency == 0) { if (latency == 0) {
DRM_DEBUG_KMS("%s WM%d latency not provided\n", drm_dbg_kms(&dev_priv->drm,
name, level); "%s WM%d latency not provided\n",
name, level);
continue; continue;
} }
...@@ -2991,9 +3008,9 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, ...@@ -2991,9 +3008,9 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
else if (level > 0) else if (level > 0)
latency *= 5; latency *= 5;
DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", drm_dbg_kms(&dev_priv->drm,
name, level, wm[level], "%s WM%d latency %u (%u.%u usec)\n", name, level,
latency / 10, latency % 10); wm[level], latency / 10, latency % 10);
} }
} }
...@@ -3027,7 +3044,8 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) ...@@ -3027,7 +3044,8 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
if (!changed) if (!changed)
return; return;
DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); drm_dbg_kms(&dev_priv->drm,
"WM latency values increased to avoid potential underruns\n");
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
...@@ -3055,7 +3073,8 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv) ...@@ -3055,7 +3073,8 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[3] = 0; dev_priv->wm.spr_latency[3] = 0;
dev_priv->wm.cur_latency[3] = 0; dev_priv->wm.cur_latency[3] = 0;
DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n"); drm_dbg_kms(&dev_priv->drm,
"LP3 watermarks disabled due to potential for lost interrupts\n");
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
...@@ -3105,7 +3124,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, ...@@ -3105,7 +3124,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
/* At least LP0 must be valid */ /* At least LP0 must be valid */
if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
DRM_DEBUG_KMS("LP0 watermark invalid\n"); drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
return false; return false;
} }
...@@ -3682,7 +3701,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv) ...@@ -3682,7 +3701,7 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
return; return;
} }
DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n"); drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
} else if (IS_GEN(dev_priv, 11)) { } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10; dev_priv->sagv_block_time_us = 10;
return; return;
...@@ -3722,7 +3741,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) ...@@ -3722,7 +3741,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
if (dev_priv->sagv_status == I915_SAGV_ENABLED) if (dev_priv->sagv_status == I915_SAGV_ENABLED)
return 0; return 0;
DRM_DEBUG_KMS("Enabling SAGV\n"); drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_ENABLE); GEN9_SAGV_ENABLE);
...@@ -3733,11 +3752,11 @@ intel_enable_sagv(struct drm_i915_private *dev_priv) ...@@ -3733,11 +3752,11 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
* don't actually have SAGV. * don't actually have SAGV.
*/ */
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
return 0; return 0;
} else if (ret < 0) { } else if (ret < 0) {
DRM_ERROR("Failed to enable SAGV\n"); drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
return ret; return ret;
} }
...@@ -3756,7 +3775,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) ...@@ -3756,7 +3775,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
if (dev_priv->sagv_status == I915_SAGV_DISABLED) if (dev_priv->sagv_status == I915_SAGV_DISABLED)
return 0; return 0;
DRM_DEBUG_KMS("Disabling SAGV\n"); drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
/* bspec says to keep retrying for at least 1 ms */ /* bspec says to keep retrying for at least 1 ms */
ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_DISABLE, GEN9_SAGV_DISABLE,
...@@ -3767,11 +3786,11 @@ intel_disable_sagv(struct drm_i915_private *dev_priv) ...@@ -3767,11 +3786,11 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
* don't actually have SAGV. * don't actually have SAGV.
*/ */
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
return 0; return 0;
} else if (ret < 0) { } else if (ret < 0) {
DRM_ERROR("Failed to disable SAGV (%d)\n", ret); drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
return ret; return ret;
} }
...@@ -4340,9 +4359,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, ...@@ -4340,9 +4359,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
} }
if (level < 0) { if (level < 0) {
DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations"); drm_dbg_kms(&dev_priv->drm,
DRM_DEBUG_KMS("minimum required %d/%d\n", blocks, "Requested display configuration exceeds system DDB limitations");
alloc_size); drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
blocks, alloc_size);
return -EINVAL; return -EINVAL;
} }
...@@ -4570,7 +4590,8 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state, ...@@ -4570,7 +4590,8 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
/* only planar format has two planes */ /* only planar format has two planes */
if (color_plane == 1 && if (color_plane == 1 &&
!intel_format_info_is_yuv_semiplanar(format, modifier)) { !intel_format_info_is_yuv_semiplanar(format, modifier)) {
DRM_DEBUG_KMS("Non planar format have single plane\n"); drm_dbg_kms(&dev_priv->drm,
"Non planar format have single plane\n");
return -EINVAL; return -EINVAL;
} }
...@@ -5269,10 +5290,11 @@ skl_print_wm_changes(struct intel_atomic_state *state) ...@@ -5269,10 +5290,11 @@ skl_print_wm_changes(struct intel_atomic_state *state)
if (skl_ddb_entry_equal(old, new)) if (skl_ddb_entry_equal(old, new))
continue; continue;
DRM_DEBUG_KMS("[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n", drm_dbg_kms(&dev_priv->drm,
plane->base.base.id, plane->base.name, "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
old->start, old->end, new->start, new->end, plane->base.base.id, plane->base.name,
skl_ddb_entry_size(old), skl_ddb_entry_size(new)); old->start, old->end, new->start, new->end,
skl_ddb_entry_size(old), skl_ddb_entry_size(new));
} }
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
...@@ -5285,70 +5307,74 @@ skl_print_wm_changes(struct intel_atomic_state *state) ...@@ -5285,70 +5307,74 @@ skl_print_wm_changes(struct intel_atomic_state *state)
if (skl_plane_wm_equals(dev_priv, old_wm, new_wm)) if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
continue; continue;
DRM_DEBUG_KMS("[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm" drm_dbg_kms(&dev_priv->drm,
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n", "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm"
plane->base.base.id, plane->base.name, " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm\n",
enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en), plane->base.base.id, plane->base.name,
enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en), enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en), enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en), enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
enast(old_wm->trans_wm.plane_en), enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en), enast(old_wm->trans_wm.plane_en),
enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en), enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en), enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en), enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
enast(new_wm->trans_wm.plane_en)); enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
enast(new_wm->trans_wm.plane_en));
DRM_DEBUG_KMS("[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n", " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
plane->base.base.id, plane->base.name, plane->base.base.id, plane->base.name,
enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l, enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l, enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l, enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l, enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l, enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l, enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l, enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l, enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l, enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l, enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l, enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l, enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l, enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l, enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l, enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l, enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l, enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l); enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
DRM_DEBUG_KMS("[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d" drm_dbg_kms(&dev_priv->drm,
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
plane->base.base.id, plane->base.name, " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b, plane->base.base.id, plane->base.name,
old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b, old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b, old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b, old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->trans_wm.plane_res_b, old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b, old_wm->trans_wm.plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b, new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b, new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b, new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->trans_wm.plane_res_b); new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b);
DRM_DEBUG_KMS("[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n", drm_dbg_kms(&dev_priv->drm,
plane->base.base.id, plane->base.name, "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, plane->base.base.id, plane->base.name,
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc, old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, old_wm->trans_wm.min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc); new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
} }
} }
} }
...@@ -5940,19 +5966,22 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv) ...@@ -5940,19 +5966,22 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
crtc_state->wm.g4x.optimal = *active; crtc_state->wm.g4x.optimal = *active;
crtc_state->wm.g4x.intermediate = *active; crtc_state->wm.g4x.intermediate = *active;
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n", drm_dbg_kms(&dev_priv->drm,
pipe_name(pipe), "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
wm->pipe[pipe].plane[PLANE_PRIMARY], pipe_name(pipe),
wm->pipe[pipe].plane[PLANE_CURSOR], wm->pipe[pipe].plane[PLANE_PRIMARY],
wm->pipe[pipe].plane[PLANE_SPRITE0]); wm->pipe[pipe].plane[PLANE_CURSOR],
wm->pipe[pipe].plane[PLANE_SPRITE0]);
} }
DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n", drm_dbg_kms(&dev_priv->drm,
wm->sr.plane, wm->sr.cursor, wm->sr.fbc); "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n", wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); drm_dbg_kms(&dev_priv->drm,
DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n", "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
} }
void g4x_wm_sanitize(struct drm_i915_private *dev_priv) void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
...@@ -6044,8 +6073,9 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) ...@@ -6044,8 +6073,9 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " drm_dbg_kms(&dev_priv->drm,
"assuming DDR DVFS is disabled\n"); "Punit not acking DDR DVFS request, "
"assuming DDR DVFS is disabled\n");
dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
} else { } else {
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
...@@ -6096,16 +6126,18 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) ...@@ -6096,16 +6126,18 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
crtc_state->wm.vlv.optimal = *active; crtc_state->wm.vlv.optimal = *active;
crtc_state->wm.vlv.intermediate = *active; crtc_state->wm.vlv.intermediate = *active;
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", drm_dbg_kms(&dev_priv->drm,
pipe_name(pipe), "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
wm->pipe[pipe].plane[PLANE_PRIMARY], pipe_name(pipe),
wm->pipe[pipe].plane[PLANE_CURSOR], wm->pipe[pipe].plane[PLANE_PRIMARY],
wm->pipe[pipe].plane[PLANE_SPRITE0], wm->pipe[pipe].plane[PLANE_CURSOR],
wm->pipe[pipe].plane[PLANE_SPRITE1]); wm->pipe[pipe].plane[PLANE_SPRITE0],
wm->pipe[pipe].plane[PLANE_SPRITE1]);
} }
DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", drm_dbg_kms(&dev_priv->drm,
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
} }
void vlv_wm_sanitize(struct drm_i915_private *dev_priv) void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
...@@ -6421,8 +6453,9 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) ...@@ -6421,8 +6453,9 @@ static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
tmp = I915_READ(MCH_SSKPD); tmp = I915_READ(MCH_SSKPD);
if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", drm_dbg_kms(&dev_priv->drm,
tmp); "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
tmp);
} }
static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
...@@ -7137,7 +7170,8 @@ void intel_suspend_hw(struct drm_i915_private *dev_priv) ...@@ -7137,7 +7170,8 @@ void intel_suspend_hw(struct drm_i915_private *dev_priv)
static void nop_init_clock_gating(struct drm_i915_private *dev_priv) static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
{ {
DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n"); drm_dbg_kms(&dev_priv->drm,
"No clock gating settings or workarounds applied.\n");
} }
/** /**
...@@ -7232,8 +7266,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv) ...@@ -7232,8 +7266,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.optimize_watermarks = dev_priv->display.optimize_watermarks =
ilk_optimize_watermarks; ilk_optimize_watermarks;
} else { } else {
DRM_DEBUG_KMS("Failed to read display plane latency. " drm_dbg_kms(&dev_priv->drm,
"Disable CxSR\n"); "Failed to read display plane latency. "
"Disable CxSR\n");
} }
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv); vlv_setup_wm_latency(dev_priv);
...@@ -7253,7 +7288,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv) ...@@ -7253,7 +7288,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->is_ddr3, dev_priv->is_ddr3,
dev_priv->fsb_freq, dev_priv->fsb_freq,
dev_priv->mem_freq)) { dev_priv->mem_freq)) {
DRM_INFO("failed to find known CxSR latency " drm_info(&dev_priv->drm,
"failed to find known CxSR latency "
"(found ddr%s fsb freq %d, mem freq %d), " "(found ddr%s fsb freq %d, mem freq %d), "
"disabling CxSR\n", "disabling CxSR\n",
(dev_priv->is_ddr3 == 1) ? "3" : "2", (dev_priv->is_ddr3 == 1) ? "3" : "2",
...@@ -7277,7 +7313,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv) ...@@ -7277,7 +7313,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.get_fifo_size = i830_get_fifo_size; dev_priv->display.get_fifo_size = i830_get_fifo_size;
} }
} else { } else {
DRM_ERROR("unexpected fall-through in intel_init_pm\n"); drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
} }
} }
......
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