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Commit fc3ebc3c authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'char-misc-5.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc fixes from Greg KH:
 "Some tiny char/misc driver fixes for 5.8-rc3.

  The "largest" changes are in the mei driver, to resolve some reported
  problems and add some new device ids. There's also a binder bugfix, an
  fpga driver build fix, and some assorted habanalabs fixes.

  All of these, except for the habanalabs fixes, have been in linux-next
  with no reported issues. The habanalabs driver changes showed up in my
  tree on Friday, but as they are totally self-contained, all should be
  good there"

* tag 'char-misc-5.8-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  habanalabs: increase h/w timer when checking idle
  habanalabs: Correct handling when failing to enqueue CB
  habanalabs: increase GAUDI QMAN ARB WDT timeout
  habanalabs: rename mmu_write() to mmu_asid_va_write()
  habanalabs: use PI in MMU cache invalidation
  habanalabs: block scalar load_and_exe on external queue
  mei: me: add tiger lake point device ids for H platforms.
  mei: me: disable mei interface on Mehlow server platforms
  binder: fix null deref of proc->context
  fpga: zynqmp: fix modular build
parents 42f8f9bc 70b23b87
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Showing with 153 additions and 30 deletions
drivers/android/binder.c
View file @ fc3ebc3c
...@@ -4686,8 +4686,15 @@ static struct binder_thread *binder_get_thread(struct binder_proc *proc) ...@@ -4686,8 +4686,15 @@ static struct binder_thread *binder_get_thread(struct binder_proc *proc)
static void binder_free_proc(struct binder_proc *proc) static void binder_free_proc(struct binder_proc *proc)
{ {
struct binder_device *device;
BUG_ON(!list_empty(&proc->todo)); BUG_ON(!list_empty(&proc->todo));
BUG_ON(!list_empty(&proc->delivered_death)); BUG_ON(!list_empty(&proc->delivered_death));
device = container_of(proc->context, struct binder_device, context);
if (refcount_dec_and_test(&device->ref)) {
kfree(proc->context->name);
kfree(device);
}
binder_alloc_deferred_release(&proc->alloc); binder_alloc_deferred_release(&proc->alloc);
put_task_struct(proc->tsk); put_task_struct(proc->tsk);
binder_stats_deleted(BINDER_STAT_PROC); binder_stats_deleted(BINDER_STAT_PROC);
...@@ -5406,7 +5413,6 @@ static int binder_node_release(struct binder_node *node, int refs) ...@@ -5406,7 +5413,6 @@ static int binder_node_release(struct binder_node *node, int refs)
static void binder_deferred_release(struct binder_proc *proc) static void binder_deferred_release(struct binder_proc *proc)
{ {
struct binder_context *context = proc->context; struct binder_context *context = proc->context;
struct binder_device *device;
struct rb_node *n; struct rb_node *n;
int threads, nodes, incoming_refs, outgoing_refs, active_transactions; int threads, nodes, incoming_refs, outgoing_refs, active_transactions;
...@@ -5423,12 +5429,6 @@ static void binder_deferred_release(struct binder_proc *proc) ...@@ -5423,12 +5429,6 @@ static void binder_deferred_release(struct binder_proc *proc)
context->binder_context_mgr_node = NULL; context->binder_context_mgr_node = NULL;
} }
mutex_unlock(&context->context_mgr_node_lock); mutex_unlock(&context->context_mgr_node_lock);
device = container_of(proc->context, struct binder_device, context);
if (refcount_dec_and_test(&device->ref)) {
kfree(context->name);
kfree(device);
}
proc->context = NULL;
binder_inner_proc_lock(proc); binder_inner_proc_lock(proc);
/* /*
* Make sure proc stays alive after we * Make sure proc stays alive after we
......
drivers/fpga/Kconfig
View file @ fc3ebc3c
...@@ -208,7 +208,7 @@ config FPGA_DFL_PCI ...@@ -208,7 +208,7 @@ config FPGA_DFL_PCI
config FPGA_MGR_ZYNQMP_FPGA config FPGA_MGR_ZYNQMP_FPGA
tristate "Xilinx ZynqMP FPGA" tristate "Xilinx ZynqMP FPGA"
depends on ARCH_ZYNQMP || COMPILE_TEST depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
help help
FPGA manager driver support for Xilinx ZynqMP FPGAs. FPGA manager driver support for Xilinx ZynqMP FPGAs.
This driver uses the processor configuration port(PCAP) This driver uses the processor configuration port(PCAP)
......
drivers/misc/habanalabs/command_submission.c
View file @ fc3ebc3c
...@@ -62,6 +62,12 @@ static void hl_fence_release(struct dma_fence *fence) ...@@ -62,6 +62,12 @@ static void hl_fence_release(struct dma_fence *fence)
container_of(fence, struct hl_cs_compl, base_fence); container_of(fence, struct hl_cs_compl, base_fence);
struct hl_device *hdev = hl_cs_cmpl->hdev; struct hl_device *hdev = hl_cs_cmpl->hdev;
/* EBUSY means the CS was never submitted and hence we don't have
* an attached hw_sob object that we should handle here
*/
if (fence->error == -EBUSY)
goto free;
if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) || if ((hl_cs_cmpl->type == CS_TYPE_SIGNAL) ||
(hl_cs_cmpl->type == CS_TYPE_WAIT)) { (hl_cs_cmpl->type == CS_TYPE_WAIT)) {
...@@ -92,6 +98,7 @@ static void hl_fence_release(struct dma_fence *fence) ...@@ -92,6 +98,7 @@ static void hl_fence_release(struct dma_fence *fence)
kref_put(&hl_cs_cmpl->hw_sob->kref, hl_sob_reset); kref_put(&hl_cs_cmpl->hw_sob->kref, hl_sob_reset);
} }
free:
kfree_rcu(hl_cs_cmpl, base_fence.rcu); kfree_rcu(hl_cs_cmpl, base_fence.rcu);
} }
...@@ -328,10 +335,16 @@ static void cs_do_release(struct kref *ref) ...@@ -328,10 +335,16 @@ static void cs_do_release(struct kref *ref)
hl_ctx_put(cs->ctx); hl_ctx_put(cs->ctx);
/* We need to mark an error for not submitted because in that case
* the dma fence release flow is different. Mainly, we don't need
* to handle hw_sob for signal/wait
*/
if (cs->timedout) if (cs->timedout)
dma_fence_set_error(cs->fence, -ETIMEDOUT); dma_fence_set_error(cs->fence, -ETIMEDOUT);
else if (cs->aborted) else if (cs->aborted)
dma_fence_set_error(cs->fence, -EIO); dma_fence_set_error(cs->fence, -EIO);
else if (!cs->submitted)
dma_fence_set_error(cs->fence, -EBUSY);
dma_fence_signal(cs->fence); dma_fence_signal(cs->fence);
dma_fence_put(cs->fence); dma_fence_put(cs->fence);
......
drivers/misc/habanalabs/debugfs.c
View file @ fc3ebc3c
...@@ -480,7 +480,7 @@ static int mmu_show(struct seq_file *s, void *data) ...@@ -480,7 +480,7 @@ static int mmu_show(struct seq_file *s, void *data)
return 0; return 0;
} }
static ssize_t mmu_write(struct file *file, const char __user *buf, static ssize_t mmu_asid_va_write(struct file *file, const char __user *buf,
size_t count, loff_t *f_pos) size_t count, loff_t *f_pos)
{ {
struct seq_file *s = file->private_data; struct seq_file *s = file->private_data;
...@@ -1125,7 +1125,7 @@ static const struct hl_info_list hl_debugfs_list[] = { ...@@ -1125,7 +1125,7 @@ static const struct hl_info_list hl_debugfs_list[] = {
{"command_submission_jobs", command_submission_jobs_show, NULL}, {"command_submission_jobs", command_submission_jobs_show, NULL},
{"userptr", userptr_show, NULL}, {"userptr", userptr_show, NULL},
{"vm", vm_show, NULL}, {"vm", vm_show, NULL},
{"mmu", mmu_show, mmu_write}, {"mmu", mmu_show, mmu_asid_va_write},
{"engines", engines_show, NULL} {"engines", engines_show, NULL}
}; };
......
drivers/misc/habanalabs/gaudi/gaudi.c
View file @ fc3ebc3c
...@@ -96,7 +96,7 @@ ...@@ -96,7 +96,7 @@
#define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3 #define GAUDI_NUM_OF_QM_ARB_ERR_CAUSE 3
#define GAUDI_ARB_WDT_TIMEOUT 0x400000 #define GAUDI_ARB_WDT_TIMEOUT 0x1000000
static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = { static const char gaudi_irq_name[GAUDI_MSI_ENTRIES][GAUDI_MAX_STRING_LEN] = {
"gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3", "gaudi cq 0_0", "gaudi cq 0_1", "gaudi cq 0_2", "gaudi cq 0_3",
...@@ -1893,6 +1893,8 @@ static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id, ...@@ -1893,6 +1893,8 @@ static void gaudi_init_pci_dma_qman(struct hl_device *hdev, int dma_id,
WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo); WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 + q_off, so_base_ws_lo);
WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi); WREG32(mmDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 + q_off, so_base_ws_hi);
WREG32(mmDMA0_QM_CP_BARRIER_CFG_0 + q_off, 0x100);
/* The following configuration is needed only once per QMAN */ /* The following configuration is needed only once per QMAN */
if (qman_id == 0) { if (qman_id == 0) {
/* Configure RAZWI IRQ */ /* Configure RAZWI IRQ */
...@@ -2725,6 +2727,12 @@ static int gaudi_mmu_init(struct hl_device *hdev) ...@@ -2725,6 +2727,12 @@ static int gaudi_mmu_init(struct hl_device *hdev)
WREG32(mmSTLB_HOP_CONFIGURATION, WREG32(mmSTLB_HOP_CONFIGURATION,
hdev->mmu_huge_page_opt ? 0x30440 : 0x40440); hdev->mmu_huge_page_opt ? 0x30440 : 0x40440);
/*
* The H/W expects the first PI after init to be 1. After wraparound
* we'll write 0.
*/
gaudi->mmu_cache_inv_pi = 1;
gaudi->hw_cap_initialized |= HW_CAP_MMU; gaudi->hw_cap_initialized |= HW_CAP_MMU;
return 0; return 0;
...@@ -3790,6 +3798,25 @@ static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev, ...@@ -3790,6 +3798,25 @@ static int gaudi_validate_dma_pkt_no_mmu(struct hl_device *hdev,
src_in_host); src_in_host);
} }
static int gaudi_validate_load_and_exe_pkt(struct hl_device *hdev,
struct hl_cs_parser *parser,
struct packet_load_and_exe *user_pkt)
{
u32 cfg;
cfg = le32_to_cpu(user_pkt->cfg);
if (cfg & GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK) {
dev_err(hdev->dev,
"User not allowed to use Load and Execute\n");
return -EPERM;
}
parser->patched_cb_size += sizeof(struct packet_load_and_exe);
return 0;
}
static int gaudi_validate_cb(struct hl_device *hdev, static int gaudi_validate_cb(struct hl_device *hdev,
struct hl_cs_parser *parser, bool is_mmu) struct hl_cs_parser *parser, bool is_mmu)
{ {
...@@ -3838,6 +3865,11 @@ static int gaudi_validate_cb(struct hl_device *hdev, ...@@ -3838,6 +3865,11 @@ static int gaudi_validate_cb(struct hl_device *hdev,
rc = -EPERM; rc = -EPERM;
break; break;
case PACKET_LOAD_AND_EXE:
rc = gaudi_validate_load_and_exe_pkt(hdev, parser,
(struct packet_load_and_exe *) user_pkt);
break;
case PACKET_LIN_DMA: case PACKET_LIN_DMA:
parser->contains_dma_pkt = true; parser->contains_dma_pkt = true;
if (is_mmu) if (is_mmu)
...@@ -3855,7 +3887,6 @@ static int gaudi_validate_cb(struct hl_device *hdev, ...@@ -3855,7 +3887,6 @@ static int gaudi_validate_cb(struct hl_device *hdev,
case PACKET_FENCE: case PACKET_FENCE:
case PACKET_NOP: case PACKET_NOP:
case PACKET_ARB_POINT: case PACKET_ARB_POINT:
case PACKET_LOAD_AND_EXE:
parser->patched_cb_size += pkt_size; parser->patched_cb_size += pkt_size;
break; break;
...@@ -5994,6 +6025,8 @@ static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard, ...@@ -5994,6 +6025,8 @@ static int gaudi_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
mutex_lock(&hdev->mmu_cache_lock); mutex_lock(&hdev->mmu_cache_lock);
/* L0 & L1 invalidation */ /* L0 & L1 invalidation */
WREG32(mmSTLB_INV_PS, 3);
WREG32(mmSTLB_CACHE_INV, gaudi->mmu_cache_inv_pi++);
WREG32(mmSTLB_INV_PS, 2); WREG32(mmSTLB_INV_PS, 2);
rc = hl_poll_timeout( rc = hl_poll_timeout(
......
drivers/misc/habanalabs/gaudi/gaudiP.h
View file @ fc3ebc3c
...@@ -229,6 +229,8 @@ struct gaudi_internal_qman_info { ...@@ -229,6 +229,8 @@ struct gaudi_internal_qman_info {
* @multi_msi_mode: whether we are working in multi MSI single MSI mode. * @multi_msi_mode: whether we are working in multi MSI single MSI mode.
* Multi MSI is possible only with IOMMU enabled. * Multi MSI is possible only with IOMMU enabled.
* @ext_queue_idx: helper index for external queues initialization. * @ext_queue_idx: helper index for external queues initialization.
* @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
* 8-bit value so use u8.
*/ */
struct gaudi_device { struct gaudi_device {
int (*armcp_info_get)(struct hl_device *hdev); int (*armcp_info_get)(struct hl_device *hdev);
...@@ -248,6 +250,7 @@ struct gaudi_device { ...@@ -248,6 +250,7 @@ struct gaudi_device {
u32 hw_cap_initialized; u32 hw_cap_initialized;
u8 multi_msi_mode; u8 multi_msi_mode;
u8 ext_queue_idx; u8 ext_queue_idx;
u8 mmu_cache_inv_pi;
}; };
void gaudi_init_security(struct hl_device *hdev); void gaudi_init_security(struct hl_device *hdev);
......
drivers/misc/habanalabs/include/gaudi/gaudi_packets.h
View file @ fc3ebc3c
...@@ -197,6 +197,9 @@ struct packet_wait { ...@@ -197,6 +197,9 @@ struct packet_wait {
__le32 ctl; __le32 ctl;
}; };
#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_SHIFT 0
#define GAUDI_PKT_LOAD_AND_EXE_CFG_DST_MASK 0x00000001
struct packet_load_and_exe { struct packet_load_and_exe {
__le32 cfg; __le32 cfg;
__le32 ctl; __le32 ctl;
......
drivers/misc/mei/hw-me-regs.h
View file @ fc3ebc3c
...@@ -94,6 +94,7 @@ ...@@ -94,6 +94,7 @@
#define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */ #define MEI_DEV_ID_JSP_N 0x4DE0 /* Jasper Lake Point N */
#define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */
#define MEI_DEV_ID_TGP_H 0x43E0 /* Tiger Lake Point H */
#define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */
#define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */
...@@ -107,6 +108,8 @@ ...@@ -107,6 +108,8 @@
# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
#define PCI_CFG_HFS_2 0x48 #define PCI_CFG_HFS_2 0x48
#define PCI_CFG_HFS_3 0x60 #define PCI_CFG_HFS_3 0x60
# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
#define PCI_CFG_HFS_4 0x64 #define PCI_CFG_HFS_4 0x64
#define PCI_CFG_HFS_5 0x68 #define PCI_CFG_HFS_5 0x68
#define PCI_CFG_HFS_6 0x6C #define PCI_CFG_HFS_6 0x6C
......
drivers/misc/mei/hw-me.c
View file @ fc3ebc3c
...@@ -1366,7 +1366,7 @@ static bool mei_me_fw_type_nm(struct pci_dev *pdev) ...@@ -1366,7 +1366,7 @@ static bool mei_me_fw_type_nm(struct pci_dev *pdev)
#define MEI_CFG_FW_NM \ #define MEI_CFG_FW_NM \
.quirk_probe = mei_me_fw_type_nm .quirk_probe = mei_me_fw_type_nm
static bool mei_me_fw_type_sps(struct pci_dev *pdev) static bool mei_me_fw_type_sps_4(struct pci_dev *pdev)
{ {
u32 reg; u32 reg;
unsigned int devfn; unsigned int devfn;
...@@ -1382,6 +1382,35 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev) ...@@ -1382,6 +1382,35 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
return (reg & 0xf0000) == 0xf0000; return (reg & 0xf0000) == 0xf0000;
} }
#define MEI_CFG_FW_SPS_4 \
.quirk_probe = mei_me_fw_type_sps_4
/**
* mei_me_fw_sku_sps() - check for sps sku
*
* Read ME FW Status register to check for SPS Firmware.
* The SPS FW is only signaled in pci function 0
*
* @pdev: pci device
*
* Return: true in case of SPS firmware
*/
static bool mei_me_fw_type_sps(struct pci_dev *pdev)
{
u32 reg;
u32 fw_type;
unsigned int devfn;
devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, &reg);
trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);
dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
return fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
}
#define MEI_CFG_FW_SPS \ #define MEI_CFG_FW_SPS \
.quirk_probe = mei_me_fw_type_sps .quirk_probe = mei_me_fw_type_sps
...@@ -1452,10 +1481,17 @@ static const struct mei_cfg mei_me_pch8_cfg = { ...@@ -1452,10 +1481,17 @@ static const struct mei_cfg mei_me_pch8_cfg = {
}; };
/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
static const struct mei_cfg mei_me_pch8_sps_cfg = { static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
MEI_CFG_PCH8_HFS, MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP, MEI_CFG_FW_VER_SUPP,
MEI_CFG_FW_SPS, MEI_CFG_FW_SPS_4,
};
/* LBG with quirk for SPS (4.0) Firmware exclusion */
static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP,
MEI_CFG_FW_SPS_4,
}; };
/* Cannon Lake and newer devices */ /* Cannon Lake and newer devices */
...@@ -1465,8 +1501,18 @@ static const struct mei_cfg mei_me_pch12_cfg = { ...@@ -1465,8 +1501,18 @@ static const struct mei_cfg mei_me_pch12_cfg = {
MEI_CFG_DMA_128, MEI_CFG_DMA_128,
}; };
/* LBG with quirk for SPS Firmware exclusion */ /* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
static const struct mei_cfg mei_me_pch12_sps_cfg = { static const struct mei_cfg mei_me_pch12_sps_cfg = {
MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP,
MEI_CFG_DMA_128,
MEI_CFG_FW_SPS,
};
/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion
* w/o DMA support
*/
static const struct mei_cfg mei_me_pch12_nodma_sps_cfg = {
MEI_CFG_PCH8_HFS, MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP, MEI_CFG_FW_VER_SUPP,
MEI_CFG_FW_SPS, MEI_CFG_FW_SPS,
...@@ -1480,6 +1526,15 @@ static const struct mei_cfg mei_me_pch15_cfg = { ...@@ -1480,6 +1526,15 @@ static const struct mei_cfg mei_me_pch15_cfg = {
MEI_CFG_TRC, MEI_CFG_TRC,
}; };
/* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */
static const struct mei_cfg mei_me_pch15_sps_cfg = {
MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP,
MEI_CFG_DMA_128,
MEI_CFG_TRC,
MEI_CFG_FW_SPS,
};
/* /*
* mei_cfg_list - A list of platform platform specific configurations. * mei_cfg_list - A list of platform platform specific configurations.
* Note: has to be synchronized with enum mei_cfg_idx. * Note: has to be synchronized with enum mei_cfg_idx.
...@@ -1492,10 +1547,13 @@ static const struct mei_cfg *const mei_cfg_list[] = { ...@@ -1492,10 +1547,13 @@ static const struct mei_cfg *const mei_cfg_list[] = {
[MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg, [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg, [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg, [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg, [MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg, [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
[MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
[MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg, [MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
[MEI_ME_PCH12_SPS_NODMA_CFG] = &mei_me_pch12_nodma_sps_cfg,
[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg, [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
[MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
}; };
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx) const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
......
drivers/misc/mei/hw-me.h
View file @ fc3ebc3c
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
/* /*
* Copyright (c) 2012-2019, Intel Corporation. All rights reserved. * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
* Intel Management Engine Interface (Intel MEI) Linux driver * Intel Management Engine Interface (Intel MEI) Linux driver
*/ */
...@@ -76,14 +76,20 @@ struct mei_me_hw { ...@@ -76,14 +76,20 @@ struct mei_me_hw {
* with quirk for Node Manager exclusion. * with quirk for Node Manager exclusion.
* @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
* client platforms. * client platforms.
* @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
* servers platforms with quirk for * servers platforms with quirk for
* SPS firmware exclusion. * SPS firmware exclusion.
* @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
* @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 and newer * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
* servers platforms with quirk for
* SPS firmware exclusion.
* @MEI_ME_PCH12_SPS_CFG: Platform Controller Hub Gen12 5.0 and newer
* servers platforms with quirk for * servers platforms with quirk for
* SPS firmware exclusion. * SPS firmware exclusion.
* @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer * @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
* @MEI_ME_PCH15_SPS_CFG: Platform Controller Hub Gen15 and newer
* servers platforms with quirk for
* SPS firmware exclusion.
* @MEI_ME_NUM_CFG: Upper Sentinel. * @MEI_ME_NUM_CFG: Upper Sentinel.
*/ */
enum mei_cfg_idx { enum mei_cfg_idx {
...@@ -94,10 +100,13 @@ enum mei_cfg_idx { ...@@ -94,10 +100,13 @@ enum mei_cfg_idx {
MEI_ME_PCH7_CFG, MEI_ME_PCH7_CFG,
MEI_ME_PCH_CPT_PBG_CFG, MEI_ME_PCH_CPT_PBG_CFG,
MEI_ME_PCH8_CFG, MEI_ME_PCH8_CFG,
MEI_ME_PCH8_SPS_CFG, MEI_ME_PCH8_SPS_4_CFG,
MEI_ME_PCH12_CFG, MEI_ME_PCH12_CFG,
MEI_ME_PCH12_SPS_4_CFG,
MEI_ME_PCH12_SPS_CFG, MEI_ME_PCH12_SPS_CFG,
MEI_ME_PCH12_SPS_NODMA_CFG,
MEI_ME_PCH15_CFG, MEI_ME_PCH15_CFG,
MEI_ME_PCH15_SPS_CFG,
MEI_ME_NUM_CFG, MEI_ME_NUM_CFG,
}; };
......
drivers/misc/mei/pci-me.c
View file @ fc3ebc3c
...@@ -59,18 +59,18 @@ static const struct pci_device_id mei_me_pci_tbl[] = { ...@@ -59,18 +59,18 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
...@@ -84,8 +84,8 @@ static const struct pci_device_id mei_me_pci_tbl[] = { ...@@ -84,8 +84,8 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_NODMA_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
...@@ -96,6 +96,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = { ...@@ -96,6 +96,7 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
......
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