Commit fc92b92a authored by Smitha T Murthy's avatar Smitha T Murthy Committed by Mauro Carvalho Chehab

media: s5p-mfc: Add VP9 decoder support

Add support for codec definition and corresponding buffer
requirements for VP9 decoder.
Signed-off-by: default avatarSmitha T Murthy <smitha.t@samsung.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Acked-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent c9fcd51c
...@@ -17,6 +17,8 @@ ...@@ -17,6 +17,8 @@
/* MFCv10 register definitions*/ /* MFCv10 register definitions*/
#define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120 #define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120
#define S5P_FIMV_MFC_STATE_V10 0x7124 #define S5P_FIMV_MFC_STATE_V10 0x7124
#define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10 0xF570
#define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10 0xF574
/* MFCv10 Context buffer sizes */ /* MFCv10 Context buffer sizes */
#define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K) #define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K)
...@@ -33,8 +35,12 @@ ...@@ -33,8 +35,12 @@
/* MFCv10 codec defines*/ /* MFCv10 codec defines*/
#define S5P_FIMV_CODEC_HEVC_DEC 17 #define S5P_FIMV_CODEC_HEVC_DEC 17
#define S5P_FIMV_CODEC_VP9_DEC 18
#define S5P_FIMV_CODEC_HEVC_ENC 26 #define S5P_FIMV_CODEC_HEVC_ENC 26
/* Decoder buffer size for MFC v10 */
#define DEC_VP9_STATIC_BUFFER_SIZE 20480
/* Encoder buffer size for MFC v10.0 */ /* Encoder buffer size for MFC v10.0 */
#define ENC_V100_BASE_SIZE(x, y) \ #define ENC_V100_BASE_SIZE(x, y) \
(((x + 3) * (y + 3) * 8) \ (((x + 3) * (y + 3) * 8) \
......
...@@ -104,6 +104,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) ...@@ -104,6 +104,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
case S5P_MFC_CODEC_HEVC_DEC: case S5P_MFC_CODEC_HEVC_DEC:
codec_type = S5P_FIMV_CODEC_HEVC_DEC; codec_type = S5P_FIMV_CODEC_HEVC_DEC;
break; break;
case S5P_MFC_CODEC_VP9_DEC:
codec_type = S5P_FIMV_CODEC_VP9_DEC;
break;
case S5P_MFC_CODEC_H264_ENC: case S5P_MFC_CODEC_H264_ENC:
codec_type = S5P_FIMV_CODEC_H264_ENC_V6; codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
break; break;
......
...@@ -73,6 +73,7 @@ ...@@ -73,6 +73,7 @@
#define S5P_MFC_CODEC_VC1RCV_DEC 6 #define S5P_MFC_CODEC_VC1RCV_DEC 6
#define S5P_MFC_CODEC_VP8_DEC 7 #define S5P_MFC_CODEC_VP8_DEC 7
#define S5P_MFC_CODEC_HEVC_DEC 17 #define S5P_MFC_CODEC_HEVC_DEC 17
#define S5P_MFC_CODEC_VP9_DEC 18
#define S5P_MFC_CODEC_H264_ENC 20 #define S5P_MFC_CODEC_H264_ENC 20
#define S5P_MFC_CODEC_H264_MVC_ENC 21 #define S5P_MFC_CODEC_H264_MVC_ENC 21
......
...@@ -151,6 +151,13 @@ static struct s5p_mfc_fmt formats[] = { ...@@ -151,6 +151,13 @@ static struct s5p_mfc_fmt formats[] = {
.num_planes = 1, .num_planes = 1,
.versions = MFC_V10_BIT, .versions = MFC_V10_BIT,
}, },
{
.fourcc = V4L2_PIX_FMT_VP9,
.codec_mode = S5P_FIMV_CODEC_VP9_DEC,
.type = MFC_FMT_DEC,
.num_planes = 1,
.versions = MFC_V10_BIT,
},
}; };
#define NUM_FORMATS ARRAY_SIZE(formats) #define NUM_FORMATS ARRAY_SIZE(formats)
......
...@@ -170,6 +170,8 @@ struct s5p_mfc_regs { ...@@ -170,6 +170,8 @@ struct s5p_mfc_regs {
void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */ void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */
void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */ void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */
void __iomem *d_min_scratch_buffer_size; /* v10 */ void __iomem *d_min_scratch_buffer_size; /* v10 */
void __iomem *d_static_buffer_addr; /* v10 */
void __iomem *d_static_buffer_size; /* v10 */
/* encoder registers */ /* encoder registers */
void __iomem *e_frame_width; void __iomem *e_frame_width;
......
...@@ -226,6 +226,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ...@@ -226,6 +226,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
ctx->scratch_buf_size + ctx->scratch_buf_size +
(ctx->mv_count * ctx->mv_size); (ctx->mv_count * ctx->mv_size);
break; break;
case S5P_MFC_CODEC_VP9_DEC:
mfc_debug(2, "Use min scratch buffer size\n");
ctx->bank1.size =
ctx->scratch_buf_size +
DEC_VP9_STATIC_BUFFER_SIZE;
break;
case S5P_MFC_CODEC_H264_ENC: case S5P_MFC_CODEC_H264_ENC:
if (IS_MFCV10(dev)) { if (IS_MFCV10(dev)) {
mfc_debug(2, "Use min scratch buffer size\n"); mfc_debug(2, "Use min scratch buffer size\n");
...@@ -336,6 +342,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx) ...@@ -336,6 +342,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
case S5P_MFC_CODEC_VC1_DEC: case S5P_MFC_CODEC_VC1_DEC:
case S5P_MFC_CODEC_MPEG2_DEC: case S5P_MFC_CODEC_MPEG2_DEC:
case S5P_MFC_CODEC_VP8_DEC: case S5P_MFC_CODEC_VP8_DEC:
case S5P_MFC_CODEC_VP9_DEC:
ctx->ctx.size = buf_size->other_dec_ctx; ctx->ctx.size = buf_size->other_dec_ctx;
break; break;
case S5P_MFC_CODEC_H264_ENC: case S5P_MFC_CODEC_H264_ENC:
...@@ -566,6 +573,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) ...@@ -566,6 +573,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
buf_size1 -= frame_size_mv; buf_size1 -= frame_size_mv;
} }
} }
if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
writel(buf_addr1, mfc_regs->d_static_buffer_addr);
writel(DEC_VP9_STATIC_BUFFER_SIZE,
mfc_regs->d_static_buffer_size);
buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;
buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;
}
mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n", mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n",
buf_addr1, buf_size1, ctx->total_dpb_count); buf_addr1, buf_size1, ctx->total_dpb_count);
...@@ -2272,6 +2286,18 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) ...@@ -2272,6 +2286,18 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8); R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8); R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
if (!IS_MFCV10(dev))
goto done;
/* Initialize registers used in MFC v10 only.
* Also, over-write the registers which have
* a different offset for MFC v10.
*/
/* decoder registers */
R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
done: done:
return &mfc_regs; return &mfc_regs;
#undef S5P_MFC_REG_ADDR #undef S5P_MFC_REG_ADDR
......
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