use register intermediate

R=rsc
APPROVED=rsc
DELTA=21  (7 added, 5 deleted, 9 changed)
OCL=34607
CL=34663

src/cmd/5g/cgen.c

@@ -697,11 +697,18 @@ bgen(Node *n, int true, Prog *to)
 		if(n->addable == 0)
 			goto def;
 		nodconst(&n1, n->type, 0);
-		gins(optoas(OCMP, n->type), n, &n1);
+		regalloc(&n2, n->type, N);
+		regalloc(&n3, n->type, N);
+		cgen(&n1, &n2);
+		cgen(n, &n3);
+		p1 = gins(optoas(OCMP, n->type), &n2, N);
+		p1->reg = n3.val.u.reg;
 		a = ABNE;
 		if(!true)
 			a = ABEQ;
 		patch(gbranch(a, n->type), to);
+		regfree(&n2);
+		regfree(&n3);
 		goto ret;
 
 	case OANDAND:

src/cmd/5g/gsubr.c

@@ -633,19 +633,14 @@ gmove(Node *f, Node *t)
 	case CASE(TUINT64, TUINT64):
 		split64(f, &flo, &fhi);
 		split64(t, &tlo, &thi);
-		if(f->op == OLITERAL) {
-			gins(AMOVW, &flo, &tlo);
-			gins(AMOVW, &fhi, &thi);
-		} else {
-			regalloc(&r1, flo.type, N);
-			regalloc(&r2, fhi.type, N);
-			gins(AMOVW, &flo, &r1);
-			gins(AMOVW, &fhi, &r2);
-			gins(AMOVW, &r1, &tlo);
-			gins(AMOVW, &r2, &thi);
-			regfree(&r1);
-			regfree(&r2);
-		}
+		regalloc(&r1, flo.type, N);
+		regalloc(&r2, fhi.type, N);
+		gins(AMOVW, &flo, &r1);
+		gins(AMOVW, &fhi, &r2);
+		gins(AMOVW, &r1, &tlo);
+		gins(AMOVW, &r2, &thi);
+		regfree(&r1);
+		regfree(&r2);
 		splitclean();
 		splitclean();
 		return;