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Commit 806cacc7 authored by David Chase's avatar David Chase
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[dev.ssa] cmd/compile: replace storeconst w/ storezero, fold addressing 

Because PPC lacks store-immediate, remove the instruction
that implies that it exists.  Replace it with storezero for
the special case of storing zero, because R0 is reserved zero
for Go (though the assembler knows this, do it in SSA).

Also added address folding for storezero.
(Now corrected to use right-sized stores in bulk-zero code.)

Hello.go now compiles to
genssa main
    00000 (...hello.go:7) TEXT "".main(SB), $0
    00001 (...hello.go:7) FUNCDATA $0, "".gcargs·0(SB)
    00002 (...hello.go:7) FUNCDATA $1, "".gclocals·1(SB)
v23 00003 (...hello.go:8) MOVD $go.string."Hello, World!\n"(SB), R3
v11 00004 (...hello.go:8) MOVD R3, 32(R1)
v22 00005 (...hello.go:8) MOVD $14, R3
v6  00006 (...hello.go:8) MOVD R3, 40(R1)
v20 00007 (...hello.go:8) MOVD R0, 48(R1)
v18 00008 (...hello.go:8) MOVD R0, 56(R1)
v9  00009 (...hello.go:8) MOVD R0, 64(R1)
v10 00010 (...hello.go:8) CALL fmt.Printf(SB)
b2  00011 (...hello.go:9) RET
    00012 (<unknown line number>) END

Updates #16010

Change-Id: I33cfd98c21a1617502260ac753fa8cad68c8d85a
Reviewed-on: https://go-review.googlesource.com/25151Reviewed-by: default avatarCherry Zhang <cherryyz@google.com>
Run-TryBot: David Chase <drchase@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
parent ae9570a5
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Inline Side-by-side
Showing with 354 additions and 132 deletions
src/cmd/compile/internal/ppc64/ssa.go
View file @ 806cacc7
...@@ -238,15 +238,14 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) { ...@@ -238,15 +238,14 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
gc.AddAux(&p.From, v) gc.AddAux(&p.From, v)
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
p.To.Reg = gc.SSARegNum(v) p.To.Reg = gc.SSARegNum(v)
case ssa.OpPPC64MOVDstoreconst, ssa.OpPPC64MOVWstoreconst, ssa.OpPPC64MOVHstoreconst, ssa.OpPPC64MOVBstoreconst:
// TODO: pretty sure this is bogus, PPC has no such instruction unless constant is zero. case ssa.OpPPC64MOVDstorezero, ssa.OpPPC64MOVWstorezero, ssa.OpPPC64MOVHstorezero, ssa.OpPPC64MOVBstorezero:
p := gc.Prog(v.Op.Asm()) p := gc.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST p.From.Type = obj.TYPE_REG
sc := v.AuxValAndOff() p.From.Reg = ppc64.REGZERO
p.From.Offset = sc.Val()
p.To.Type = obj.TYPE_MEM p.To.Type = obj.TYPE_MEM
p.To.Reg = gc.SSARegNum(v.Args[0]) p.To.Reg = gc.SSARegNum(v.Args[0])
gc.AddAux2(&p.To, v, sc.Off()) gc.AddAux(&p.To, v)
case ssa.OpPPC64MOVDstore, ssa.OpPPC64MOVWstore, ssa.OpPPC64MOVHstore, ssa.OpPPC64MOVBstore: case ssa.OpPPC64MOVDstore, ssa.OpPPC64MOVWstore, ssa.OpPPC64MOVHstore, ssa.OpPPC64MOVBstore:
p := gc.Prog(v.Op.Asm()) p := gc.Prog(v.Op.Asm())
......
src/cmd/compile/internal/ssa/gen/PPC64.rules
View file @ 806cacc7
...@@ -160,64 +160,78 @@ ...@@ -160,64 +160,78 @@
(Store [1] ptr val mem) -> (MOVBstore ptr val mem) (Store [1] ptr val mem) -> (MOVBstore ptr val mem)
(Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem (Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem) (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstorezero destptr mem)
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 ->
(MOVHstoreconst [0] destptr mem) (MOVHstorezero destptr mem)
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 ->
(MOVBstoreconst [makeValAndOff(0,1)] destptr (MOVBstorezero [1] destptr
(MOVBstoreconst [0] destptr mem)) (MOVBstorezero [0] destptr mem))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 ->
(MOVWstoreconst [0] destptr mem) (MOVWstorezero destptr mem)
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 ->
(MOVHstoreconst [makeValAndOff(0,2)] destptr (MOVHstorezero [2] destptr
(MOVHstoreconst [0] destptr mem)) (MOVHstorezero [0] destptr mem))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 ->
(MOVBstoreconst [makeValAndOff(0,3)] destptr (MOVBstorezero [3] destptr
(MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVBstorezero [2] destptr
(MOVBstoreconst [makeValAndOff(0,1)] destptr (MOVBstorezero [1] destptr
(MOVBstoreconst [0] destptr mem)))) (MOVBstorezero [0] destptr mem))))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 ->
(MOVDstoreconst [0] destptr mem) (MOVDstorezero [0] destptr mem)
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 ->
(MOVWstoreconst [makeValAndOff(0,4)] destptr (MOVWstorezero [4] destptr
(MOVWstoreconst [0] destptr mem)) (MOVWstorezero [0] destptr mem))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 ->
(MOVHstoreconst [makeValAndOff(0,6)] destptr (MOVHstorezero [6] destptr
(MOVHstoreconst [makeValAndOff(0,4)] destptr (MOVHstorezero [4] destptr
(MOVHstoreconst [makeValAndOff(0,2)] destptr (MOVHstorezero [2] destptr
(MOVHstoreconst [0] destptr mem)))) (MOVHstorezero [0] destptr mem))))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 ->
(MOVBstoreconst [makeValAndOff(0,2)] destptr (MOVBstorezero [2] destptr
(MOVBstoreconst [makeValAndOff(0,1)] destptr (MOVBstorezero [1] destptr
(MOVBstoreconst [0] destptr mem))) (MOVBstorezero [0] destptr mem)))
// Zero small numbers of words directly. // Zero small numbers of words directly.
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 ->
(MOVDstoreconst [makeValAndOff(0,8)] destptr (MOVDstorezero [8] destptr
(MOVDstoreconst [0] destptr mem)) (MOVDstorezero [0] destptr mem))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 ->
(MOVDstoreconst [makeValAndOff(0,16)] destptr (MOVDstorezero [16] destptr
(MOVDstoreconst [makeValAndOff(0,8)] destptr (MOVDstorezero [8] destptr
(MOVDstoreconst [0] destptr mem))) (MOVDstorezero [0] destptr mem)))
(Zero [s] destptr mem) && SizeAndAlign(s).Size() == 32 && SizeAndAlign(s).Align()%8 == 0 -> (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 32 && SizeAndAlign(s).Align()%8 == 0 ->
(MOVDstoreconst [makeValAndOff(0,24)] destptr (MOVDstorezero [24] destptr
(MOVDstoreconst [makeValAndOff(0,16)] destptr (MOVDstorezero [16] destptr
(MOVDstoreconst [makeValAndOff(0,8)] destptr (MOVDstorezero [8] destptr
(MOVDstoreconst [0] destptr mem)))) (MOVDstorezero [0] destptr mem))))
// Optimizations // Optimizations
(ADD (MOVDconst [c]) x) -> (ADDconst [c] x) (ADD (MOVDconst [c]) x) -> (ADDconst [c] x)
(ADD x (MOVDconst [c])) -> (ADDconst [c] x) (ADD x (MOVDconst [c])) -> (ADDconst [c] x)
(MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} x val mem) // Fold offsets for stores.
(MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} x val mem) (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} x val mem)
(MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} x val mem) (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} x val mem)
(MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} x val mem) (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} x val mem)
(MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} x val mem)
// TODO MOV*storeconst is wrong for PPC
// (MOVDstore ptr (MOVDconst [c]) mem) && c == 0 -> (MOVDstoreconst [c] ptr mem) // Store of zero -> storezero
(MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVDstorezero [off] {sym} ptr mem)
(MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVWstorezero [off] {sym} ptr mem)
(MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVHstorezero [off] {sym} ptr mem)
(MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVBstorezero [off] {sym} ptr mem)
// Fold offsets for storezero
(MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) ->
(MOVDstorezero [off1+off2] {sym} x mem)
(MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) ->
(MOVWstorezero [off1+off2] {sym} x mem)
(MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) ->
(MOVHstorezero [off1+off2] {sym} x mem)
(MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) ->
(MOVBstorezero [off1+off2] {sym} x mem)
// Lowering extension // Lowering extension
// Note: we always extend to 64 bits even though some ops don't need that many result bits. // Note: we always extend to 64 bits even though some ops don't need that many result bits.
......
src/cmd/compile/internal/ssa/gen/PPC64Ops.go
View file @ 806cacc7
...@@ -102,16 +102,16 @@ func init() { ...@@ -102,16 +102,16 @@ func init() {
// tmp = buildReg("R31") // tmp = buildReg("R31")
// ctxt = buildReg("R11") // ctxt = buildReg("R11")
// tls = buildReg("R13") // tls = buildReg("R13")
gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}} gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}} gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}} gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
gp1cr = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{cr}} gp1cr = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{cr}}
gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{cr}} gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{cr}}
crgp = regInfo{inputs: []regMask{cr}, outputs: []regMask{gp}} crgp = regInfo{inputs: []regMask{cr}, outputs: []regMask{gp}}
gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}} gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{}} gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{}}
gpstoreconst = regInfo{inputs: []regMask{gp | sp | sb, 0}, outputs: []regMask{}} gpstorezero = regInfo{inputs: []regMask{gp | sp | sb, 0}, outputs: []regMask{}} // ppc64.REGZERO is reserved zero value
fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}} fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}}
// fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}} // fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}} fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
fp2cr = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{cr}} fp2cr = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{cr}}
...@@ -162,10 +162,10 @@ func init() { ...@@ -162,10 +162,10 @@ func init() {
{name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", typ: "Mem"}, {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", typ: "Mem"},
{name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", typ: "Mem"}, {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", typ: "Mem"},
{name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem {name: "MOVBstorezero", argLength: 2, reg: gpstorezero, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store zero byte to arg0+aux. arg1=mem
{name: "MOVHstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVH", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... {name: "MOVHstorezero", argLength: 2, reg: gpstorezero, asm: "MOVH", aux: "SymOff", typ: "Mem"}, // store zero 2 bytes to ...
{name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... {name: "MOVWstorezero", argLength: 2, reg: gpstorezero, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store zero 4 bytes to ...
{name: "MOVDstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVD", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ... {name: "MOVDstorezero", argLength: 2, reg: gpstorezero, asm: "MOVD", aux: "SymOff", typ: "Mem"}, // store zero 8 bytes to ...
{name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp | sb}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp | sb}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB
......
src/cmd/compile/internal/ssa/opGen.go
View file @ 806cacc7
...@@ -951,10 +951,10 @@ const ( ...@@ -951,10 +951,10 @@ const (
OpPPC64MOVDstore OpPPC64MOVDstore
OpPPC64FMOVDstore OpPPC64FMOVDstore
OpPPC64FMOVSstore OpPPC64FMOVSstore
OpPPC64MOVBstoreconst OpPPC64MOVBstorezero
OpPPC64MOVHstoreconst OpPPC64MOVHstorezero
OpPPC64MOVWstoreconst OpPPC64MOVWstorezero
OpPPC64MOVDstoreconst OpPPC64MOVDstorezero
OpPPC64MOVDaddr OpPPC64MOVDaddr
OpPPC64MOVDconst OpPPC64MOVDconst
OpPPC64MOVWconst OpPPC64MOVWconst
...@@ -11937,8 +11937,8 @@ var opcodeTable = [...]opInfo{ ...@@ -11937,8 +11937,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVBstoreconst", name: "MOVBstorezero",
auxType: auxSymValAndOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: ppc64.AMOVB, asm: ppc64.AMOVB,
reg: regInfo{ reg: regInfo{
...@@ -11948,8 +11948,8 @@ var opcodeTable = [...]opInfo{ ...@@ -11948,8 +11948,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVHstoreconst", name: "MOVHstorezero",
auxType: auxSymValAndOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: ppc64.AMOVH, asm: ppc64.AMOVH,
reg: regInfo{ reg: regInfo{
...@@ -11959,8 +11959,8 @@ var opcodeTable = [...]opInfo{ ...@@ -11959,8 +11959,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVWstoreconst", name: "MOVWstorezero",
auxType: auxSymValAndOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: ppc64.AMOVW, asm: ppc64.AMOVW,
reg: regInfo{ reg: regInfo{
...@@ -11970,8 +11970,8 @@ var opcodeTable = [...]opInfo{ ...@@ -11970,8 +11970,8 @@ var opcodeTable = [...]opInfo{
}, },
}, },
{ {
name: "MOVDstoreconst", name: "MOVDstorezero",
auxType: auxSymValAndOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: ppc64.AMOVD, asm: ppc64.AMOVD,
reg: regInfo{ reg: regInfo{
......
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