e100.c 65 KB
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/*******************************************************************************

  
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  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
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  This program is free software; you can redistribute it and/or modify it 
  under the terms of the GNU General Public License as published by the Free 
  Software Foundation; either version 2 of the License, or (at your option) 
  any later version.
  
  This program is distributed in the hope that it will be useful, but WITHOUT 
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
  more details.
  
  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc., 59 
  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  
  The full GNU General Public License is included in this distribution in the
  file called LICENSE.
  
  Contact Information:
  Linux NICS <linux.nics@intel.com>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

/*
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 *	e100.c: Intel(R) PRO/100 ethernet driver
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 *
 *	(Re)written 2003 by scott.feldman@intel.com.  Based loosely on
 *	original e100 driver, but better described as a munging of
 *	e100, e1000, eepro100, tg3, 8139cp, and other drivers.
 *
 *	References:
 *		Intel 8255x 10/100 Mbps Ethernet Controller Family,
 *		Open Source Software Developers Manual,
 *		http://sourceforge.net/projects/e1000
 *
 *
 *	                      Theory of Operation
 *
 *	I.   General
 *
 *	The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
 *	controller family, which includes the 82557, 82558, 82559, 82550,
 *	82551, and 82562 devices.  82558 and greater controllers
 *	integrate the Intel 82555 PHY.  The controllers are used in
 *	server and client network interface cards, as well as in
 *	LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
 *	configurations.  8255x supports a 32-bit linear addressing
 *	mode and operates at 33Mhz PCI clock rate.
 *
 *	II.  Driver Operation
 *
 *	Memory-mapped mode is used exclusively to access the device's
 *	shared-memory structure, the Control/Status Registers (CSR). All
 *	setup, configuration, and control of the device, including queuing
 *	of Tx, Rx, and configuration commands is through the CSR.
 *	cmd_lock serializes accesses to the CSR command register.  cb_lock
 *	protects the shared Command Block List (CBL).
 *
 *	8255x is highly MII-compliant and all access to the PHY go
 *	through the Management Data Interface (MDI).  Consequently, the
 *	driver leverages the mii.c library shared with other MII-compliant
 *	devices.
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 *
 *	Big- and Little-Endian byte order as well as 32- and 64-bit
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 *	archs are supported.  Weak-ordered memory and non-cache-coherent
 *	archs are supported.
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 *
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 *	III. Transmit
 *
 *	A Tx skb is mapped and hangs off of a TCB.  TCBs are linked
 *	together in a fixed-size ring (CBL) thus forming the flexible mode
 *	memory structure.  A TCB marked with the suspend-bit indicates
 *	the end of the ring.  The last TCB processed suspends the
 *	controller, and the controller can be restarted by issue a CU
 *	resume command to continue from the suspend point, or a CU start
 *	command to start at a given position in the ring.
 *
 *	Non-Tx commands (config, multicast setup, etc) are linked
 *	into the CBL ring along with Tx commands.  The common structure
 *	used for both Tx and non-Tx commands is the Command Block (CB).
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 *
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 *	cb_to_use is the next CB to use for queuing a command; cb_to_clean
 *	is the next CB to check for completion; cb_to_send is the first
 *	CB to start on in case of a previous failure to resume.  CB clean
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 *	up happens in interrupt context in response to a CU interrupt.
 *	cbs_avail keeps track of number of free CB resources available.
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 *
 * 	Hardware padding of short packets to minimum packet size is
 * 	enabled.  82557 pads with 7Eh, while the later controllers pad
 * 	with 00h.
 *
 *	IV.  Recieve
 *
 *	The Receive Frame Area (RFA) comprises a ring of Receive Frame
 *	Descriptors (RFD) + data buffer, thus forming the simplified mode
 *	memory structure.  Rx skbs are allocated to contain both the RFD
 *	and the data buffer, but the RFD is pulled off before the skb is
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 *	indicated.  The data buffer is aligned such that encapsulated
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 *	protocol headers are u32-aligned.  Since the RFD is part of the
 *	mapped shared memory, and completion status is contained within
 *	the RFD, the RFD must be dma_sync'ed to maintain a consistent
 *	view from software and hardware.
 *
 *	Under typical operation, the  receive unit (RU) is start once,
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 *	and the controller happily fills RFDs as frames arrive.  If
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 *	replacement RFDs cannot be allocated, or the RU goes non-active,
 *	the RU must be restarted.  Frame arrival generates an interrupt,
 *	and Rx indication and re-allocation happen in the same context,
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 *	therefore no locking is required.  A software-generated interrupt
 *	is generated from the watchdog to recover from a failed allocation
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 *	senario where all Rx resources have been indicated and none re-
 *	placed.
 *
 *	V.   Miscellaneous
 *
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 * 	VLAN offloading of tagging, stripping and filtering is not
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 * 	supported, but driver will accommodate the extra 4-byte VLAN tag
 * 	for processing by upper layers.  Tx/Rx Checksum offloading is not
 * 	supported.  Tx Scatter/Gather is not supported.  Jumbo Frames is
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 * 	not supported (hardware limitation).
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 *
 * 	MagicPacket(tm) WoL support is enabled/disabled via ethtool.
 *
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 * 	Thanks to JC (jchapman@katalix.com) for helping with
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 * 	testing/troubleshooting the development driver.
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 *
 * 	TODO:
 * 	o several entry points race with dev->close
 * 	o check for tx-no-resources/stop Q races with tx clean/wake Q
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 */

#include <linux/config.h>
#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
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#include <linux/string.h>
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#include <asm/unaligned.h>


#define DRV_NAME		"e100"
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#define DRV_EXT		"-NAPI"
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#define DRV_VERSION		"3.2.3-k2"DRV_EXT
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#define DRV_DESCRIPTION		"Intel(R) PRO/100 Network Driver"
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#define DRV_COPYRIGHT		"Copyright(c) 1999-2004 Intel Corporation"
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#define PFX			DRV_NAME ": "

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#define E100_WATCHDOG_PERIOD	(2 * HZ)
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#define E100_NAPI_WEIGHT	16

MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_AUTHOR(DRV_COPYRIGHT);
MODULE_LICENSE("GPL");

static int debug = 3;
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module_param(debug, int, 0);
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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
#define DPRINTK(nlevel, klevel, fmt, args...) \
	(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
	printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
		__FUNCTION__ , ## args))

#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
	PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
	PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
static struct pci_device_id e100_id_table[] = {
	INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
	INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
	INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
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	INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
	INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
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	INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
	INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
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	INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
	INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
	INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
	INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, e100_id_table);

enum mac {
	mac_82557_D100_A  = 0,
	mac_82557_D100_B  = 1,
	mac_82557_D100_C  = 2,
	mac_82558_D101_A4 = 4,
	mac_82558_D101_B0 = 5,
	mac_82559_D101M   = 8,
	mac_82559_D101S   = 9,
	mac_82550_D102    = 12,
	mac_82550_D102_C  = 13,
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	mac_82551_E       = 14,
	mac_82551_F       = 15,
	mac_82551_10      = 16,
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	mac_unknown       = 0xFF,
};

enum phy {
	phy_100a     = 0x000003E0,
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	phy_100c     = 0x035002A8,
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	phy_82555_tx = 0x015002A8,
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	phy_nsc_tx   = 0x5C002000,
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	phy_82562_et = 0x033002A8,
	phy_82562_em = 0x032002A8,
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	phy_82562_ek = 0x031002A8,
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	phy_82562_eh = 0x017002A8,
	phy_unknown  = 0xFFFFFFFF,
};

/* CSR (Control/Status Registers) */
struct csr {
	struct {
		u8 status;
		u8 stat_ack;
		u8 cmd_lo;
		u8 cmd_hi;
		u32 gen_ptr;
	} scb;
	u32 port;
	u16 flash_ctrl;
	u8 eeprom_ctrl_lo;
	u8 eeprom_ctrl_hi;
	u32 mdi_ctrl;
	u32 rx_dma_count;
};

enum scb_status {
	rus_ready        = 0x10,
	rus_mask         = 0x3C,
};

enum scb_stat_ack {
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	stat_ack_not_ours    = 0x00,
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	stat_ack_sw_gen      = 0x04,
	stat_ack_rnr         = 0x10,
	stat_ack_cu_idle     = 0x20,
	stat_ack_frame_rx    = 0x40,
	stat_ack_cu_cmd_done = 0x80,
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	stat_ack_not_present = 0xFF,
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	stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
	stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
};

enum scb_cmd_hi {
	irq_mask_none = 0x00,
	irq_mask_all  = 0x01,
	irq_sw_gen    = 0x02,
};

enum scb_cmd_lo {
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	cuc_nop        = 0x00,
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	ruc_start      = 0x01,
	ruc_load_base  = 0x06,
	cuc_start      = 0x10,
	cuc_resume     = 0x20,
	cuc_dump_addr  = 0x40,
	cuc_dump_stats = 0x50,
	cuc_load_base  = 0x60,
	cuc_dump_reset = 0x70,
};

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enum cuc_dump {
	cuc_dump_complete       = 0x0000A005,
	cuc_dump_reset_complete = 0x0000A007,
};
		
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enum port {
	software_reset  = 0x0000,
	selftest        = 0x0001,
	selective_reset = 0x0002,
};

enum eeprom_ctrl_lo {
	eesk = 0x01,
	eecs = 0x02,
	eedi = 0x04,
	eedo = 0x08,
};

enum mdi_ctrl {
	mdi_write = 0x04000000,
	mdi_read  = 0x08000000,
	mdi_ready = 0x10000000,
};

enum eeprom_op {
	op_write = 0x05,
	op_read  = 0x06,
	op_ewds  = 0x10,
	op_ewen  = 0x13,
};

enum eeprom_offsets {
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	eeprom_cnfg_mdix  = 0x03,
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	eeprom_id         = 0x0A,
	eeprom_config_asf = 0x0D,
	eeprom_smbus_addr = 0x90,
};

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enum eeprom_cnfg_mdix {
	eeprom_mdix_enabled = 0x0080,
};

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enum eeprom_id {
	eeprom_id_wol = 0x0020,
};

enum eeprom_config_asf {
	eeprom_asf = 0x8000,
	eeprom_gcl = 0x4000,
};

enum cb_status {
	cb_complete = 0x8000,
	cb_ok       = 0x2000,
};

enum cb_command {
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	cb_nop    = 0x0000,
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	cb_iaaddr = 0x0001,
	cb_config = 0x0002,
	cb_multi  = 0x0003,
	cb_tx     = 0x0004,
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	cb_ucode  = 0x0005,
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	cb_dump   = 0x0006,
	cb_tx_sf  = 0x0008,
	cb_cid    = 0x1f00,
	cb_i      = 0x2000,
	cb_s      = 0x4000,
	cb_el     = 0x8000,
};

struct rfd {
	u16 status;
	u16 command;
	u32 link;
	u32 rbd;
	u16 actual_size;
	u16 size;
};

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struct rx {
	struct rx *next, *prev;
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	struct sk_buff *skb;
	dma_addr_t dma_addr;
};

#if defined(__BIG_ENDIAN_BITFIELD)
#define X(a,b)	b,a
#else
#define X(a,b)	a,b
#endif
struct config {
/*0*/	u8 X(byte_count:6, pad0:2);
/*1*/	u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
/*2*/	u8 adaptive_ifs;
/*3*/	u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
	   term_write_cache_line:1), pad3:4);
/*4*/	u8 X(rx_dma_max_count:7, pad4:1);
/*5*/	u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
/*6*/	u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
	   tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
	   rx_discard_overruns:1), rx_save_bad_frames:1);
/*7*/	u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
	   pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
	   tx_dynamic_tbd:1);
/*8*/	u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
/*9*/	u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
	   link_status_wake:1), arp_wake:1), mcmatch_wake:1);
/*10*/	u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
	   loopback:2);
/*11*/	u8 X(linear_priority:3, pad11:5);
/*12*/	u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
/*13*/	u8 ip_addr_lo;
/*14*/	u8 ip_addr_hi;
/*15*/	u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
	   wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
	   pad15_2:1), crs_or_cdt:1);
/*16*/	u8 fc_delay_lo;
/*17*/	u8 fc_delay_hi;
/*18*/	u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
	   rx_long_ok:1), fc_priority_threshold:3), pad18:1);
/*19*/	u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
	   fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
	   full_duplex_force:1), full_duplex_pin:1);
/*20*/	u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
/*21*/	u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
/*22*/	u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
	u8 pad_d102[9];
};

#define E100_MAX_MULTICAST_ADDRS	64
struct multi {
	u16 count;
	u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
};

/* Important: keep total struct u32-aligned */
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#define UCODE_SIZE			134
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struct cb {
	u16 status;
	u16 command;
	u32 link;
	union {
		u8 iaaddr[ETH_ALEN];
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		u32 ucode[UCODE_SIZE];
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		struct config config;
		struct multi multi;
		struct {
			u32 tbd_array;
			u16 tcb_byte_count;
			u8 threshold;
			u8 tbd_count;
			struct {
				u32 buf_addr;
				u16 size;
				u16 eol;
			} tbd;
		} tcb;
		u32 dump_buffer_addr;
	} u;
	struct cb *next, *prev;
	dma_addr_t dma_addr;
	struct sk_buff *skb;
};

enum loopback {
	lb_none = 0, lb_mac = 1, lb_phy = 3,
};

struct stats {
	u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
		tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
		tx_multiple_collisions, tx_total_collisions;
	u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
		rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
		rx_short_frame_errors;
	u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
	u16 xmt_tco_frames, rcv_tco_frames;
	u32 complete;
};

struct mem {
	struct {
		u32 signature;
		u32 result;
	} selftest;
	struct stats stats;
	u8 dump_buf[596];
};

struct param_range {
	u32 min;
	u32 max;
	u32 count;
};

struct params {
	struct param_range rfds;
	struct param_range cbs;
};

struct nic {
	/* Begin: frequently used values: keep adjacent for cache effect */
	u32 msg_enable				____cacheline_aligned;
	struct net_device *netdev;
	struct pci_dev *pdev;
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	struct rx *rxs				____cacheline_aligned;
	struct rx *rx_to_use;
	struct rx *rx_to_clean;
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	struct rfd blank_rfd;
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	int ru_running;

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	spinlock_t cb_lock			____cacheline_aligned;
	spinlock_t cmd_lock;
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	struct csr __iomem *csr;
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	enum scb_cmd_lo cuc_cmd;
	unsigned int cbs_avail;
	struct cb *cbs;
	struct cb *cb_to_use;
	struct cb *cb_to_send;
	struct cb *cb_to_clean;
	u16 tx_command;
	/* End: frequently used values: keep adjacent for cache effect */

	enum {
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		ich                = (1 << 0),
		promiscuous        = (1 << 1),
		multicast_all      = (1 << 2),
		wol_magic          = (1 << 3),
		ich_10h_workaround = (1 << 4),
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	} flags					____cacheline_aligned;
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	enum mac mac;
	enum phy phy;
	struct params params;
	struct net_device_stats net_stats;
	struct timer_list watchdog;
	struct timer_list blink_timer;
	struct mii_if_info mii;
	enum loopback loopback;

	struct mem *mem;
	dma_addr_t dma_addr;

	dma_addr_t cbs_dma_addr;
	u8 adaptive_ifs;
	u8 tx_threshold;
	u32 tx_frames;
	u32 tx_collisions;
	u32 tx_deferred;
	u32 tx_single_collisions;
	u32 tx_multiple_collisions;
	u32 tx_fc_pause;
	u32 tx_tco_frames;

	u32 rx_fc_pause;
	u32 rx_fc_unsupported;
	u32 rx_tco_frames;
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	u32 rx_over_length_errors;
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	u8 rev_id;
	u16 leds;
	u16 eeprom_wc;
	u16 eeprom[256];
};

static inline void e100_write_flush(struct nic *nic)
{
	/* Flush previous PCI writes through intermediate bridges
	 * by doing a benign read */
	(void)readb(&nic->csr->scb.status);
}

static inline void e100_enable_irq(struct nic *nic)
{
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	unsigned long flags;

	spin_lock_irqsave(&nic->cmd_lock, flags);
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	writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
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	spin_unlock_irqrestore(&nic->cmd_lock, flags);
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	e100_write_flush(nic);
}

static inline void e100_disable_irq(struct nic *nic)
{
587 588 589
	unsigned long flags;

	spin_lock_irqsave(&nic->cmd_lock, flags);
590
	writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
591
	spin_unlock_irqrestore(&nic->cmd_lock, flags);
592 593 594 595 596 597 598 599 600
	e100_write_flush(nic);
}

static void e100_hw_reset(struct nic *nic)
{
	/* Put CU and RU into idle with a selective reset to get
	 * device off of PCI bus */
	writel(selective_reset, &nic->csr->port);
	e100_write_flush(nic); udelay(20);
601

602 603 604
	/* Now fully reset device */
	writel(software_reset, &nic->csr->port);
	e100_write_flush(nic); udelay(20);
605

606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
	/* Mask off our interrupt line - it's unmasked after reset */
	e100_disable_irq(nic);
}

static int e100_self_test(struct nic *nic)
{
	u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);

	/* Passing the self-test is a pretty good indication
	 * that the device can DMA to/from host memory */

	nic->mem->selftest.signature = 0;
	nic->mem->selftest.result = 0xFFFFFFFF;

	writel(selftest | dma_addr, &nic->csr->port);
	e100_write_flush(nic);
	/* Wait 10 msec for self-test to complete */
	set_current_state(TASK_UNINTERRUPTIBLE);
	schedule_timeout(HZ / 100 + 1);

	/* Interrupts are enabled after self-test */
	e100_disable_irq(nic);

	/* Check results of self-test */
	if(nic->mem->selftest.result != 0) {
		DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
			nic->mem->selftest.result);
		return -ETIMEDOUT;
	}
	if(nic->mem->selftest.signature == 0) {
		DPRINTK(HW, ERR, "Self-test failed: timed out\n");
		return -ETIMEDOUT;
	}

	return 0;
}

static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
{
	u32 cmd_addr_data[3];
	u8 ctrl;
	int i, j;

	/* Three cmds: write/erase enable, write data, write/erase disable */
	cmd_addr_data[0] = op_ewen << (addr_len - 2);
651 652
	cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
		cpu_to_le16(data);
653 654 655 656 657 658 659 660 661 662 663 664 665 666
	cmd_addr_data[2] = op_ewds << (addr_len - 2);

	/* Bit-bang cmds to write word to eeprom */
	for(j = 0; j < 3; j++) {

		/* Chip select */
		writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
		e100_write_flush(nic); udelay(4);

		for(i = 31; i >= 0; i--) {
			ctrl = (cmd_addr_data[j] & (1 << i)) ?
				eecs | eedi : eecs;
			writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
			e100_write_flush(nic); udelay(4);
667

668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699
			writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
			e100_write_flush(nic); udelay(4);
		}
		/* Wait 10 msec for cmd to complete */
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_timeout(HZ / 100 + 1);

		/* Chip deselect */
		writeb(0, &nic->csr->eeprom_ctrl_lo);
		e100_write_flush(nic); udelay(4);
	}
};

/* General technique stolen from the eepro100 driver - very clever */
static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
{
	u32 cmd_addr_data;
	u16 data = 0;
	u8 ctrl;
	int i;

	cmd_addr_data = ((op_read << *addr_len) | addr) << 16;

	/* Chip select */
	writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
	e100_write_flush(nic); udelay(4);

	/* Bit-bang to read word from eeprom */
	for(i = 31; i >= 0; i--) {
		ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
		writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
		e100_write_flush(nic); udelay(4);
700
		
701 702
		writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
		e100_write_flush(nic); udelay(4);
703
		
704 705 706 707 708 709 710
		/* Eeprom drives a dummy zero to EEDO after receiving
		 * complete address.  Use this to adjust addr_len. */
		ctrl = readb(&nic->csr->eeprom_ctrl_lo);
		if(!(ctrl & eedo) && i > 16) {
			*addr_len -= (i - 16);
			i = 17;
		}
711
		
712 713 714 715 716 717 718
		data = (data << 1) | (ctrl & eedo ? 1 : 0);
	}

	/* Chip deselect */
	writeb(0, &nic->csr->eeprom_ctrl_lo);
	e100_write_flush(nic); udelay(4);

719
	return le16_to_cpu(data);
720 721 722 723 724 725 726 727 728 729
};

/* Load entire EEPROM image into driver cache and validate checksum */
static int e100_eeprom_load(struct nic *nic)
{
	u16 addr, addr_len = 8, checksum = 0;

	/* Try reading with an 8-bit addr len to discover actual addr len */
	e100_eeprom_read(nic, &addr_len, 0);
	nic->eeprom_wc = 1 << addr_len;
730

731 732 733
	for(addr = 0; addr < nic->eeprom_wc; addr++) {
		nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
		if(addr < nic->eeprom_wc - 1)
734
			checksum += cpu_to_le16(nic->eeprom[addr]);
735 736 737 738
	}

	/* The checksum, stored in the last word, is calculated such that
	 * the sum of words should be 0xBABA */
739
	checksum = le16_to_cpu(0xBABA - checksum);
740 741 742 743
	if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
		DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
		return -EAGAIN;
	}
744

745 746 747 748 749 750 751 752 753 754 755
	return 0;
}

/* Save (portion of) driver EEPROM cache to device and update checksum */
static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
{
	u16 addr, addr_len = 8, checksum = 0;

	/* Try reading with an 8-bit addr len to discover actual addr len */
	e100_eeprom_read(nic, &addr_len, 0);
	nic->eeprom_wc = 1 << addr_len;
756

757 758
	if(start + count >= nic->eeprom_wc)
		return -EINVAL;
759

760 761 762 763 764 765
	for(addr = start; addr < start + count; addr++)
		e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);

	/* The checksum, stored in the last word, is calculated such that
	 * the sum of words should be 0xBABA */
	for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
766 767 768 769
		checksum += cpu_to_le16(nic->eeprom[addr]);
	nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
	e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
		nic->eeprom[nic->eeprom_wc - 1]);
770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828

	return 0;
}

#define E100_WAIT_SCB_TIMEOUT 40
static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
{
	unsigned long flags;
	unsigned int i;
	int err = 0;

	spin_lock_irqsave(&nic->cmd_lock, flags);

	/* Previous command is accepted when SCB clears */
	for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
		if(likely(!readb(&nic->csr->scb.cmd_lo)))
			break;
		cpu_relax();
		if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
			udelay(5);
	}
	if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
		err = -EAGAIN;
		goto err_unlock;
	}

	if(unlikely(cmd != cuc_resume))
		writel(dma_addr, &nic->csr->scb.gen_ptr);
	writeb(cmd, &nic->csr->scb.cmd_lo);

err_unlock:
	spin_unlock_irqrestore(&nic->cmd_lock, flags);

	return err;
}

static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
	void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
{
	struct cb *cb;
	unsigned long flags;
	int err = 0;

	spin_lock_irqsave(&nic->cb_lock, flags);

	if(unlikely(!nic->cbs_avail)) {
		err = -ENOMEM;
		goto err_unlock;
	}

	cb = nic->cb_to_use;
	nic->cb_to_use = cb->next;
	nic->cbs_avail--;
	cb->skb = skb;

	if(unlikely(!nic->cbs_avail))
		err = -ENOSPC;

	cb_prepare(nic, cb, skb);
829

830 831 832
	/* Order is important otherwise we'll be in a race with h/w:
	 * set S-bit in current first, then clear S-bit in previous. */
	cb->command |= cpu_to_le16(cb_s);
833
	wmb();
834 835 836
	cb->prev->command &= cpu_to_le16(~cb_s);

	while(nic->cb_to_send != nic->cb_to_use) {
837 838
		if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
			nic->cb_to_send->dma_addr))) {
839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868
			/* Ok, here's where things get sticky.  It's
			 * possible that we can't schedule the command
			 * because the controller is too busy, so
			 * let's just queue the command and try again
			 * when another command is scheduled. */
			break;
		} else {
			nic->cuc_cmd = cuc_resume;
			nic->cb_to_send = nic->cb_to_send->next;
		}
	}

err_unlock:
	spin_unlock_irqrestore(&nic->cb_lock, flags);

	return err;
}

static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
{
	u32 data_out = 0;
	unsigned int i;

	writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);

	for(i = 0; i < 100; i++) {
		udelay(20);
		if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
			break;
	}
869

870 871 872 873 874 875 876 877
	DPRINTK(HW, DEBUG,
		"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
		dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
	return (u16)data_out;
}

static int mdio_read(struct net_device *netdev, int addr, int reg)
{
878
	return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
879 880 881 882
}

static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
{
883
	mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
884 885
}

886 887 888 889 890 891 892 893 894 895 896
static void e100_get_defaults(struct nic *nic)
{
	struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
	struct param_range cbs  = { .min = 64, .max = 256, .count = 64 };

	pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
	/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
	nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
	if(nic->mac == mac_unknown)
		nic->mac = mac_82557_D100_A;

897 898 899
	nic->params.rfds = rfds;
	nic->params.cbs = cbs;

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918
	/* Quadwords to DMA into FIFO before starting frame transmit */
	nic->tx_threshold = 0xE0;

	nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
		((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));

	/* Template for a freshly allocated RFD */
	nic->blank_rfd.command = cpu_to_le16(cb_el);
	nic->blank_rfd.rbd = 0xFFFFFFFF;
	nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);

	/* MII setup */
	nic->mii.phy_id_mask = 0x1F;
	nic->mii.reg_num_mask = 0x1F;
	nic->mii.dev = nic->netdev;
	nic->mii.mdio_read = mdio_read;
	nic->mii.mdio_write = mdio_write;
}

919 920 921 922 923 924
static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
	struct config *config = &cb->u.config;
	u8 *c = (u8 *)config;

	cb->command = cpu_to_le16(cb_config);
925

926
	memset(config, 0, sizeof(struct config));
927

928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957
	config->byte_count = 0x16;		/* bytes in this struct */
	config->rx_fifo_limit = 0x8;		/* bytes in FIFO before DMA */
	config->direct_rx_dma = 0x1;		/* reserved */
	config->standard_tcb = 0x1;		/* 1=standard, 0=extended */
	config->standard_stat_counter = 0x1;	/* 1=standard, 0=extended */
	config->rx_discard_short_frames = 0x1;	/* 1=discard, 0=pass */
	config->tx_underrun_retry = 0x3;	/* # of underrun retries */
	config->mii_mode = 0x1;			/* 1=MII mode, 0=503 mode */
	config->pad10 = 0x6;
	config->no_source_addr_insertion = 0x1;	/* 1=no, 0=yes */
	config->preamble_length = 0x2;		/* 0=1, 1=3, 2=7, 3=15 bytes */
	config->ifs = 0x6;			/* x16 = inter frame spacing */
	config->ip_addr_hi = 0xF2;		/* ARP IP filter - not used */
	config->pad15_1 = 0x1;
	config->pad15_2 = 0x1;
	config->crs_or_cdt = 0x0;		/* 0=CRS only, 1=CRS or CDT */
	config->fc_delay_hi = 0x40;		/* time delay for fc frame */
	config->tx_padding = 0x1;		/* 1=pad short frames */
	config->fc_priority_threshold = 0x7;	/* 7=priority fc disabled */
	config->pad18 = 0x1;
	config->full_duplex_pin = 0x1;		/* 1=examine FDX# pin */
	config->pad20_1 = 0x1F;
	config->fc_priority_location = 0x1;	/* 1=byte#31, 0=byte#19 */
	config->pad21_1 = 0x5;

	config->adaptive_ifs = nic->adaptive_ifs;
	config->loopback = nic->loopback;

	if(nic->mii.force_media && nic->mii.full_duplex)
		config->full_duplex_force = 0x1;	/* 1=force, 0=auto */
958

959 960 961 962 963 964 965 966
	if(nic->flags & promiscuous || nic->loopback) {
		config->rx_save_bad_frames = 0x1;	/* 1=save, 0=discard */
		config->rx_discard_short_frames = 0x0;	/* 1=discard, 0=save */
		config->promiscuous_mode = 0x1;		/* 1=on, 0=off */
	}

	if(nic->flags & multicast_all)
		config->multicast_all = 0x1;		/* 1=accept, 0=no */
967

968 969 970 971 972 973 974 975 976 977 978 979 980
	if(!(nic->flags & wol_magic))
		config->magic_packet_disable = 0x1;	/* 1=off, 0=on */

	if(nic->mac >= mac_82558_D101_A4) {
		config->fc_disable = 0x1;	/* 1=Tx fc off, 0=Tx fc on */
		config->mwi_enable = 0x1;	/* 1=enable, 0=disable */
		config->standard_tcb = 0x0;	/* 1=standard, 0=extended */
		config->rx_long_ok = 0x1;	/* 1=VLANs ok, 0=standard */
		if(nic->mac >= mac_82559_D101M)
			config->tno_intr = 0x1;		/* TCO stats enable */
		else
			config->standard_stat_counter = 0x0;
	}
981

982 983 984 985 986 987 988 989
	DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
		c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
	DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
		c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
	DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
		c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
}

990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
	int i;
	static const u32 ucode[UCODE_SIZE] = {
		/* NFS packets are misinterpreted as TCO packets and
		 * incorrectly routed to the BMC over SMBus.  This
		 * microcode patch checks the fragmented IP bit in the
		 * NFS/UDP header to distinguish between NFS and TCO. */
		0x0EF70E36, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF, 0x1FFF1FFF,
		0x1FFF1FFF, 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000,
		0x00906EFD, 0x00900EFD,	0x00E00EF8,
	};

	if(nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
		for(i = 0; i < UCODE_SIZE; i++)
			cb->u.ucode[i] = cpu_to_le32(ucode[i]);
		cb->command = cpu_to_le16(cb_ucode);
	} else
		cb->command = cpu_to_le16(cb_nop);
}

1011 1012 1013 1014
static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
	struct sk_buff *skb)
{
	cb->command = cpu_to_le16(cb_iaaddr);
1015
	memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047
}

static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
	cb->command = cpu_to_le16(cb_dump);
	cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
		offsetof(struct mem, dump_buf));
}

#define NCONFIG_AUTO_SWITCH	0x0080
#define MII_NSC_CONG		MII_RESV1
#define NSC_CONG_ENABLE		0x0100
#define NSC_CONG_TXREADY	0x0400
#define ADVERTISE_FC_SUPPORTED	0x0400
static int e100_phy_init(struct nic *nic)
{
	struct net_device *netdev = nic->netdev;
	u32 addr;
	u16 bmcr, stat, id_lo, id_hi, cong;

	/* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
	for(addr = 0; addr < 32; addr++) {
		nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
		bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
		stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
		stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
		if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
			break;
	}
	DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
	if(addr == 32)
		return -EAGAIN;
1048

1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
	/* Selected the phy and isolate the rest */
	for(addr = 0; addr < 32; addr++) {
		if(addr != nic->mii.phy_id) {
			mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
		} else {
			bmcr = mdio_read(netdev, addr, MII_BMCR);
			mdio_write(netdev, addr, MII_BMCR,
				bmcr & ~BMCR_ISOLATE);
		}
	}
1059

1060 1061 1062 1063 1064
	/* Get phy ID */
	id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
	id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
	nic->phy = (u32)id_hi << 16 | (u32)id_lo;
	DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1065

1066 1067 1068
	/* Handle National tx phys */
#define NCS_PHY_MODEL_MASK	0xFFF0FFFF
	if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1069 1070 1071 1072 1073 1074
		/* Disable congestion control */
		cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
		cong |= NSC_CONG_TXREADY;
		cong &= ~NSC_CONG_ENABLE;
		mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
	}
1075

1076 1077 1078
	if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) && 
		(mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) && 
		(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled)))
1079
		/* enable/disable MDI/MDI-X auto-switching */
1080
		mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1081
			nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1082 1083 1084 1085 1086 1087 1088

	return 0;
}

static int e100_hw_init(struct nic *nic)
{
	int err;
1089

1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101
	e100_hw_reset(nic);

	DPRINTK(HW, ERR, "e100_hw_init\n");
	if(!in_interrupt() && (err = e100_self_test(nic)))
		return err;

	if((err = e100_phy_init(nic)))
		return err;
	if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
		return err;
	if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
		return err;
1102 1103
	if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
		return err;
1104 1105 1106 1107
	if((err = e100_exec_cb(nic, NULL, e100_configure)))
		return err;
	if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
		return err;
1108
	if((err = e100_exec_cmd(nic, cuc_dump_addr,
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133
		nic->dma_addr + offsetof(struct mem, stats))))
		return err;
	if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
		return err;

	e100_disable_irq(nic);

	return 0;
}

static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
	struct net_device *netdev = nic->netdev;
	struct dev_mc_list *list = netdev->mc_list;
	u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);

	cb->command = cpu_to_le16(cb_multi);
	cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
	for(i = 0; list && i < count; i++, list = list->next)
		memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
			ETH_ALEN);
}

static void e100_set_multicast_list(struct net_device *netdev)
{
1134
	struct nic *nic = netdev_priv(netdev);
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162

	DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
		netdev->mc_count, netdev->flags);

	if(netdev->flags & IFF_PROMISC)
		nic->flags |= promiscuous;
	else
		nic->flags &= ~promiscuous;

	if(netdev->flags & IFF_ALLMULTI ||
		netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
		nic->flags |= multicast_all;
	else
		nic->flags &= ~multicast_all;

	e100_exec_cb(nic, NULL, e100_configure);
	e100_exec_cb(nic, NULL, e100_multi);
}

static void e100_update_stats(struct nic *nic)
{
	struct net_device_stats *ns = &nic->net_stats;
	struct stats *s = &nic->mem->stats;
	u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
		(nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
		&s->complete;

	/* Device's stats reporting may take several microseconds to
1163
	 * complete, so where always waiting for results of the
1164 1165
	 * previous command. */

1166
	if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177
		*complete = 0;
		nic->tx_frames = le32_to_cpu(s->tx_good_frames);
		nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
		ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
		ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
		ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
		ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
		ns->collisions += nic->tx_collisions;
		ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
			le32_to_cpu(s->tx_lost_crs);
		ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1178 1179
		ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
			nic->rx_over_length_errors;
1180 1181
		ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
		ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1182
		ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
		ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
		ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
			le32_to_cpu(s->rx_alignment_errors) +
			le32_to_cpu(s->rx_short_frame_errors) +
			le32_to_cpu(s->rx_cdt_errors);
		nic->tx_deferred += le32_to_cpu(s->tx_deferred);
		nic->tx_single_collisions +=
			le32_to_cpu(s->tx_single_collisions);
		nic->tx_multiple_collisions +=
			le32_to_cpu(s->tx_multiple_collisions);
		if(nic->mac >= mac_82558_D101_A4) {
			nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
			nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
			nic->rx_fc_unsupported +=
				le32_to_cpu(s->fc_rcv_unsupported);
			if(nic->mac >= mac_82559_D101M) {
				nic->tx_tco_frames +=
					le16_to_cpu(s->xmt_tco_frames);
				nic->rx_tco_frames +=
					le16_to_cpu(s->rcv_tco_frames);
			}
		}
	}

	e100_exec_cmd(nic, cuc_dump_reset, 0);
}

static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
{
	/* Adjust inter-frame-spacing (IFS) between two transmits if
	 * we're getting collisions on a half-duplex connection. */

	if(duplex == DUPLEX_HALF) {
		u32 prev = nic->adaptive_ifs;
		u32 min_frames = (speed == SPEED_100) ? 1000 : 100;

		if((nic->tx_frames / 32 < nic->tx_collisions) &&
		   (nic->tx_frames > min_frames)) {
			if(nic->adaptive_ifs < 60)
				nic->adaptive_ifs += 5;
		} else if (nic->tx_frames < min_frames) {
			if(nic->adaptive_ifs >= 5)
				nic->adaptive_ifs -= 5;
		}
		if(nic->adaptive_ifs != prev)
			e100_exec_cb(nic, NULL, e100_configure);
	}
}

static void e100_watchdog(unsigned long data)
{
	struct nic *nic = (struct nic *)data;
	struct ethtool_cmd cmd;

	DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);

	/* mii library handles link maintenance tasks */

	mii_ethtool_gset(&nic->mii, &cmd);

	if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
		DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
			cmd.speed == SPEED_100 ? "100" : "10",
			cmd.duplex == DUPLEX_FULL ? "full" : "half");
	} else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
		DPRINTK(LINK, INFO, "link down\n");
	}
1250

1251
	mii_check_link(&nic->mii);
1252 1253

	/* Software generated interrupt to recover from (rare) Rx
1254 1255 1256 1257 1258 1259 1260
	* allocation failure.
	* Unfortunately have to use a spinlock to not re-enable interrupts
	* accidentally, due to hardware that shares a register between the
	* interrupt mask bit and the SW Interrupt generation bit */
	spin_lock_irq(&nic->cmd_lock);
	writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
	spin_unlock_irq(&nic->cmd_lock);
1261 1262 1263 1264 1265 1266 1267 1268 1269
	e100_write_flush(nic);

	e100_update_stats(nic);
	e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);

	if(nic->mac <= mac_82557_D100_C)
		/* Issue a multicast command to workaround a 557 lock up */
		e100_set_multicast_list(nic->netdev);

1270 1271 1272 1273 1274 1275
	if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
		/* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
		nic->flags |= ich_10h_workaround;
	else
		nic->flags &= ~ich_10h_workaround;

1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
	mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
}

static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
	struct sk_buff *skb)
{
	cb->command = nic->tx_command;
	cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
	cb->u.tcb.tcb_byte_count = 0;
	cb->u.tcb.threshold = nic->tx_threshold;
	cb->u.tcb.tbd_count = 1;
	cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
		skb->data, skb->len, PCI_DMA_TODEVICE));
	cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
}

static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{
1294
	struct nic *nic = netdev_priv(netdev);
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305
	int err;

	if(nic->flags & ich_10h_workaround) {
		/* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
		   Issue a NOP command followed by a 1us delay before
		   issuing the Tx command. */
		e100_exec_cmd(nic, cuc_nop, 0);
		udelay(1);
	}

	err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1306 1307 1308

	switch(err) {
	case -ENOSPC:
1309
		/* We queued the skb, but now we're out of space. */
1310
		DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
		netif_stop_queue(netdev);
		break;
	case -ENOMEM:
		/* This is a hard error - log it. */
		DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
		netif_stop_queue(netdev);
		return 1;
	}

	netdev->trans_start = jiffies;
	return 0;
}

static inline int e100_tx_clean(struct nic *nic)
{
	struct cb *cb;
	int tx_cleaned = 0;

	spin_lock(&nic->cb_lock);

	DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
		nic->cb_to_clean->status);

	/* Clean CBs marked complete */
	for(cb = nic->cb_to_clean;
	    cb->status & cpu_to_le16(cb_complete);
	    cb = nic->cb_to_clean = cb->next) {
1338
		if(likely(cb->skb != NULL)) {
1339 1340 1341 1342 1343 1344 1345 1346
			nic->net_stats.tx_packets++;
			nic->net_stats.tx_bytes += cb->skb->len;

			pci_unmap_single(nic->pdev,
				le32_to_cpu(cb->u.tcb.tbd.buf_addr),
				le16_to_cpu(cb->u.tcb.tbd.size),
				PCI_DMA_TODEVICE);
			dev_kfree_skb_any(cb->skb);
1347
			cb->skb = NULL;
1348 1349 1350 1351 1352
			tx_cleaned = 1;
		}
		cb->status = 0;
		nic->cbs_avail++;
	}
1353

1354 1355 1356 1357 1358 1359 1360 1361 1362
	spin_unlock(&nic->cb_lock);

	/* Recover from running out of Tx resources in xmit_frame */
	if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
		netif_wake_queue(nic->netdev);

	return tx_cleaned;
}

1363
static void e100_clean_cbs(struct nic *nic)
1364 1365
{
	if(nic->cbs) {
1366
		while(nic->cbs_avail != nic->params.cbs.count) {
1367 1368 1369 1370 1371 1372 1373 1374 1375
			struct cb *cb = nic->cb_to_clean;
			if(cb->skb) {
				pci_unmap_single(nic->pdev,
					le32_to_cpu(cb->u.tcb.tbd.buf_addr),
					le16_to_cpu(cb->u.tcb.tbd.size),
					PCI_DMA_TODEVICE);
				dev_kfree_skb(cb->skb);
			}
			nic->cb_to_clean = nic->cb_to_clean->next;
1376
			nic->cbs_avail++;
1377
		}
1378 1379 1380 1381 1382
		pci_free_consistent(nic->pdev,
			sizeof(struct cb) * nic->params.cbs.count,
			nic->cbs, nic->cbs_dma_addr);
		nic->cbs = NULL;
		nic->cbs_avail = 0;
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
	}
	nic->cuc_cmd = cuc_start;
	nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
		nic->cbs;
}

static int e100_alloc_cbs(struct nic *nic)
{
	struct cb *cb;
	unsigned int i, count = nic->params.cbs.count;
1393

1394 1395 1396
	nic->cuc_cmd = cuc_start;
	nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
	nic->cbs_avail = 0;
1397 1398

	nic->cbs = pci_alloc_consistent(nic->pdev,
1399 1400 1401 1402 1403 1404
		sizeof(struct cb) * count, &nic->cbs_dma_addr);
	if(!nic->cbs)
		return -ENOMEM;

	for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
		cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1405 1406
		cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;

1407 1408 1409
		cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
		cb->link = cpu_to_le32(nic->cbs_dma_addr +
			((i+1) % count) * sizeof(struct cb));
1410
		cb->skb = NULL;
1411
	}
1412

1413 1414 1415 1416 1417 1418 1419 1420
	nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
	nic->cbs_avail = count;

	return 0;
}

static inline void e100_start_receiver(struct nic *nic)
{
1421 1422 1423 1424
	/* (Re)start RU if suspended or idle and RFA is non-NULL */
	if(!nic->ru_running && nic->rx_to_clean->skb) {
		e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
		nic->ru_running = 1;
1425 1426 1427
	}
}

1428 1429
#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1430
{
1431
	if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1432 1433
		return -ENOMEM;

1434
	/* Align, init, and map the RFD. */
1435
	rx->skb->dev = nic->netdev;
1436
	skb_reserve(rx->skb, NET_IP_ALIGN);
1437 1438
	memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
	rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1439
		RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1440 1441 1442 1443 1444 1445 1446

	/* Link the RFD to end of RFA by linking previous RFD to
	 * this one, and clearing EL bit of previous.  */
	if(rx->prev->skb) {
		struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
		put_unaligned(cpu_to_le32(rx->dma_addr),
			(u32 *)&prev_rfd->link);
1447
		wmb();
1448
		prev_rfd->command &= ~cpu_to_le16(cb_el);
1449
		pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1450
			sizeof(struct rfd), PCI_DMA_TODEVICE);
1451
	}
1452 1453 1454 1455

	return 0;
}

1456
static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1457 1458
	unsigned int *work_done, unsigned int work_to_do)
{
1459
	struct sk_buff *skb = rx->skb;
1460 1461 1462 1463 1464 1465 1466
	struct rfd *rfd = (struct rfd *)skb->data;
	u16 rfd_status, actual_size;

	if(unlikely(work_done && *work_done >= work_to_do))
		return -EAGAIN;

	/* Need to sync before taking a peek at cb_complete bit */
1467
	pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1468
		sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1469 1470 1471 1472 1473 1474
	rfd_status = le16_to_cpu(rfd->status);

	DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);

	/* If data isn't ready, nothing to indicate */
	if(unlikely(!(rfd_status & cb_complete)))
1475
		return -EAGAIN;
1476 1477 1478

	/* Get actual data size */
	actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1479 1480
	if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
		actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1481 1482

	/* Get data */
1483
	pci_unmap_single(nic->pdev, rx->dma_addr,
1484
		RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1485 1486 1487 1488 1489 1490

	/* Pull off the RFD and put the actual data (minus eth hdr) */
	skb_reserve(skb, sizeof(struct rfd));
	skb_put(skb, actual_size);
	skb->protocol = eth_type_trans(skb, nic->netdev);

1491 1492 1493 1494 1495 1496
	if(unlikely(!(rfd_status & cb_ok))) {
		/* Don't indicate if hardware indicates errors */
		nic->net_stats.rx_dropped++;
		dev_kfree_skb_any(skb);
	} else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
		/* Don't indicate oversized frames */
1497
		nic->rx_over_length_errors++;
1498
		nic->net_stats.rx_dropped++;
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
		dev_kfree_skb_any(skb);
	} else {
		nic->net_stats.rx_packets++;
		nic->net_stats.rx_bytes += actual_size;
		nic->netdev->last_rx = jiffies;
		netif_receive_skb(skb);
		if(work_done)
			(*work_done)++;
	}

1509 1510
	rx->skb = NULL;

1511 1512 1513 1514 1515 1516
	return 0;
}

static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
	unsigned int work_to_do)
{
1517
	struct rx *rx;
1518 1519

	/* Indicate newly arrived packets */
1520 1521 1522
	for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
		if(e100_rx_indicate(nic, rx, work_done, work_to_do))
			break; /* No more to clean */
1523 1524 1525
	}

	/* Alloc new skbs to refill list */
1526 1527
	for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
		if(unlikely(e100_rx_alloc_skb(nic, rx)))
1528 1529 1530 1531 1532 1533 1534 1535
			break; /* Better luck next time (see watchdog) */
	}

	e100_start_receiver(nic);
}

static void e100_rx_clean_list(struct nic *nic)
{
1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
	struct rx *rx;
	unsigned int i, count = nic->params.rfds.count;

	if(nic->rxs) {
		for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
			if(rx->skb) {
				pci_unmap_single(nic->pdev, rx->dma_addr,
					RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
				dev_kfree_skb(rx->skb);
			}
1546
		}
1547 1548
		kfree(nic->rxs);
		nic->rxs = NULL;
1549 1550
	}

1551 1552
	nic->rx_to_use = nic->rx_to_clean = NULL;
	nic->ru_running = 0;
1553 1554 1555 1556
}

static int e100_rx_alloc_list(struct nic *nic)
{
1557
	struct rx *rx;
1558 1559
	unsigned int i, count = nic->params.rfds.count;

1560 1561 1562
	nic->rx_to_use = nic->rx_to_clean = NULL;

	if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1563
		return -ENOMEM;
1564
	memset(nic->rxs, 0, sizeof(struct rx) * count);
1565

1566 1567 1568 1569
	for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
		rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
		rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
		if(e100_rx_alloc_skb(nic, rx)) {
1570 1571 1572 1573
			e100_rx_clean_list(nic);
			return -ENOMEM;
		}
	}
1574 1575 1576

	nic->rx_to_use = nic->rx_to_clean = nic->rxs;

1577 1578 1579 1580 1581 1582
	return 0;
}

static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct net_device *netdev = dev_id;
1583
	struct nic *nic = netdev_priv(netdev);
1584 1585 1586 1587
	u8 stat_ack = readb(&nic->csr->scb.stat_ack);

	DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);

1588 1589
	if(stat_ack == stat_ack_not_ours ||	/* Not our interrupt */
	   stat_ack == stat_ack_not_present)	/* Hardware is ejected */
1590 1591
		return IRQ_NONE;

1592
	/* Ack interrupt(s) */
1593
	writeb(stat_ack, &nic->csr->scb.stat_ack);
1594 1595 1596 1597

	/* We hit Receive No Resource (RNR); restart RU after cleaning */
	if(stat_ack & stat_ack_rnr)
		nic->ru_running = 0;
1598 1599 1600 1601 1602 1603 1604 1605 1606

	e100_disable_irq(nic);
	netif_rx_schedule(netdev);

	return IRQ_HANDLED;
}

static int e100_poll(struct net_device *netdev, int *budget)
{
1607
	struct nic *nic = netdev_priv(netdev);
1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627
	unsigned int work_to_do = min(netdev->quota, *budget);
	unsigned int work_done = 0;
	int tx_cleaned;

	e100_rx_clean(nic, &work_done, work_to_do);
	tx_cleaned = e100_tx_clean(nic);

	/* If no Rx and Tx cleanup work was done, exit polling mode. */
	if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
		netif_rx_complete(netdev);
		e100_enable_irq(nic);
		return 0;
	}

	*budget -= work_done;
	netdev->quota -= work_done;

	return 1;
}

1628 1629 1630
#ifdef CONFIG_NET_POLL_CONTROLLER
static void e100_netpoll(struct net_device *netdev)
{
1631
	struct nic *nic = netdev_priv(netdev);
1632 1633 1634 1635 1636 1637
	e100_disable_irq(nic);
	e100_intr(nic->pdev->irq, netdev, NULL);
	e100_enable_irq(nic);
}
#endif

1638 1639
static struct net_device_stats *e100_get_stats(struct net_device *netdev)
{
1640
	struct nic *nic = netdev_priv(netdev);
1641 1642 1643 1644 1645
	return &nic->net_stats;
}

static int e100_set_mac_address(struct net_device *netdev, void *p)
{
1646
	struct nic *nic = netdev_priv(netdev);
1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
	e100_exec_cb(nic, NULL, e100_setup_iaaddr);

	return 0;
}

static int e100_change_mtu(struct net_device *netdev, int new_mtu)
{
	if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
		return -EINVAL;
	netdev->mtu = new_mtu;
	return 0;
}

static int e100_asf(struct nic *nic)
{
	/* ASF can be enabled from eeprom */
1669
	return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1670 1671 1672 1673
	   (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
	   !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
	   ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
}
1674

1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691
static int e100_up(struct nic *nic)
{
	int err;

	if((err = e100_rx_alloc_list(nic)))
		return err;
	if((err = e100_alloc_cbs(nic)))
		goto err_rx_clean_list;
	if((err = e100_hw_init(nic)))
		goto err_clean_cbs;
	e100_set_multicast_list(nic->netdev);
	e100_start_receiver(nic);
	mod_timer(&nic->watchdog, jiffies);
	if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
		nic->netdev->name, nic->netdev)))
		goto err_no_irq;
	e100_enable_irq(nic);
1692
	netif_wake_queue(nic->netdev);
1693 1694 1695 1696 1697
	return 0;

err_no_irq:
	del_timer_sync(&nic->watchdog);
err_clean_cbs:
1698
	e100_clean_cbs(nic);
1699 1700 1701 1702 1703 1704 1705
err_rx_clean_list:
	e100_rx_clean_list(nic);
	return err;
}

static void e100_down(struct nic *nic)
{
1706
	e100_hw_reset(nic);
1707 1708 1709 1710
	free_irq(nic->pdev->irq, nic->netdev);
	del_timer_sync(&nic->watchdog);
	netif_carrier_off(nic->netdev);
	netif_stop_queue(nic->netdev);
1711
	e100_clean_cbs(nic);
1712 1713 1714 1715 1716
	e100_rx_clean_list(nic);
}

static void e100_tx_timeout(struct net_device *netdev)
{
1717
	struct nic *nic = netdev_priv(netdev);
1718 1719 1720

	DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
		readb(&nic->csr->scb.status));
1721 1722
	e100_down(netdev_priv(netdev));
	e100_up(netdev_priv(netdev));
1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752
}

static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
{
	int err;
	struct sk_buff *skb;

	/* Use driver resources to perform internal MAC or PHY
	 * loopback test.  A single packet is prepared and transmitted
	 * in loopback mode, and the test passes if the received
	 * packet compares byte-for-byte to the transmitted packet. */

	if((err = e100_rx_alloc_list(nic)))
		return err;
	if((err = e100_alloc_cbs(nic)))
		goto err_clean_rx;

	/* ICH PHY loopback is broken so do MAC loopback instead */
	if(nic->flags & ich && loopback_mode == lb_phy)
		loopback_mode = lb_mac;

	nic->loopback = loopback_mode;
	if((err = e100_hw_init(nic)))
		goto err_loopback_none;

	if(loopback_mode == lb_phy)
		mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
			BMCR_LOOPBACK);

	e100_start_receiver(nic);
1753

1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764
	if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
		err = -ENOMEM;
		goto err_loopback_none;
	}
	skb_put(skb, ETH_DATA_LEN);
	memset(skb->data, 0xFF, ETH_DATA_LEN);
	e100_xmit_frame(skb, nic->netdev);

	set_current_state(TASK_UNINTERRUPTIBLE);
	schedule_timeout(HZ / 100 + 1);

1765 1766
	if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
	   skb->data, ETH_DATA_LEN))
1767
		err = -EAGAIN;
1768 1769 1770 1771 1772

err_loopback_none:
	mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
	nic->loopback = lb_none;
	e100_hw_init(nic);
1773
	e100_clean_cbs(nic);
1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797
err_clean_rx:
	e100_rx_clean_list(nic);
	return err;
}

#define MII_LED_CONTROL	0x1B
static void e100_blink_led(unsigned long data)
{
	struct nic *nic = (struct nic *)data;
	enum led_state {
		led_on     = 0x01,
		led_off    = 0x04,
		led_on_559 = 0x05,
		led_on_557 = 0x07,
	};

	nic->leds = (nic->leds & led_on) ? led_off :
		(nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
	mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
	mod_timer(&nic->blink_timer, jiffies + HZ / 4);
}

static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
{
1798
	struct nic *nic = netdev_priv(netdev);
1799 1800
	return mii_ethtool_gset(&nic->mii, cmd);
}
1801

1802 1803
static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
{
1804
	struct nic *nic = netdev_priv(netdev);
1805 1806 1807 1808 1809 1810 1811
	int err;

	mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
	err = mii_ethtool_sset(&nic->mii, cmd);
	e100_exec_cb(nic, NULL, e100_configure);

	return err;
1812
}
1813

1814 1815 1816
static void e100_get_drvinfo(struct net_device *netdev,
	struct ethtool_drvinfo *info)
{
1817
	struct nic *nic = netdev_priv(netdev);
1818 1819 1820 1821 1822
	strcpy(info->driver, DRV_NAME);
	strcpy(info->version, DRV_VERSION);
	strcpy(info->fw_version, "N/A");
	strcpy(info->bus_info, pci_name(nic->pdev));
}
1823

1824 1825
static int e100_get_regs_len(struct net_device *netdev)
{
1826
	struct nic *nic = netdev_priv(netdev);
1827 1828 1829 1830 1831 1832 1833 1834 1835
#define E100_PHY_REGS		0x1C
#define E100_REGS_LEN		1 + E100_PHY_REGS + \
	sizeof(nic->mem->dump_buf) / sizeof(u32)
	return E100_REGS_LEN * sizeof(u32);
}

static void e100_get_regs(struct net_device *netdev,
	struct ethtool_regs *regs, void *p)
{
1836
	struct nic *nic = netdev_priv(netdev);
1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
	u32 *buff = p;
	int i;

	regs->version = (1 << 24) | nic->rev_id;
	buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
		readb(&nic->csr->scb.cmd_lo) << 16 |
		readw(&nic->csr->scb.status);
	for(i = E100_PHY_REGS; i >= 0; i--)
		buff[1 + E100_PHY_REGS - i] =
			mdio_read(netdev, nic->mii.phy_id, i);
	memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
	e100_exec_cb(nic, NULL, e100_dump);
	set_current_state(TASK_UNINTERRUPTIBLE);
	schedule_timeout(HZ / 100 + 1);
	memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
		sizeof(nic->mem->dump_buf));
}

static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
1857
	struct nic *nic = netdev_priv(netdev);
1858 1859 1860
	wol->supported = (nic->mac >= mac_82558_D101_A4) ?  WAKE_MAGIC : 0;
	wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
}
1861

1862 1863
static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
1864
	struct nic *nic = netdev_priv(netdev);
1865

1866 1867 1868 1869 1870 1871 1872 1873 1874 1875
	if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
		return -EOPNOTSUPP;

	if(wol->wolopts)
		nic->flags |= wol_magic;
	else
		nic->flags &= ~wol_magic;

	pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
	e100_exec_cb(nic, NULL, e100_configure);
1876

1877 1878
	return 0;
}
1879

1880 1881
static u32 e100_get_msglevel(struct net_device *netdev)
{
1882
	struct nic *nic = netdev_priv(netdev);
1883 1884
	return nic->msg_enable;
}
1885

1886 1887
static void e100_set_msglevel(struct net_device *netdev, u32 value)
{
1888
	struct nic *nic = netdev_priv(netdev);
1889 1890
	nic->msg_enable = value;
}
1891

1892 1893
static int e100_nway_reset(struct net_device *netdev)
{
1894
	struct nic *nic = netdev_priv(netdev);
1895 1896 1897 1898 1899
	return mii_nway_restart(&nic->mii);
}

static u32 e100_get_link(struct net_device *netdev)
{
1900
	struct nic *nic = netdev_priv(netdev);
1901 1902
	return mii_link_ok(&nic->mii);
}
1903

1904 1905
static int e100_get_eeprom_len(struct net_device *netdev)
{
1906
	struct nic *nic = netdev_priv(netdev);
1907 1908 1909 1910 1911 1912 1913
	return nic->eeprom_wc << 1;
}

#define E100_EEPROM_MAGIC	0x1234
static int e100_get_eeprom(struct net_device *netdev,
	struct ethtool_eeprom *eeprom, u8 *bytes)
{
1914
	struct nic *nic = netdev_priv(netdev);
1915

1916 1917 1918 1919 1920 1921 1922 1923 1924
	eeprom->magic = E100_EEPROM_MAGIC;
	memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);

	return 0;
}

static int e100_set_eeprom(struct net_device *netdev,
	struct ethtool_eeprom *eeprom, u8 *bytes)
{
1925
	struct nic *nic = netdev_priv(netdev);
1926

1927 1928
	if(eeprom->magic != E100_EEPROM_MAGIC)
		return -EINVAL;
1929

1930 1931 1932 1933 1934 1935 1936 1937 1938
	memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);

	return e100_eeprom_save(nic, eeprom->offset >> 1,
		(eeprom->len >> 1) + 1);
}

static void e100_get_ringparam(struct net_device *netdev,
	struct ethtool_ringparam *ring)
{
1939
	struct nic *nic = netdev_priv(netdev);
1940 1941
	struct param_range *rfds = &nic->params.rfds;
	struct param_range *cbs = &nic->params.cbs;
1942

1943 1944 1945 1946 1947 1948 1949 1950 1951
	ring->rx_max_pending = rfds->max;
	ring->tx_max_pending = cbs->max;
	ring->rx_mini_max_pending = 0;
	ring->rx_jumbo_max_pending = 0;
	ring->rx_pending = rfds->count;
	ring->tx_pending = cbs->count;
	ring->rx_mini_pending = 0;
	ring->rx_jumbo_pending = 0;
}
1952

1953 1954 1955
static int e100_set_ringparam(struct net_device *netdev,
	struct ethtool_ringparam *ring)
{
1956
	struct nic *nic = netdev_priv(netdev);
1957 1958
	struct param_range *rfds = &nic->params.rfds;
	struct param_range *cbs = &nic->params.cbs;
1959

1960 1961 1962
	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 
		return -EINVAL;

1963 1964 1965 1966 1967 1968
	if(netif_running(netdev))
		e100_down(nic);
	rfds->count = max(ring->rx_pending, rfds->min);
	rfds->count = min(rfds->count, rfds->max);
	cbs->count = max(ring->tx_pending, cbs->min);
	cbs->count = min(cbs->count, cbs->max);
1969 1970
	DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
	        rfds->count, cbs->count);
1971 1972
	if(netif_running(netdev))
		e100_up(nic);
1973

1974 1975
	return 0;
}
1976 1977

static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993
	"Link test     (on/offline)",
	"Eeprom test   (on/offline)",
	"Self test        (offline)",
	"Mac loopback     (offline)",
	"Phy loopback     (offline)",
};
#define E100_TEST_LEN	sizeof(e100_gstrings_test) / ETH_GSTRING_LEN

static int e100_diag_test_count(struct net_device *netdev)
{
	return E100_TEST_LEN;
}

static void e100_diag_test(struct net_device *netdev,
	struct ethtool_test *test, u64 *data)
{
1994
	struct ethtool_cmd cmd;
1995
	struct nic *nic = netdev_priv(netdev);
1996
	int i, err;
1997 1998 1999 2000 2001

	memset(data, 0, E100_TEST_LEN * sizeof(u64));
	data[0] = !mii_link_ok(&nic->mii);
	data[1] = e100_eeprom_load(nic);
	if(test->flags & ETH_TEST_FL_OFFLINE) {
2002 2003 2004 2005

		/* save speed, duplex & autoneg settings */
		err = mii_ethtool_gset(&nic->mii, &cmd);

2006 2007 2008 2009 2010
		if(netif_running(netdev))
			e100_down(nic);
		data[2] = e100_self_test(nic);
		data[3] = e100_loopback_test(nic, lb_mac);
		data[4] = e100_loopback_test(nic, lb_phy);
2011 2012 2013 2014

		/* restore speed, duplex & autoneg settings */
		err = mii_ethtool_sset(&nic->mii, &cmd);

2015 2016 2017 2018 2019 2020 2021 2022 2023
		if(netif_running(netdev))
			e100_up(nic);
	}
	for(i = 0; i < E100_TEST_LEN; i++)
		test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
}

static int e100_phys_id(struct net_device *netdev, u32 data)
{
2024
	struct nic *nic = netdev_priv(netdev);
2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036

	if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
		data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
	mod_timer(&nic->blink_timer, jiffies);
	set_current_state(TASK_INTERRUPTIBLE);
	schedule_timeout(data * HZ);
	del_timer_sync(&nic->blink_timer);
	mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);

	return 0;
}

2037
static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2038 2039 2040 2041 2042 2043 2044
	"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
	"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
	"rx_length_errors", "rx_over_errors", "rx_crc_errors",
	"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
	"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
	"tx_heartbeat_errors", "tx_window_errors",
	/* device-specific stats */
2045
	"tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
	"tx_flow_control_pause", "rx_flow_control_pause",
	"rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
};
#define E100_NET_STATS_LEN	21
#define E100_STATS_LEN	sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN

static int e100_get_stats_count(struct net_device *netdev)
{
	return E100_STATS_LEN;
}

static void e100_get_ethtool_stats(struct net_device *netdev,
	struct ethtool_stats *stats, u64 *data)
{
2060
	struct nic *nic = netdev_priv(netdev);
2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114
	int i;

	for(i = 0; i < E100_NET_STATS_LEN; i++)
		data[i] = ((unsigned long *)&nic->net_stats)[i];

	data[i++] = nic->tx_deferred;
	data[i++] = nic->tx_single_collisions;
	data[i++] = nic->tx_multiple_collisions;
	data[i++] = nic->tx_fc_pause;
	data[i++] = nic->rx_fc_pause;
	data[i++] = nic->rx_fc_unsupported;
	data[i++] = nic->tx_tco_frames;
	data[i++] = nic->rx_tco_frames;
}

static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
{
	switch(stringset) {
	case ETH_SS_TEST:
		memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
		break;
	case ETH_SS_STATS:
		memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
		break;
	}
}

static struct ethtool_ops e100_ethtool_ops = {
	.get_settings		= e100_get_settings,
	.set_settings		= e100_set_settings,
	.get_drvinfo		= e100_get_drvinfo,
	.get_regs_len		= e100_get_regs_len,
	.get_regs		= e100_get_regs,
	.get_wol		= e100_get_wol,
	.set_wol		= e100_set_wol,
	.get_msglevel		= e100_get_msglevel,
	.set_msglevel		= e100_set_msglevel,
	.nway_reset		= e100_nway_reset,
	.get_link		= e100_get_link,
	.get_eeprom_len		= e100_get_eeprom_len,
	.get_eeprom		= e100_get_eeprom,
	.set_eeprom		= e100_set_eeprom,
	.get_ringparam		= e100_get_ringparam,
	.set_ringparam		= e100_set_ringparam,
	.self_test_count	= e100_diag_test_count,
	.self_test		= e100_diag_test,
	.get_strings		= e100_get_strings,
	.phys_id		= e100_phys_id,
	.get_stats_count	= e100_get_stats_count,
	.get_ethtool_stats	= e100_get_ethtool_stats,
};

static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
2115
	struct nic *nic = netdev_priv(netdev);
2116

2117
	return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
}

static int e100_alloc(struct nic *nic)
{
	nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
		&nic->dma_addr);
	return nic->mem ? 0 : -ENOMEM;
}

static void e100_free(struct nic *nic)
{
	if(nic->mem) {
		pci_free_consistent(nic->pdev, sizeof(struct mem),
			nic->mem, nic->dma_addr);
		nic->mem = NULL;
	}
}

static int e100_open(struct net_device *netdev)
{
2138
	struct nic *nic = netdev_priv(netdev);
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148
	int err = 0;

	netif_carrier_off(netdev);
	if((err = e100_up(nic)))
		DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
	return err;
}

static int e100_close(struct net_device *netdev)
{
2149
	e100_down(netdev_priv(netdev));
2150 2151 2152
	return 0;
}

2153
static int __devinit e100_probe(struct pci_dev *pdev,
2154 2155 2156 2157 2158
	const struct pci_device_id *ent)
{
	struct net_device *netdev;
	struct nic *nic;
	int err;
2159

2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178
	if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
		if(((1 << debug) - 1) & NETIF_MSG_PROBE)
			printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
		return -ENOMEM;
	}

	netdev->open = e100_open;
	netdev->stop = e100_close;
	netdev->hard_start_xmit = e100_xmit_frame;
	netdev->get_stats = e100_get_stats;
	netdev->set_multicast_list = e100_set_multicast_list;
	netdev->set_mac_address = e100_set_mac_address;
	netdev->change_mtu = e100_change_mtu;
	netdev->do_ioctl = e100_do_ioctl;
	SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
	netdev->tx_timeout = e100_tx_timeout;
	netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
	netdev->poll = e100_poll;
	netdev->weight = E100_NAPI_WEIGHT;
2179 2180 2181
#ifdef CONFIG_NET_POLL_CONTROLLER
	netdev->poll_controller = e100_netpoll;
#endif
2182
	strcpy(netdev->name, pci_name(pdev));
2183

2184
	nic = netdev_priv(netdev);
2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206
	nic->netdev = netdev;
	nic->pdev = pdev;
	nic->msg_enable = (1 << debug) - 1;
	pci_set_drvdata(pdev, netdev);

	if((err = pci_enable_device(pdev))) {
		DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
		goto err_out_free_dev;
	}

	if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
		DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
			"base address, aborting.\n");
		err = -ENODEV;
		goto err_out_disable_pdev;
	}

	if((err = pci_request_regions(pdev, DRV_NAME))) {
		DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
		goto err_out_disable_pdev;
	}

2207 2208 2209 2210 2211 2212 2213 2214 2215
	nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
	if(!nic->csr) {
		DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
		err = -ENOMEM;
		goto err_out_free_res;
	}

	e100_hw_reset(nic);

2216 2217 2218 2219
	pci_set_master(pdev);

	if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
		DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2220
		goto err_out_iounmap;
2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
	}

	SET_MODULE_OWNER(netdev);
	SET_NETDEV_DEV(netdev, &pdev->dev);

	if(ent->driver_data)
		nic->flags |= ich;
	else
		nic->flags &= ~ich;

	spin_lock_init(&nic->cb_lock);
	spin_lock_init(&nic->cmd_lock);

	init_timer(&nic->watchdog);
	nic->watchdog.function = e100_watchdog;
	nic->watchdog.data = (unsigned long)nic;
	init_timer(&nic->blink_timer);
	nic->blink_timer.function = e100_blink_led;
	nic->blink_timer.data = (unsigned long)nic;

	if((err = e100_alloc(nic))) {
		DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
		goto err_out_iounmap;
	}

	e100_get_defaults(nic);
	e100_hw_reset(nic);
	e100_phy_init(nic);

	if((err = e100_eeprom_load(nic)))
		goto err_out_free;
2252 2253

	memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2254
	if(!is_valid_ether_addr(netdev->dev_addr)) {
2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267
		DPRINTK(PROBE, ERR, "Invalid MAC address from "
			"EEPROM, aborting.\n");
		err = -EAGAIN;
		goto err_out_free;
	}

	/* Wol magic packet can be enabled from eeprom */
	if((nic->mac >= mac_82558_D101_A4) &&
	   (nic->eeprom[eeprom_id] & eeprom_id_wol))
		nic->flags |= wol_magic;

	pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));

2268
	strcpy(netdev->name, "eth%d");
2269 2270 2271 2272 2273
	if((err = register_netdev(netdev))) {
		DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
		goto err_out_free;
	}

2274 2275 2276 2277 2278 2279
	DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
		"MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
		pci_resource_start(pdev, 0), pdev->irq,
		netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
		netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);

2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300
	return 0;

err_out_free:
	e100_free(nic);
err_out_iounmap:
	iounmap(nic->csr);
err_out_free_res:
	pci_release_regions(pdev);
err_out_disable_pdev:
	pci_disable_device(pdev);
err_out_free_dev:
	pci_set_drvdata(pdev, NULL);
	free_netdev(netdev);
	return err;
}

static void __devexit e100_remove(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);

	if(netdev) {
2301
		struct nic *nic = netdev_priv(netdev);
2302 2303 2304 2305 2306 2307 2308 2309 2310 2311
		unregister_netdev(netdev);
		e100_free(nic);
		iounmap(nic->csr);
		free_netdev(netdev);
		pci_release_regions(pdev);
		pci_disable_device(pdev);
		pci_set_drvdata(pdev, NULL);
	}
}

2312
#ifdef CONFIG_PM
2313 2314 2315
static int e100_suspend(struct pci_dev *pdev, u32 state)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
2316
	struct nic *nic = netdev_priv(netdev);
2317 2318 2319 2320 2321 2322

	if(netif_running(netdev))
		e100_down(nic);
	e100_hw_reset(nic);
	netif_device_detach(netdev);

2323
	pci_save_state(pdev);
2324 2325 2326 2327 2328 2329 2330 2331 2332 2333
	pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
	pci_disable_device(pdev);
	pci_set_power_state(pdev, state);

	return 0;
}

static int e100_resume(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
2334
	struct nic *nic = netdev_priv(netdev);
2335 2336

	pci_set_power_state(pdev, 0);
2337
	pci_restore_state(pdev);
2338 2339 2340 2341 2342
	e100_hw_init(nic);

	netif_device_attach(netdev);
	if(netif_running(netdev))
		e100_up(nic);
2343

2344 2345 2346 2347 2348 2349 2350 2351 2352
	return 0;
}
#endif

static struct pci_driver e100_driver = {
	.name =         DRV_NAME,
	.id_table =     e100_id_table,
	.probe =        e100_probe,
	.remove =       __devexit_p(e100_remove),
2353
#ifdef CONFIG_PM
2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364
	.suspend =      e100_suspend,
	.resume =       e100_resume,
#endif
};

static int __init e100_init_module(void)
{
	if(((1 << debug) - 1) & NETIF_MSG_DRV) {
		printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
		printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
	}
2365
	return pci_module_init(&e100_driver);
2366 2367 2368 2369 2370 2371 2372 2373 2374
}

static void __exit e100_cleanup_module(void)
{
	pci_unregister_driver(&e100_driver);
}

module_init(e100_init_module);
module_exit(e100_cleanup_module);