cx25821-core.c 35.9 KB
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/*
 *  Driver for the Conexant CX25821 PCIe bridge
 *
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 *  Copyright (C) 2009 Conexant Systems Inc.
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 *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
 *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include "cx25821.h"
#include "cx25821-sram.h"
#include "cx25821-video.h"

MODULE_DESCRIPTION("Driver for Athena cards");
MODULE_AUTHOR("Shu Lin - Hiep Huynh");
MODULE_LICENSE("GPL");

static unsigned int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "enable debug messages");

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static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
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module_param_array(card, int, NULL, 0444);
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MODULE_PARM_DESC(card, "card type");

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const struct sram_channel cx25821_sram_channels[] = {
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	[SRAM_CH00] = {
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		.i = SRAM_CH00,
		.name = "VID A",
		.cmds_start = VID_A_DOWN_CMDS,
		.ctrl_start = VID_A_IQ,
		.cdt = VID_A_CDT,
		.fifo_start = VID_A_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA1_PTR1,
		.ptr2_reg = DMA1_PTR2,
		.cnt1_reg = DMA1_CNT1,
		.cnt2_reg = DMA1_CNT2,
		.int_msk = VID_A_INT_MSK,
		.int_stat = VID_A_INT_STAT,
		.int_mstat = VID_A_INT_MSTAT,
		.dma_ctl = VID_DST_A_DMA_CTL,
		.gpcnt_ctl = VID_DST_A_GPCNT_CTL,
		.gpcnt = VID_DST_A_GPCNT,
		.vip_ctl = VID_DST_A_VIP_CTL,
		.pix_frmt = VID_DST_A_PIX_FRMT,
	},
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	[SRAM_CH01] = {
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		.i = SRAM_CH01,
		.name = "VID B",
		.cmds_start = VID_B_DOWN_CMDS,
		.ctrl_start = VID_B_IQ,
		.cdt = VID_B_CDT,
		.fifo_start = VID_B_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA2_PTR1,
		.ptr2_reg = DMA2_PTR2,
		.cnt1_reg = DMA2_CNT1,
		.cnt2_reg = DMA2_CNT2,
		.int_msk = VID_B_INT_MSK,
		.int_stat = VID_B_INT_STAT,
		.int_mstat = VID_B_INT_MSTAT,
		.dma_ctl = VID_DST_B_DMA_CTL,
		.gpcnt_ctl = VID_DST_B_GPCNT_CTL,
		.gpcnt = VID_DST_B_GPCNT,
		.vip_ctl = VID_DST_B_VIP_CTL,
		.pix_frmt = VID_DST_B_PIX_FRMT,
	},
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	[SRAM_CH02] = {
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		.i = SRAM_CH02,
		.name = "VID C",
		.cmds_start = VID_C_DOWN_CMDS,
		.ctrl_start = VID_C_IQ,
		.cdt = VID_C_CDT,
		.fifo_start = VID_C_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA3_PTR1,
		.ptr2_reg = DMA3_PTR2,
		.cnt1_reg = DMA3_CNT1,
		.cnt2_reg = DMA3_CNT2,
		.int_msk = VID_C_INT_MSK,
		.int_stat = VID_C_INT_STAT,
		.int_mstat = VID_C_INT_MSTAT,
		.dma_ctl = VID_DST_C_DMA_CTL,
		.gpcnt_ctl = VID_DST_C_GPCNT_CTL,
		.gpcnt = VID_DST_C_GPCNT,
		.vip_ctl = VID_DST_C_VIP_CTL,
		.pix_frmt = VID_DST_C_PIX_FRMT,
	},
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	[SRAM_CH03] = {
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		.i = SRAM_CH03,
		.name = "VID D",
		.cmds_start = VID_D_DOWN_CMDS,
		.ctrl_start = VID_D_IQ,
		.cdt = VID_D_CDT,
		.fifo_start = VID_D_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA4_PTR1,
		.ptr2_reg = DMA4_PTR2,
		.cnt1_reg = DMA4_CNT1,
		.cnt2_reg = DMA4_CNT2,
		.int_msk = VID_D_INT_MSK,
		.int_stat = VID_D_INT_STAT,
		.int_mstat = VID_D_INT_MSTAT,
		.dma_ctl = VID_DST_D_DMA_CTL,
		.gpcnt_ctl = VID_DST_D_GPCNT_CTL,
		.gpcnt = VID_DST_D_GPCNT,
		.vip_ctl = VID_DST_D_VIP_CTL,
		.pix_frmt = VID_DST_D_PIX_FRMT,
	},
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	[SRAM_CH04] = {
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		.i = SRAM_CH04,
		.name = "VID E",
		.cmds_start = VID_E_DOWN_CMDS,
		.ctrl_start = VID_E_IQ,
		.cdt = VID_E_CDT,
		.fifo_start = VID_E_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA5_PTR1,
		.ptr2_reg = DMA5_PTR2,
		.cnt1_reg = DMA5_CNT1,
		.cnt2_reg = DMA5_CNT2,
		.int_msk = VID_E_INT_MSK,
		.int_stat = VID_E_INT_STAT,
		.int_mstat = VID_E_INT_MSTAT,
		.dma_ctl = VID_DST_E_DMA_CTL,
		.gpcnt_ctl = VID_DST_E_GPCNT_CTL,
		.gpcnt = VID_DST_E_GPCNT,
		.vip_ctl = VID_DST_E_VIP_CTL,
		.pix_frmt = VID_DST_E_PIX_FRMT,
	},
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	[SRAM_CH05] = {
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		.i = SRAM_CH05,
		.name = "VID F",
		.cmds_start = VID_F_DOWN_CMDS,
		.ctrl_start = VID_F_IQ,
		.cdt = VID_F_CDT,
		.fifo_start = VID_F_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA6_PTR1,
		.ptr2_reg = DMA6_PTR2,
		.cnt1_reg = DMA6_CNT1,
		.cnt2_reg = DMA6_CNT2,
		.int_msk = VID_F_INT_MSK,
		.int_stat = VID_F_INT_STAT,
		.int_mstat = VID_F_INT_MSTAT,
		.dma_ctl = VID_DST_F_DMA_CTL,
		.gpcnt_ctl = VID_DST_F_GPCNT_CTL,
		.gpcnt = VID_DST_F_GPCNT,
		.vip_ctl = VID_DST_F_VIP_CTL,
		.pix_frmt = VID_DST_F_PIX_FRMT,
	},
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	[SRAM_CH06] = {
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		.i = SRAM_CH06,
		.name = "VID G",
		.cmds_start = VID_G_DOWN_CMDS,
		.ctrl_start = VID_G_IQ,
		.cdt = VID_G_CDT,
		.fifo_start = VID_G_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA7_PTR1,
		.ptr2_reg = DMA7_PTR2,
		.cnt1_reg = DMA7_CNT1,
		.cnt2_reg = DMA7_CNT2,
		.int_msk = VID_G_INT_MSK,
		.int_stat = VID_G_INT_STAT,
		.int_mstat = VID_G_INT_MSTAT,
		.dma_ctl = VID_DST_G_DMA_CTL,
		.gpcnt_ctl = VID_DST_G_GPCNT_CTL,
		.gpcnt = VID_DST_G_GPCNT,
		.vip_ctl = VID_DST_G_VIP_CTL,
		.pix_frmt = VID_DST_G_PIX_FRMT,
	},
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	[SRAM_CH07] = {
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		.i = SRAM_CH07,
		.name = "VID H",
		.cmds_start = VID_H_DOWN_CMDS,
		.ctrl_start = VID_H_IQ,
		.cdt = VID_H_CDT,
		.fifo_start = VID_H_DOWN_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA8_PTR1,
		.ptr2_reg = DMA8_PTR2,
		.cnt1_reg = DMA8_CNT1,
		.cnt2_reg = DMA8_CNT2,
		.int_msk = VID_H_INT_MSK,
		.int_stat = VID_H_INT_STAT,
		.int_mstat = VID_H_INT_MSTAT,
		.dma_ctl = VID_DST_H_DMA_CTL,
		.gpcnt_ctl = VID_DST_H_GPCNT_CTL,
		.gpcnt = VID_DST_H_GPCNT,
		.vip_ctl = VID_DST_H_VIP_CTL,
		.pix_frmt = VID_DST_H_PIX_FRMT,
	},
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	[SRAM_CH08] = {
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		.name = "audio from",
		.cmds_start = AUD_A_DOWN_CMDS,
		.ctrl_start = AUD_A_IQ,
		.cdt = AUD_A_CDT,
		.fifo_start = AUD_A_DOWN_CLUSTER_1,
		.fifo_size = AUDIO_CLUSTER_SIZE * 3,
		.ptr1_reg = DMA17_PTR1,
		.ptr2_reg = DMA17_PTR2,
		.cnt1_reg = DMA17_CNT1,
		.cnt2_reg = DMA17_CNT2,
	},
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	[SRAM_CH09] = {
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		.i = SRAM_CH09,
		.name = "VID Upstream I",
		.cmds_start = VID_I_UP_CMDS,
		.ctrl_start = VID_I_IQ,
		.cdt = VID_I_CDT,
		.fifo_start = VID_I_UP_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA15_PTR1,
		.ptr2_reg = DMA15_PTR2,
		.cnt1_reg = DMA15_CNT1,
		.cnt2_reg = DMA15_CNT2,
		.int_msk = VID_I_INT_MSK,
		.int_stat = VID_I_INT_STAT,
		.int_mstat = VID_I_INT_MSTAT,
		.dma_ctl = VID_SRC_I_DMA_CTL,
		.gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
		.gpcnt = VID_SRC_I_GPCNT,

		.vid_fmt_ctl = VID_SRC_I_FMT_CTL,
		.vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
		.vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
		.vid_cdt_size = VID_SRC_I_CDT_SZ,
		.irq_bit = 8,
	},
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	[SRAM_CH10] = {
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		.i = SRAM_CH10,
		.name = "VID Upstream J",
		.cmds_start = VID_J_UP_CMDS,
		.ctrl_start = VID_J_IQ,
		.cdt = VID_J_CDT,
		.fifo_start = VID_J_UP_CLUSTER_1,
		.fifo_size = (VID_CLUSTER_SIZE << 2),
		.ptr1_reg = DMA16_PTR1,
		.ptr2_reg = DMA16_PTR2,
		.cnt1_reg = DMA16_CNT1,
		.cnt2_reg = DMA16_CNT2,
		.int_msk = VID_J_INT_MSK,
		.int_stat = VID_J_INT_STAT,
		.int_mstat = VID_J_INT_MSTAT,
		.dma_ctl = VID_SRC_J_DMA_CTL,
		.gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
		.gpcnt = VID_SRC_J_GPCNT,

		.vid_fmt_ctl = VID_SRC_J_FMT_CTL,
		.vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
		.vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
		.vid_cdt_size = VID_SRC_J_CDT_SZ,
		.irq_bit = 9,
	},
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	[SRAM_CH11] = {
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		.i = SRAM_CH11,
		.name = "Audio Upstream Channel B",
		.cmds_start = AUD_B_UP_CMDS,
		.ctrl_start = AUD_B_IQ,
		.cdt = AUD_B_CDT,
		.fifo_start = AUD_B_UP_CLUSTER_1,
		.fifo_size = (AUDIO_CLUSTER_SIZE * 3),
		.ptr1_reg = DMA22_PTR1,
		.ptr2_reg = DMA22_PTR2,
		.cnt1_reg = DMA22_CNT1,
		.cnt2_reg = DMA22_CNT2,
		.int_msk = AUD_B_INT_MSK,
		.int_stat = AUD_B_INT_STAT,
		.int_mstat = AUD_B_INT_MSTAT,
		.dma_ctl = AUD_INT_DMA_CTL,
		.gpcnt_ctl = AUD_B_GPCNT_CTL,
		.gpcnt = AUD_B_GPCNT,
		.aud_length = AUD_B_LNGTH,
		.aud_cfg = AUD_B_CFG,
		.fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
		.fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
		.irq_bit = 11,
	},
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};
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EXPORT_SYMBOL(cx25821_sram_channels);
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static int cx25821_risc_decode(u32 risc)
{
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	static const char * const instr[16] = {
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		[RISC_SYNC >> 28] = "sync",
		[RISC_WRITE >> 28] = "write",
		[RISC_WRITEC >> 28] = "writec",
		[RISC_READ >> 28] = "read",
		[RISC_READC >> 28] = "readc",
		[RISC_JUMP >> 28] = "jump",
		[RISC_SKIP >> 28] = "skip",
		[RISC_WRITERM >> 28] = "writerm",
		[RISC_WRITECM >> 28] = "writecm",
		[RISC_WRITECR >> 28] = "writecr",
	};
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	static const int incr[16] = {
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		[RISC_WRITE >> 28] = 3,
		[RISC_JUMP >> 28] = 3,
		[RISC_SKIP >> 28] = 1,
		[RISC_SYNC >> 28] = 1,
		[RISC_WRITERM >> 28] = 3,
		[RISC_WRITECM >> 28] = 3,
		[RISC_WRITECR >> 28] = 4,
	};
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	static const char * const bits[] = {
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		"12", "13", "14", "resync",
		"cnt0", "cnt1", "18", "19",
		"20", "21", "22", "23",
		"irq1", "irq2", "eol", "sol",
	};
	int i;

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	pr_cont("0x%08x [ %s",
		risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
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	for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
		if (risc & (1 << (i + 12)))
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			pr_cont(" %s", bits[i]);
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	}
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	pr_cont(" count=%d ]\n", risc & 0xfff);
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	return incr[risc >> 28] ? incr[risc >> 28] : 1;
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}

static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
{
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	struct cx25821_i2c *bus = i2c_adap->algo_data;
	struct cx25821_dev *dev = bus->dev;
	return cx_read(bus->reg_stat) & 0x01;
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}

static void cx25821_registers_init(struct cx25821_dev *dev)
{
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	u32 tmp;
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	/* enable RUN_RISC in Pecos */
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	cx_write(DEV_CNTRL2, 0x20);
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	/* Set the master PCI interrupt masks to enable video, audio, MBIF,
	 * and GPIO interrupts
	 * I2C interrupt masking is handled by the I2C objects themselves. */
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	cx_write(PCI_INT_MSK, 0x2001FFFF);
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	tmp = cx_read(RDR_TLCTL0);
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	tmp &= ~FLD_CFG_RCB_CK_EN;	/* Clear the RCB_CK_EN bit */
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	cx_write(RDR_TLCTL0, tmp);
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	/* PLL-A setting for the Audio Master Clock */
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	cx_write(PLL_A_INT_FRAC, 0x9807A58B);
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	/* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
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	cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
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	/* clear reset bit [31] */
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	tmp = cx_read(PLL_A_INT_FRAC);
	cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
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	/* PLL-B setting for Mobilygen Host Bus Interface */
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	cx_write(PLL_B_INT_FRAC, 0x9883A86F);
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	/* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
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	cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
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	/* clear reset bit [31] */
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	tmp = cx_read(PLL_B_INT_FRAC);
	cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
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	/* PLL-C setting for video upstream channel */
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	cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
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	/* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
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	cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
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	/* clear reset bit [31] */
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	tmp = cx_read(PLL_C_INT_FRAC);
	cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
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	/* PLL-D setting for audio upstream channel */
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	cx_write(PLL_D_INT_FRAC, 0x98757F5B);
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	/* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
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	cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
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	/* clear reset bit [31] */
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	tmp = cx_read(PLL_D_INT_FRAC);
	cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
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	/* This selects the PLL C clock source for the video upstream channel
	 * I and J */
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	tmp = cx_read(VID_CH_CLK_SEL);
	cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
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	/* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
	 * channel A-C
	 * select 656/VIP DST for downstream Channel A - C */
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	tmp = cx_read(VID_CH_MODE_SEL);
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	/* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
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	cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
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	/* enables 656 port I and J as output */
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	tmp = cx_read(CLK_RST);
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	/* use external ALT_PLL_REF pin as its reference clock instead */
	tmp |= FLD_USE_ALT_PLL_REF;
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	cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
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	mdelay(100);
}
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int cx25821_sram_channel_setup(struct cx25821_dev *dev,
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			       const struct sram_channel *ch,
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			       unsigned int bpl, u32 risc)
{
	unsigned int i, lines;
	u32 cdt;

	if (ch->cmds_start == 0) {
		cx_write(ch->ptr1_reg, 0);
		cx_write(ch->ptr2_reg, 0);
		cx_write(ch->cnt2_reg, 0);
		cx_write(ch->cnt1_reg, 0);
		return 0;
	}
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	bpl = (bpl + 7) & ~7;	/* alignment */
	cdt = ch->cdt;
	lines = ch->fifo_size / bpl;
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	if (lines > 4)
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		lines = 4;
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	BUG_ON(lines < 2);

	cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
	cx_write(8 + 4, 8);
	cx_write(8 + 8, 0);

	/* write CDT */
	for (i = 0; i < lines; i++) {
		cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
		cx_write(cdt + 16 * i + 4, 0);
		cx_write(cdt + 16 * i + 8, 0);
		cx_write(cdt + 16 * i + 12, 0);
	}

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	/* init the first cdt buffer */
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	for (i = 0; i < 128; i++)
		cx_write(ch->fifo_start + 4 * i, i);

	/* write CMDS */
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	if (ch->jumponly)
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		cx_write(ch->cmds_start + 0, 8);
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	else
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		cx_write(ch->cmds_start + 0, risc);

	cx_write(ch->cmds_start + 4, 0);	/* 64 bits 63-32 */
	cx_write(ch->cmds_start + 8, cdt);
	cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
	cx_write(ch->cmds_start + 16, ch->ctrl_start);

	if (ch->jumponly)
		cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
	else
		cx_write(ch->cmds_start + 20, 64 >> 2);

	for (i = 24; i < 80; i += 4)
		cx_write(ch->cmds_start + i, 0);

	/* fill registers */
	cx_write(ch->ptr1_reg, ch->fifo_start);
	cx_write(ch->ptr2_reg, cdt);
	cx_write(ch->cnt2_reg, (lines * 16) >> 3);
	cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
502

503
	return 0;
504 505 506
}

int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
507
				     const struct sram_channel *ch,
508
				     unsigned int bpl, u32 risc)
509
{
510 511 512 513 514 515 516 517 518 519 520 521 522 523 524
	unsigned int i, lines;
	u32 cdt;

	if (ch->cmds_start == 0) {
		cx_write(ch->ptr1_reg, 0);
		cx_write(ch->ptr2_reg, 0);
		cx_write(ch->cnt2_reg, 0);
		cx_write(ch->cnt1_reg, 0);
		return 0;
	}

	bpl = (bpl + 7) & ~7;	/* alignment */
	cdt = ch->cdt;
	lines = ch->fifo_size / bpl;

525 526
	if (lines > 3)
		lines = 3;	/* for AUDIO */
527

528 529 530 531 532 533 534 535 536 537 538 539 540 541 542
	BUG_ON(lines < 2);

	cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
	cx_write(8 + 4, 8);
	cx_write(8 + 8, 0);

	/* write CDT */
	for (i = 0; i < lines; i++) {
		cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
		cx_write(cdt + 16 * i + 4, 0);
		cx_write(cdt + 16 * i + 8, 0);
		cx_write(cdt + 16 * i + 12, 0);
	}

	/* write CMDS */
543
	if (ch->jumponly)
544
		cx_write(ch->cmds_start + 0, 8);
545
	else
546 547 548 549 550 551 552
		cx_write(ch->cmds_start + 0, risc);

	cx_write(ch->cmds_start + 4, 0);	/* 64 bits 63-32 */
	cx_write(ch->cmds_start + 8, cdt);
	cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
	cx_write(ch->cmds_start + 16, ch->ctrl_start);

553 554
	/* IQ size */
	if (ch->jumponly)
555
		cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
556
	else
557 558
		cx_write(ch->cmds_start + 20, 64 >> 2);

559
	/* zero out */
560 561 562 563 564 565 566 567
	for (i = 24; i < 80; i += 4)
		cx_write(ch->cmds_start + i, 0);

	/* fill registers */
	cx_write(ch->ptr1_reg, ch->fifo_start);
	cx_write(ch->ptr2_reg, cdt);
	cx_write(ch->cnt2_reg, (lines * 16) >> 3);
	cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
568

569
	return 0;
570
}
571
EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
572

573
void cx25821_sram_channel_dump(struct cx25821_dev *dev, const struct sram_channel *ch)
574
{
575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593
	static char *name[] = {
		"init risc lo",
		"init risc hi",
		"cdt base",
		"cdt size",
		"iq base",
		"iq size",
		"risc pc lo",
		"risc pc hi",
		"iq wr ptr",
		"iq rd ptr",
		"cdt current",
		"pci target lo",
		"pci target hi",
		"line / byte",
	};
	u32 risc;
	unsigned int i, j, n;

594
	pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
595
	for (i = 0; i < ARRAY_SIZE(name); i++)
596 597
		pr_warn("cmds + 0x%2x:   %-15s: 0x%08x\n",
			i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
598 599 600 601

	j = i * 4;
	for (i = 0; i < 4;) {
		risc = cx_read(ch->cmds_start + 4 * (i + 14));
602
		pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
603 604 605 606 607 608 609
		i += cx25821_risc_decode(risc);
	}

	for (i = 0; i < (64 >> 2); i += n) {
		risc = cx_read(ch->ctrl_start + 4 * i);
		/* No consideration for bits 63-32 */

610 611
		pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
			i * 4, ch->ctrl_start + 4 * i, i);
612 613 614
		n = cx25821_risc_decode(risc);
		for (j = 1; j < n; j++) {
			risc = cx_read(ch->ctrl_start + 4 * (i + j));
615 616
			pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
				4 * (i + j), i + j, risc, j);
617
		}
618
	}
619

620 621 622 623 624 625 626 627 628 629 630 631
	pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
		ch->fifo_start, ch->fifo_start + ch->fifo_size);
	pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
		ch->ctrl_start, ch->ctrl_start + 6 * 16);
	pr_warn("        :   ptr1_reg: 0x%08x\n",
		cx_read(ch->ptr1_reg));
	pr_warn("        :   ptr2_reg: 0x%08x\n",
		cx_read(ch->ptr2_reg));
	pr_warn("        :   cnt1_reg: 0x%08x\n",
		cx_read(ch->cnt1_reg));
	pr_warn("        :   cnt2_reg: 0x%08x\n",
		cx_read(ch->cnt2_reg));
632 633
}

634
void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
635
				     const struct sram_channel *ch)
636
{
637
	static const char * const name[] = {
638 639 640 641 642 643 644 645 646 647 648 649 650 651 652
		"init risc lo",
		"init risc hi",
		"cdt base",
		"cdt size",
		"iq base",
		"iq size",
		"risc pc lo",
		"risc pc hi",
		"iq wr ptr",
		"iq rd ptr",
		"cdt current",
		"pci target lo",
		"pci target hi",
		"line / byte",
	};
653 654

	u32 risc, value, tmp;
655
	unsigned int i, j, n;
656

657 658
	pr_info("\n%s: %s - dma Audio channel status dump\n",
		dev->name, ch->name);
659

660
	for (i = 0; i < ARRAY_SIZE(name); i++)
661 662 663
		pr_info("%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
			dev->name, i * 4, name[i],
			cx_read(ch->cmds_start + 4 * i));
664

665 666 667
	j = i * 4;
	for (i = 0; i < 4;) {
		risc = cx_read(ch->cmds_start + 4 * (i + 14));
668
		pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
669 670
		i += cx25821_risc_decode(risc);
	}
671

672 673 674
	for (i = 0; i < (64 >> 2); i += n) {
		risc = cx_read(ch->ctrl_start + 4 * i);
		/* No consideration for bits 63-32 */
675

676 677
		pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
			i * 4, ch->ctrl_start + 4 * i, i);
678
		n = cx25821_risc_decode(risc);
679

680 681
		for (j = 1; j < n; j++) {
			risc = cx_read(ch->ctrl_start + 4 * (i + j));
682 683
			pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
				4 * (i + j), i + j, risc, j);
684 685
		}
	}
686

687 688 689 690 691 692 693 694 695 696 697 698
	pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
		ch->fifo_start, ch->fifo_start + ch->fifo_size);
	pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
		ch->ctrl_start, ch->ctrl_start + 6 * 16);
	pr_warn("        :   ptr1_reg: 0x%08x\n",
		cx_read(ch->ptr1_reg));
	pr_warn("        :   ptr2_reg: 0x%08x\n",
		cx_read(ch->ptr2_reg));
	pr_warn("        :   cnt1_reg: 0x%08x\n",
		cx_read(ch->cnt1_reg));
	pr_warn("        :   cnt2_reg: 0x%08x\n",
		cx_read(ch->cnt2_reg));
699 700 701

	for (i = 0; i < 4; i++) {
		risc = cx_read(ch->cmds_start + 56 + (i * 4));
702
		pr_warn("instruction %d = 0x%x\n", i, risc);
703
	}
704

705
	/* read data from the first cdt buffer */
706
	risc = cx_read(AUD_A_CDT);
707
	pr_warn("\nread cdt loc=0x%x\n", risc);
708 709
	for (i = 0; i < 8; i++) {
		n = cx_read(risc + i * 4);
710
		pr_cont("0x%x ", n);
711
	}
712
	pr_cont("\n\n");
713 714

	value = cx_read(CLK_RST);
715
	CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
716 717

	value = cx_read(PLL_A_POST_STAT_BIST);
718
	CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
719
	value = cx_read(PLL_A_INT_FRAC);
720
	CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
721 722

	value = cx_read(PLL_B_POST_STAT_BIST);
723
	CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
724
	value = cx_read(PLL_B_INT_FRAC);
725
	CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
726 727

	value = cx_read(PLL_C_POST_STAT_BIST);
728
	CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
729
	value = cx_read(PLL_C_INT_FRAC);
730
	CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
731 732

	value = cx_read(PLL_D_POST_STAT_BIST);
733
	CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
734
	value = cx_read(PLL_D_INT_FRAC);
735
	CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
736 737

	value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
738
	CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
739
}
740
EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
741 742 743

static void cx25821_shutdown(struct cx25821_dev *dev)
{
744
	int i;
745

746 747
	/* disable RISC controller */
	cx_write(DEV_CNTRL2, 0);
748

749 750
	/* Disable Video A/B activity */
	for (i = 0; i < VID_CHANNEL_NUM; i++) {
751 752
		cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
		cx_write(dev->channels[i].sram_channels->int_msk, 0);
753
	}
754

755 756 757 758
	for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
		i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
		cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
		cx_write(dev->channels[i].sram_channels->int_msk, 0);
759
	}
760

761 762
	/* Disable Audio activity */
	cx_write(AUD_INT_DMA_CTL, 0);
763

764 765
	/* Disable Serial port */
	cx_write(UART_CTL, 0);
766

767 768 769
	/* Disable Interrupts */
	cx_write(PCI_INT_MSK, 0);
	cx_write(AUD_A_INT_MSK, 0);
770 771
}

772 773
void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
			      u32 format)
774
{
775
	if (channel_select <= 7 && channel_select >= 0) {
776 777
		cx_write(dev->channels[channel_select].sram_channels->pix_frmt,
				format);
778
	}
779
	dev->channels[channel_select].pixel_formats = format;
780 781
}

782
static void cx25821_set_vip_mode(struct cx25821_dev *dev,
783
				 const struct sram_channel *ch)
784
{
785 786
	cx_write(ch->pix_frmt, PIXEL_FRMT_422);
	cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
787 788 789 790
}

static void cx25821_initialize(struct cx25821_dev *dev)
{
791
	int i;
792

793
	dprintk(1, "%s()\n", __func__);
794

795 796
	cx25821_shutdown(dev);
	cx_write(PCI_INT_STAT, 0xffffffff);
797

798
	for (i = 0; i < VID_CHANNEL_NUM; i++)
799
		cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
800

801 802 803 804 805
	cx_write(AUD_A_INT_STAT, 0xffffffff);
	cx_write(AUD_B_INT_STAT, 0xffffffff);
	cx_write(AUD_C_INT_STAT, 0xffffffff);
	cx_write(AUD_D_INT_STAT, 0xffffffff);
	cx_write(AUD_E_INT_STAT, 0xffffffff);
806

807
	cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
808 809
	cx_write(PAD_CTRL, 0x12);	/* for I2C */
	cx25821_registers_init(dev);	/* init Pecos registers */
810
	mdelay(100);
811

812
	for (i = 0; i < VID_CHANNEL_NUM; i++) {
813 814 815 816
		cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
		cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
						1440, 0);
		dev->channels[i].pixel_formats = PIXEL_FRMT_422;
817
		dev->channels[i].use_cif_resolution = 0;
818
	}
819

820
	/* Probably only affect Downstream */
821 822
	for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
		i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
823
		dev->channels[i].pixel_formats = PIXEL_FRMT_422;
824
		cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
825
	}
826

827
	cx25821_sram_channel_setup_audio(dev,
828
			dev->channels[SRAM_CH08].sram_channels, 128, 0);
829

830
	cx25821_gpio_init(dev);
831 832
}

833
static int cx25821_get_resources(struct cx25821_dev *dev)
834
{
835 836
	if (request_mem_region(pci_resource_start(dev->pci, 0),
				pci_resource_len(dev->pci, 0), dev->name))
837
		return 0;
838

839
	pr_err("%s: can't get MMIO memory @ 0x%llx\n",
840
		dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
841

842
	return -EBUSY;
843 844 845 846
}

static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
{
847
	dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
848

849
	pr_info("Hardware revision = 0x%02x\n", dev->hwrevision);
850 851 852 853
}

static void cx25821_iounmap(struct cx25821_dev *dev)
{
854 855 856 857 858 859 860 861
	if (dev == NULL)
		return;

	/* Releasing IO memory */
	if (dev->lmmio != NULL) {
		iounmap(dev->lmmio);
		dev->lmmio = NULL;
	}
862 863 864
}

static int cx25821_dev_setup(struct cx25821_dev *dev)
865
{
866
	static unsigned int cx25821_devcount;
867
	int i;
868 869 870 871 872 873

	mutex_init(&dev->lock);

	dev->nr = ++cx25821_devcount;
	sprintf(dev->name, "cx25821[%d]", dev->nr);

874 875 876 877
	if (dev->nr >= ARRAY_SIZE(card)) {
		CX25821_INFO("dev->nr >= %zd", ARRAY_SIZE(card));
		return -ENODEV;
	}
878
	if (dev->pci->device != 0x8210) {
879 880
		pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
			__func__, dev->pci->device);
881
		return -ENODEV;
882
	}
883
	pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
884

885 886
	/* Apply a sensible clock frequency for the PCIe bridge */
	dev->clk_freq = 28000000;
887 888 889
	for (i = 0; i < MAX_VID_CHANNEL_NUM; i++) {
		dev->channels[i].dev = dev;
		dev->channels[i].id = i;
890
		dev->channels[i].sram_channels = &cx25821_sram_channels[i];
891
	}
892

893
	/* board config */
894
	dev->board = 1;		/* card[dev->nr]; */
895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
	dev->_max_num_decoders = MAX_DECODERS;

	dev->pci_bus = dev->pci->bus->number;
	dev->pci_slot = PCI_SLOT(dev->pci->devfn);
	dev->pci_irqmask = 0x001f00;

	/* External Master 1 Bus */
	dev->i2c_bus[0].nr = 0;
	dev->i2c_bus[0].dev = dev;
	dev->i2c_bus[0].reg_stat = I2C1_STAT;
	dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
	dev->i2c_bus[0].reg_addr = I2C1_ADDR;
	dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
	dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
	dev->i2c_bus[0].i2c_period = (0x07 << 24);	/* 1.95MHz */

911
	if (cx25821_get_resources(dev) < 0) {
912
		pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
913 914 915 916
		       dev->name, dev->pci->subsystem_vendor,
		       dev->pci->subsystem_device);

		cx25821_devcount--;
917
		return -EBUSY;
918
	}
919

920 921
	/* PCIe stuff */
	dev->base_io_addr = pci_resource_start(dev->pci, 0);
922

923 924 925 926
	if (!dev->base_io_addr) {
		CX25821_ERR("No PCI Memory resources, exiting!\n");
		return -ENODEV;
	}
927

928
	dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
929

930
	if (!dev->lmmio) {
931
		CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
932 933 934 935 936
		cx25821_iounmap(dev);
		return -ENOMEM;
	}

	dev->bmmio = (u8 __iomem *) dev->lmmio;
937

938 939 940 941 942
	pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
		dev->name, dev->pci->subsystem_vendor,
		dev->pci->subsystem_device, cx25821_boards[dev->board].name,
		dev->board, card[dev->nr] == dev->board ?
		"insmod option" : "autodetected");
943

944 945
	/* init hardware */
	cx25821_initialize(dev);
946

947
	cx25821_i2c_register(&dev->i2c_bus[0]);
948 949
/*  cx25821_i2c_register(&dev->i2c_bus[1]);
 *  cx25821_i2c_register(&dev->i2c_bus[2]); */
950

951
	if (medusa_video_init(dev) < 0)
952
		CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
953

954
	cx25821_video_register(dev);
955

956 957
	cx25821_dev_checkrevision(dev);
	return 0;
958
}
959 960 961

void cx25821_dev_unregister(struct cx25821_dev *dev)
{
962
	int i;
963

964 965
	if (!dev->base_io_addr)
		return;
966

967
	release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
968

969
	for (i = 0; i < MAX_VID_CAP_CHANNEL_NUM - 1; i++) {
970 971
		if (i == SRAM_CH08) /* audio channel */
			continue;
972 973 974
		/*
		 * TODO: enable when video output is properly
		 * supported.
975 976
		if (i == SRAM_CH09 || i == SRAM_CH10)
			cx25821_free_mem_upstream(&dev->channels[i]);
977
		 */
978 979
		cx25821_video_unregister(dev, i);
	}
980

981 982
	cx25821_i2c_unregister(&dev->i2c_bus[0]);
	cx25821_iounmap(dev);
983
}
984
EXPORT_SYMBOL(cx25821_dev_unregister);
985

986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006
int cx25821_riscmem_alloc(struct pci_dev *pci,
		       struct cx25821_riscmem *risc,
		       unsigned int size)
{
	__le32 *cpu;
	dma_addr_t dma = 0;

	if (NULL != risc->cpu && risc->size < size)
		pci_free_consistent(pci, risc->size, risc->cpu, risc->dma);
	if (NULL == risc->cpu) {
		cpu = pci_zalloc_consistent(pci, size, &dma);
		if (NULL == cpu)
			return -ENOMEM;
		risc->cpu  = cpu;
		risc->dma  = dma;
		risc->size = size;
	}
	return 0;
}
EXPORT_SYMBOL(cx25821_riscmem_alloc);

1007 1008 1009
static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
				  unsigned int offset, u32 sync_line,
				  unsigned int bpl, unsigned int padding,
1010
				  unsigned int lines, bool jump)
1011
{
1012 1013 1014
	struct scatterlist *sg;
	unsigned int line, todo;

1015 1016 1017 1018 1019 1020
	if (jump) {
		*(rp++) = cpu_to_le32(RISC_JUMP);
		*(rp++) = cpu_to_le32(0);
		*(rp++) = cpu_to_le32(0); /* bits 63-32 */
	}

1021
	/* sync instruction */
1022
	if (sync_line != NO_SYNC_LINE)
1023
		*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1024

1025 1026 1027 1028 1029
	/* scan lines */
	sg = sglist;
	for (line = 0; line < lines; line++) {
		while (offset && offset >= sg_dma_len(sg)) {
			offset -= sg_dma_len(sg);
1030
			sg = sg_next(sg);
1031 1032 1033
		}
		if (bpl <= sg_dma_len(sg) - offset) {
			/* fits into current chunk */
1034 1035
			*(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL |
					bpl);
1036 1037 1038 1039 1040 1041
			*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			offset += bpl;
		} else {
			/* scanline needs to be split */
			todo = bpl;
1042
			*(rp++) = cpu_to_le32(RISC_WRITE | RISC_SOL |
1043 1044 1045 1046 1047
					(sg_dma_len(sg) - offset));
			*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			todo -= (sg_dma_len(sg) - offset);
			offset = 0;
1048
			sg = sg_next(sg);
1049
			while (todo > sg_dma_len(sg)) {
1050 1051
				*(rp++) = cpu_to_le32(RISC_WRITE |
						sg_dma_len(sg));
1052 1053 1054
				*(rp++) = cpu_to_le32(sg_dma_address(sg));
				*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
				todo -= sg_dma_len(sg);
1055
				sg = sg_next(sg);
1056 1057 1058 1059 1060 1061 1062 1063 1064
			}
			*(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
			*(rp++) = cpu_to_le32(sg_dma_address(sg));
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			offset += todo;
		}

		offset += padding;
	}
1065

1066
	return rp;
1067 1068
}

1069
int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
1070 1071 1072
			struct scatterlist *sglist, unsigned int top_offset,
			unsigned int bottom_offset, unsigned int bpl,
			unsigned int padding, unsigned int lines)
1073
{
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
	u32 instructions;
	u32 fields;
	__le32 *rp;
	int rc;

	fields = 0;
	if (UNSET != top_offset)
		fields++;
	if (UNSET != bottom_offset)
		fields++;

	/* estimate risc mem: worst case is one write per page border +
1086
	   one write per scan line + syncs + jump (all 3 dwords).  Padding
1087 1088 1089
	   can cause next bpl to start close to a page border.  First DMA
	   region may be smaller than PAGE_SIZE */
	/* write and jump need and extra dword */
1090 1091
	instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE +
			lines);
1092
	instructions += 5;
1093
	rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1094 1095 1096 1097 1098 1099 1100 1101 1102

	if (rc < 0)
		return rc;

	/* write risc instructions */
	rp = risc->cpu;

	if (UNSET != top_offset) {
		rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1103
					lines, true);
1104
	}
1105

1106 1107
	if (UNSET != bottom_offset) {
		rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1108
					padding, lines, UNSET == top_offset);
1109 1110
	}

1111 1112
	/* save pointer to jmp instruction address */
	risc->jmp = rp;
1113
	BUG_ON((risc->jmp - risc->cpu + 3) * sizeof(*risc->cpu) > risc->size);
1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134

	return 0;
}

static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
					unsigned int offset, u32 sync_line,
					unsigned int bpl, unsigned int padding,
					unsigned int lines, unsigned int lpi)
{
	struct scatterlist *sg;
	unsigned int line, todo, sol;

	/* sync instruction */
	if (sync_line != NO_SYNC_LINE)
		*(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);

	/* scan lines */
	sg = sglist;
	for (line = 0; line < lines; line++) {
		while (offset && offset >= sg_dma_len(sg)) {
			offset -= sg_dma_len(sg);
1135
			sg = sg_next(sg);
1136 1137 1138 1139 1140 1141 1142 1143 1144
		}

		if (lpi && line > 0 && !(line % lpi))
			sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
		else
			sol = RISC_SOL;

		if (bpl <= sg_dma_len(sg) - offset) {
			/* fits into current chunk */
1145 1146
			*(rp++) = cpu_to_le32(RISC_WRITE | sol | RISC_EOL |
					bpl);
1147 1148 1149 1150 1151 1152 1153
			*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			offset += bpl;
		} else {
			/* scanline needs to be split */
			todo = bpl;
			*(rp++) = cpu_to_le32(RISC_WRITE | sol |
1154
					(sg_dma_len(sg) - offset));
1155 1156 1157 1158
			*(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			todo -= (sg_dma_len(sg) - offset);
			offset = 0;
1159
			sg = sg_next(sg);
1160 1161
			while (todo > sg_dma_len(sg)) {
				*(rp++) = cpu_to_le32(RISC_WRITE |
1162
						sg_dma_len(sg));
1163 1164 1165
				*(rp++) = cpu_to_le32(sg_dma_address(sg));
				*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
				todo -= sg_dma_len(sg);
1166
				sg = sg_next(sg);
1167 1168 1169 1170 1171 1172 1173
			}
			*(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
			*(rp++) = cpu_to_le32(sg_dma_address(sg));
			*(rp++) = cpu_to_le32(0);	/* bits 63-32 */
			offset += todo;
		}
		offset += padding;
1174
	}
1175

1176
	return rp;
1177 1178 1179
}

int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1180
				  struct cx25821_riscmem *risc,
1181 1182 1183
				  struct scatterlist *sglist,
				  unsigned int bpl,
				  unsigned int lines, unsigned int lpi)
1184
{
1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196
	u32 instructions;
	__le32 *rp;
	int rc;

	/* estimate risc mem: worst case is one write per page border +
	   one write per scan line + syncs + jump (all 2 dwords).  Here
	   there is no padding and no sync.  First DMA region may be smaller
	   than PAGE_SIZE */
	/* Jump and write need an extra dword */
	instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
	instructions += 1;

1197
	rc = cx25821_riscmem_alloc(pci, risc, instructions * 12);
1198
	if (rc < 0)
1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
		return rc;

	/* write risc instructions */
	rp = risc->cpu;
	rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
				      lines, lpi);

	/* save pointer to jmp instruction address */
	risc->jmp = rp;
	BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
	return 0;
1210
}
1211
EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1212

1213
void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf)
1214
{
1215
	BUG_ON(in_interrupt());
1216 1217 1218
	if (WARN_ON(buf->risc.size == 0))
		return;
	pci_free_consistent(dev->pci,
1219
			buf->risc.size, buf->risc.cpu, buf->risc.dma);
1220
	memset(&buf->risc, 0, sizeof(buf->risc));
1221 1222 1223 1224
}

static irqreturn_t cx25821_irq(int irq, void *dev_id)
{
1225
	struct cx25821_dev *dev = dev_id;
1226
	u32 pci_status;
1227 1228 1229
	u32 vid_status;
	int i, handled = 0;
	u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1230

1231
	pci_status = cx_read(PCI_INT_STAT);
1232

1233 1234
	if (pci_status == 0)
		goto out;
1235

1236 1237
	for (i = 0; i < VID_CHANNEL_NUM; i++) {
		if (pci_status & mask[i]) {
1238 1239
			vid_status = cx_read(dev->channels[i].
				sram_channels->int_stat);
1240

1241
			if (vid_status)
1242 1243
				handled += cx25821_video_irq(dev, i,
						vid_status);
1244

1245 1246
			cx_write(PCI_INT_STAT, mask[i]);
		}
1247 1248
	}

1249
out:
1250
	return IRQ_RETVAL(handled);
1251 1252 1253
}

void cx25821_print_irqbits(char *name, char *tag, char **strings,
1254
			   int len, u32 bits, u32 mask)
1255
{
1256 1257
	unsigned int i;

1258
	printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1259 1260 1261 1262 1263

	for (i = 0; i < len; i++) {
		if (!(bits & (1 << i)))
			continue;
		if (strings[i])
1264
			pr_cont(" %s", strings[i]);
1265
		else
1266
			pr_cont(" %d", i);
1267 1268
		if (!(mask & (1 << i)))
			continue;
1269
		pr_cont("*");
1270
	}
1271
	pr_cont("\n");
1272
}
1273
EXPORT_SYMBOL(cx25821_print_irqbits);
1274

1275
struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1276
{
1277 1278
	struct cx25821_dev *dev = pci_get_drvdata(pci);
	return dev;
1279
}
1280
EXPORT_SYMBOL(cx25821_dev_get);
1281

1282 1283
static int cx25821_initdev(struct pci_dev *pci_dev,
			   const struct pci_device_id *pci_id)
1284
{
1285 1286
	struct cx25821_dev *dev;
	int err = 0;
1287

1288 1289 1290
	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	if (NULL == dev)
		return -ENOMEM;
1291

1292 1293 1294
	err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
	if (err < 0)
		goto fail_free;
1295

1296 1297 1298 1299
	/* pci init */
	dev->pci = pci_dev;
	if (pci_enable_device(pci_dev)) {
		err = -EIO;
1300

1301
		pr_info("pci enable failed!\n");
1302

1303 1304
		goto fail_unregister_device;
	}
1305

1306
	err = cx25821_dev_setup(dev);
1307
	if (err)
1308
		goto fail_unregister_pci;
1309

1310 1311 1312
	/* print pci info */
	pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
	pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1313 1314 1315
	pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
		dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
		dev->pci_lat, (unsigned long long)dev->base_io_addr);
1316 1317

	pci_set_master(pci_dev);
1318 1319
	err = pci_set_dma_mask(pci_dev, 0xffffffff);
	if (err) {
1320
		pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1321 1322 1323
		err = -EIO;
		goto fail_irq;
	}
1324

1325 1326
	err = request_irq(pci_dev->irq, cx25821_irq,
			IRQF_SHARED, dev->name, dev);
1327

1328
	if (err < 0) {
1329
		pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1330 1331
		goto fail_irq;
	}
1332

1333
	return 0;
1334

1335
fail_irq:
1336
	pr_info("cx25821_initdev() can't get IRQ !\n");
1337
	cx25821_dev_unregister(dev);
1338

1339 1340
fail_unregister_pci:
	pci_disable_device(pci_dev);
1341
fail_unregister_device:
1342
	v4l2_device_unregister(&dev->v4l2_dev);
1343

1344
fail_free:
1345 1346
	kfree(dev);
	return err;
1347 1348
}

1349
static void cx25821_finidev(struct pci_dev *pci_dev)
1350
{
1351 1352
	struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
	struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1353

1354 1355
	cx25821_shutdown(dev);
	pci_disable_device(pci_dev);
1356

1357 1358 1359
	/* unregister stuff */
	if (pci_dev->irq)
		free_irq(pci_dev->irq, dev);
1360

1361 1362 1363
	cx25821_dev_unregister(dev);
	v4l2_device_unregister(v4l2_dev);
	kfree(dev);
1364 1365
}

1366
static const struct pci_device_id cx25821_pci_tbl[] = {
1367
	{
1368 1369 1370 1371 1372
		/* CX25821 Athena */
		.vendor = 0x14f1,
		.device = 0x8210,
		.subvendor = 0x14f1,
		.subdevice = 0x0920,
1373 1374 1375 1376 1377 1378 1379
	}, {
		/* CX25821 No Brand */
		.vendor = 0x14f1,
		.device = 0x8210,
		.subvendor = 0x0000,
		.subdevice = 0x0000,
	}, {
1380 1381
		/* --- end of list --- */
	}
1382 1383 1384 1385
};

MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);

1386 1387 1388 1389
static struct pci_driver cx25821_pci_driver = {
	.name = "cx25821",
	.id_table = cx25821_pci_tbl,
	.probe = cx25821_initdev,
1390
	.remove = cx25821_finidev,
1391 1392 1393
	/* TODO */
	.suspend = NULL,
	.resume = NULL,
1394 1395
};

1396
static int __init cx25821_init(void)
1397
{
1398 1399 1400 1401
	pr_info("driver version %d.%d.%d loaded\n",
		(CX25821_VERSION_CODE >> 16) & 0xff,
		(CX25821_VERSION_CODE >> 8) & 0xff,
		CX25821_VERSION_CODE & 0xff);
1402
	return pci_register_driver(&cx25821_pci_driver);
1403 1404
}

1405
static void __exit cx25821_fini(void)
1406
{
1407
	pci_unregister_driver(&cx25821_pci_driver);
1408 1409 1410 1411
}

module_init(cx25821_init);
module_exit(cx25821_fini);