iSeries_pci.c 22.2 KB
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#define PCIFR(...)
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/*
 * iSeries_pci.c
 *
 * Copyright (C) 2001 Allan Trautman, IBM Corporation
 *
 * iSeries specific routines for PCI.
 * 
 * Based on code from pci.c and iSeries_pci.c 32bit
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
#include <linux/kernel.h>
#include <linux/list.h> 
#include <linux/string.h>
#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/ide.h>
#include <linux/pci.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/ppcdebug.h>
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#include <asm/naca.h>
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#include <asm/iommu.h>
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#include <asm/iSeries/HvCallPci.h>
#include <asm/iSeries/HvCallSm.h>
#include <asm/iSeries/HvCallXm.h>
#include <asm/iSeries/LparData.h>
#include <asm/iSeries/iSeries_irq.h>
#include <asm/iSeries/iSeries_pci.h>
#include <asm/iSeries/mf.h>

#include "iSeries_IoMmTable.h"
#include "pci.h"

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extern int panic_timeout;
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extern unsigned long iSeries_Base_Io_Memory;    

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extern struct iommu_table *tceTables[256];
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extern void iSeries_MmIoTest(void);

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/*
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 * Forward declares of prototypes. 
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 */
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static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
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static void iSeries_Scan_PHBs_Slots(struct pci_controller *Phb);
static void iSeries_Scan_EADs_Bridge(HvBusNumber Bus, HvSubBusNumber SubBus,
		int IdSel);
static int iSeries_Scan_Bridge_Slot(HvBusNumber Bus,
		struct HvCallPci_BridgeInfo *Info);
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LIST_HEAD(iSeries_Global_Device_List);
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static int DeviceCount;
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/* Counters and control flags. */
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static long Pci_Io_Read_Count;
static long Pci_Io_Write_Count;
#if 0
static long Pci_Cfg_Read_Count;
static long Pci_Cfg_Write_Count;
#endif
static long Pci_Error_Count;

static int Pci_Retry_Max = 3;	/* Only retry 3 times  */	
static int Pci_Error_Flag = 1;	/* Set Retry Error on. */
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static struct pci_ops iSeries_pci_ops;
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/*
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 * Log Error infor in Flight Recorder to system Console.
 * Filter out the device not there errors.
 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
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 */
static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
		int AgentId, int HvRc)
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{
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	if (HvRc == 0x0302)
		return;
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	printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
	       Error_Text, Bus, SubBus, AgentId, HvRc);
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}

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/*
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 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
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 */
static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
		HvSubBusNumber SubBus, int AgentId, int Function)
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{
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	struct iSeries_Device_Node *node;
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	PPCDBG(PPCDBG_BUSWALK,
			"-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
			Bus, SubBus, AgentId, Function);
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	node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
	if (node == NULL)
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		return NULL;
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	memset(node, 0, sizeof(struct iSeries_Device_Node));
	list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
#if 0
	node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
#endif
	node->DsaAddr.DsaAddr = 0;
	node->DsaAddr.Dsa.busNumber = Bus;
	node->DsaAddr.Dsa.subBusNumber = SubBus;
	node->DsaAddr.Dsa.deviceId = 0x10;
	node->AgentId = AgentId;
	node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
	node->IoRetry = 0;
	iSeries_Get_Location_Code(node);
	PCIFR("Device 0x%02X.%2X, Node:0x%p ", ISERIES_BUS(node),
			ISERIES_DEVFUN(node), node);
	return node;
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}

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/*
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 * unsigned long __init find_and_init_phbs(void)
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 *
 * Description:
 *   This function checks for all possible system PCI host bridges that connect
 *   PCI buses.  The system hypervisor is queried as to the guest partition
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 *   ownership status.  A pci_controller is built for any bus which is partially
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 *   owned or fully owned by this guest partition.
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 */
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unsigned long __init find_and_init_phbs(void)
{
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	struct pci_controller *phb;
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	HvBusNumber bus;
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	PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
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	/* Check all possible buses. */
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	for (bus = 0; bus < 256; bus++) {
		int ret = HvCallXm_testBus(bus);
		if (ret == 0) {
			printk("bus %d appears to exist\n", bus);
			phb = pci_alloc_pci_controller(phb_type_hypervisor);
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			if (phb == NULL) {
				PCIFR("Allocate pci_controller failed.");
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				return -1;
			}
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			phb->pci_mem_offset = phb->local_number = bus;
			phb->first_busno = bus;
			phb->last_busno = bus;
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			phb->ops = &iSeries_pci_ops;
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			PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
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					phb, bus);
			PCIFR("Create iSeries PHB controller: %04X", bus);
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			/* Find and connect the devices. */
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			iSeries_Scan_PHBs_Slots(phb);
		}
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		/*
		 * Check for Unexpected Return code, a clue that something
		 * has gone wrong.
		 */
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		else if (ret != 0x0301)
			printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
			       bus, ret);
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	}
	return 0;
}
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/*
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 * iSeries_pcibios_init
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 *  
 * Chance to initialize and structures or variable before PCI Bus walk.
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 */
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void iSeries_pcibios_init(void)
{
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	PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n"); 
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	iSeries_IoMmTable_Initialize();
	find_and_init_phbs();
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	/* pci_assign_all_busses = 0;		SFRXXX*/
	PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n"); 
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}
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/*
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 * iSeries_pci_final_fixup(void)  
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 */
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void __init iSeries_pci_final_fixup(void)
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{
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	struct pci_dev *pdev = NULL;
	struct iSeries_Device_Node *node;
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	char Buffer[256];
    	int DeviceCount = 0;

	PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n"); 
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	/* Fix up at the device node and pci_dev relationship */
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	mf_displaySrc(0xC9000100);

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	printk("pcibios_final_fixup\n");
	while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))
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			!= NULL) {
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		node = find_Device_Node(pdev->bus->number, pdev->devfn);
		printk("pci dev %p (%x.%x), node %p\n", pdev,
		       pdev->bus->number, pdev->devfn, node);

		if (node != NULL) {
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			++DeviceCount;
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			pdev->sysdata = (void *)node;
			node->PciDev = pdev;
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			PPCDBG(PPCDBG_BUSWALK,
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					"pdev 0x%p <==> DevNode 0x%p\n",
					pdev, node);
			iSeries_allocateDeviceBars(pdev);
			iSeries_Device_Information(pdev, Buffer,
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					sizeof(Buffer));
			printk("%d. %s\n", DeviceCount, Buffer);
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			iommu_devnode_init(node);
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		} else
			printk("PCI: Device Tree not found for 0x%016lX\n",
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					(unsigned long)pdev);
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		pdev->irq = node->Irq;
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	}
	iSeries_IoMmTable_Status();
	iSeries_activate_IRQs();
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	mf_displaySrc(0xC9000200);
}

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void pcibios_fixup_bus(struct pci_bus *PciBus)
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{
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	PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
			PciBus->number); 
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}

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void pcibios_fixup_resources(struct pci_dev *pdev)
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{
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	PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
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}   

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/*
 * Loop through each node function to find usable EADs bridges.  
 */
static void iSeries_Scan_PHBs_Slots(struct pci_controller *Phb)
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{
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	struct HvCallPci_DeviceInfo *DevInfo;
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	HvBusNumber bus = Phb->local_number;	/* System Bus */	
	const HvSubBusNumber SubBus = 0;	/* EADs is always 0. */
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	int HvRc = 0;
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	int IdSel;	
	const int MaxAgents = 8;
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	DevInfo = (struct HvCallPci_DeviceInfo*)
		kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
	if (DevInfo == NULL)
		return;
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	/*
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	 * Probe for EADs Bridges      
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	 */
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	for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
    		HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
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				ISERIES_HV_ADDR(DevInfo),
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				sizeof(struct HvCallPci_DeviceInfo));
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		if (HvRc == 0) {
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			if (DevInfo->deviceType == HvCallPci_NodeDevice)
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				iSeries_Scan_EADs_Bridge(bus, SubBus, IdSel);
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			else
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				printk("PCI: Invalid System Configuration(0x%02X)"
				       " for bus 0x%02x id 0x%02x.\n",
				       DevInfo->deviceType, bus, IdSel);
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		}
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		else
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			pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
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	}
	kfree(DevInfo);
}

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static void iSeries_Scan_EADs_Bridge(HvBusNumber bus, HvSubBusNumber SubBus,
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		int IdSel)
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{
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	struct HvCallPci_BridgeInfo *BridgeInfo;
	HvAgentId AgentId;
	int Function;
	int HvRc;
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	BridgeInfo = (struct HvCallPci_BridgeInfo *)
		kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
	if (BridgeInfo == NULL)
		return;
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	/* Note: hvSubBus and irq is always be 0 at this level! */
	for (Function = 0; Function < 8; ++Function) {
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	  	AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
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		HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
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 		if (HvRc == 0) {
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			printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
			       bus, IdSel, Function, AgentId);
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  			/*  Connect EADs: 0x18.00.12 = 0x00 */
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			PPCDBG(PPCDBG_BUSWALK,
					"PCI:Connect EADs: 0x%02X.%02X.%02X\n",
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					bus, SubBus, AgentId);
	    		HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
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					ISERIES_HV_ADDR(BridgeInfo),
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					sizeof(struct HvCallPci_BridgeInfo));
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	 		if (HvRc == 0) {
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				printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
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					BridgeInfo->busUnitInfo.deviceType,
					BridgeInfo->subBusNumber,
					BridgeInfo->maxAgents,
					BridgeInfo->maxSubBusNumber,
					BridgeInfo->logicalSlotNumber);
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				PPCDBG(PPCDBG_BUSWALK,
					"PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
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					BridgeInfo->busUnitInfo.deviceType,
					BridgeInfo->subBusNumber,
					BridgeInfo->maxAgents,
					BridgeInfo->maxSubBusNumber,
					BridgeInfo->logicalSlotNumber);

				if (BridgeInfo->busUnitInfo.deviceType ==
						HvCallPci_BridgeDevice)  {
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					/* Scan_Bridge_Slot...: 0x18.00.12 */
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					iSeries_Scan_Bridge_Slot(bus, BridgeInfo);
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				} else
					printk("PCI: Invalid Bridge Configuration(0x%02X)",
						BridgeInfo->busUnitInfo.deviceType);
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			}
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    		} else if (HvRc != 0x000B)
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			pci_Log_Error("EADs Connect",
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					bus, SubBus, AgentId, HvRc);
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	}
	kfree(BridgeInfo);
}

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/*
 * This assumes that the node slot is always on the primary bus!
 */
static int iSeries_Scan_Bridge_Slot(HvBusNumber Bus,
		struct HvCallPci_BridgeInfo *BridgeInfo)
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{
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	struct iSeries_Device_Node *node;
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	HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
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	u16 VendorId = 0;
	int HvRc = 0;
	u8 Irq = 0;
	int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
	int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
	HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);

	/* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
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  	Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
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	PPCDBG(PPCDBG_BUSWALK,
		"PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
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		Bus, 0, EADsIdSel, Irq);
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	/*
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	 * Connect all functions of any device found.  
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	 */
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  	for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
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    		for (Function = 0; Function < 8; ++Function) {
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			HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
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			HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
					AgentId, Irq);
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			if (HvRc != 0) {
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				pci_Log_Error("Connect Bus Unit",
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					      Bus, SubBus, AgentId, HvRc);
				continue;
			}

			HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
						      PCI_VENDOR_ID, &VendorId);
			if (HvRc != 0) {
				pci_Log_Error("Read Vendor",
					      Bus, SubBus, AgentId, HvRc);
				continue;
			}
			printk("read vendor ID: %x\n", VendorId);

			/* FoundDevice: 0x18.28.10 = 0x12AE */
			PPCDBG(PPCDBG_BUSWALK,
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			       "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
			       Bus, SubBus, AgentId, VendorId, Irq);
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			HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
						      PCI_INTERRUPT_LINE, Irq);  
			if (HvRc != 0)
				pci_Log_Error("PciCfgStore Irq Failed!",
					      Bus, SubBus, AgentId, HvRc);

			++DeviceCount;
			node = build_device_node(Bus, SubBus, EADsIdSel, Function);
			node->Vendor = VendorId;
			node->Irq = Irq;
			node->LogicalSlot = BridgeInfo->logicalSlotNumber;

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		} /* for (Function = 0; Function < 8; ++Function) */
	} /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
	return HvRc;
}
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/*
 * I/0 Memory copy MUST use mmio commands on iSeries
 * To do; For performance, include the hv call directly
 */
void *iSeries_memset_io(void *dest, char c, size_t Count)
{
	u8 ByteValue = c;
	long NumberOfBytes = Count;
	char *IoBuffer = dest;

	while (NumberOfBytes > 0) {
		iSeries_Write_Byte(ByteValue, (void *)IoBuffer);
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		++IoBuffer;
		-- NumberOfBytes;
	}
	return dest;
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}
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EXPORT_SYMBOL(iSeries_memset_io);
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void *iSeries_memcpy_toio(void *dest, void *source, size_t count)
{
	char *dst = dest;
	char *src = source;
	long NumberOfBytes = count;

	while (NumberOfBytes > 0) {
		iSeries_Write_Byte(*src++, (void *)dst++);
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		-- NumberOfBytes;
	}
	return dest;
}
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EXPORT_SYMBOL(iSeries_memcpy_toio);
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void *iSeries_memcpy_fromio(void *dest, void *source, size_t count)
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{
	char *dst = dest;
	char *src = source;
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	long NumberOfBytes = count;

	while (NumberOfBytes > 0) {
		*dst++ = iSeries_Read_Byte((void *)src++);
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		-- NumberOfBytes;
	}
	return dest;
}
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EXPORT_SYMBOL(iSeries_memcpy_fromio);
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/*
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 * Look down the chain to find the matching Device Device
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 */
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static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
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{
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	struct list_head *pos;
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	list_for_each(pos, &iSeries_Global_Device_List) {
		struct iSeries_Device_Node *node =
			list_entry(pos, struct iSeries_Device_Node, Device_List);
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		if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
			return node;
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	}
	return NULL;
}
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#if 0
/*
 * Returns the device node for the passed pci_dev
 * Sanity Check Node PciDev to passed pci_dev
 * If none is found, returns a NULL which the client must handle.
 */
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static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
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{
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	struct iSeries_Device_Node *node;

	node = pdev->sysdata;
	if (node == NULL || node->PciDev != pdev)
		node = find_Device_Node(pdev->bus->number, pdev->devfn);
	return node;
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}
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#endif

/*
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 * Config space read and write functions.
 * For now at least, we look for the device node for the bus and devfn
 * that we are asked to access.  It may be possible to translate the devfn
 * to a subbus and deviceid more directly.
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 */
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static u64 hv_cfg_read_func[4]  = {
	HvCallPciConfigLoad8, HvCallPciConfigLoad16,
	HvCallPciConfigLoad32, HvCallPciConfigLoad32
};
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static u64 hv_cfg_write_func[4] = {
	HvCallPciConfigStore8, HvCallPciConfigStore16,
	HvCallPciConfigStore32, HvCallPciConfigStore32
};
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/*
 * Read PCI config space
 */
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static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
		int offset, int size, u32 *val)
{
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	struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
	u64 fn;
	struct HvCallPci_LoadReturn ret;
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	if (node == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	fn = hv_cfg_read_func[(size - 1) & 3];
	HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);

	if (ret.rc != 0) {
		*val = ~0;
		return PCIBIOS_DEVICE_NOT_FOUND;	/* or something */
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	}
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	*val = ret.value;
	return 0;
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}
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/*
 * Write PCI config space
 */
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static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
		int offset, int size, u32 val)
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{
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	struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
	u64 fn;
	u64 ret;

	if (node == NULL)
		return PCIBIOS_DEVICE_NOT_FOUND;

	fn = hv_cfg_write_func[(size - 1) & 3];
	ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);

	if (ret != 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return 0;
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}

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static struct pci_ops iSeries_pci_ops = {
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	.read = iSeries_pci_read_config,
	.write = iSeries_pci_write_config
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};

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/*
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 * Check Return Code
 * -> On Failure, print and log information.
 *    Increment Retry Count, if exceeds max, panic partition.
 * -> If in retry, print and log success 
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 *
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 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
 * PCI: Device 23.90 ReadL Retry( 1)
 * PCI: Device 23.90 ReadL Retry Successful(1)
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 */
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static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
		u64 ret)
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{
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	if (ret != 0)  {
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		++Pci_Error_Count;
		++DevNode->IoRetry;
		printk("PCI: %s: Device 0x%04X:%02X  I/O Error(%2d): 0x%04X\n",
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				TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
				DevNode->IoRetry, (int)ret);
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		/*
		 * Bump the retry and check for retry count exceeded.
		 * If, Exceeded, panic the system.
		 */
		if ((DevNode->IoRetry > Pci_Retry_Max) &&
				(Pci_Error_Flag > 0)) {
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			mf_displaySrc(0xB6000103);
			panic_timeout = 0; 
595 596
			panic("PCI: Hardware I/O Error, SRC B6000103, "
					"Automatic Reboot Disabled.\n");
597 598 599
		}
		return -1;	/* Retry Try */
	}
600 601
	/* If retry was in progress, log success and rest retry count */
	if (DevNode->IoRetry > 0) {
602
		PCIFR("%s: Device 0x%04X:%02X Retry Successful(%2d).",
603
				TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
604
				DevNode->IoRetry);
605 606 607 608
		DevNode->IoRetry = 0;
	}
	return 0; 
}
609 610 611 612 613 614 615

/*
 * Translate the I/O Address into a device node, bar, and bar offset.
 * Note: Make sure the passed variable end up on the stack to avoid
 * the exposure of being device global.
 */
static inline struct iSeries_Device_Node *xlateIoMmAddress(void *IoAddress,
616
		 u64 *dsaptr, u64 *BarOffsetPtr)
617
{
618 619 620 621 622 623 624 625 626 627
	unsigned long BaseIoAddr;
	unsigned long TableIndex;
	struct iSeries_Device_Node *DevNode;

	if (((unsigned long)IoAddress < iSeries_Base_Io_Memory) ||
			((unsigned long)IoAddress >= iSeries_Max_Io_Memory))
		return NULL;
	BaseIoAddr = (unsigned long)IoAddress - iSeries_Base_Io_Memory;
	TableIndex = BaseIoAddr / iSeries_IoMmTable_Entry_Size;
	DevNode = iSeries_IoMmTable[TableIndex];
628 629

	if (DevNode != NULL) {
630 631
		int barnum = iSeries_IoBarTable[TableIndex];
		*dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
632 633
		*BarOffsetPtr = BaseIoAddr % iSeries_IoMmTable_Entry_Size;
	} else
634 635 636 637
		panic("PCI: Invalid PCI IoAddress detected!\n");
	return DevNode;
}

638 639 640 641 642 643 644 645 646 647
/*
 * Read MM I/O Instructions for the iSeries
 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
 * else, data is returned in big Endian format.
 *
 * iSeries_Read_Byte = Read Byte  ( 8 bit)
 * iSeries_Read_Word = Read Word  (16 bit)
 * iSeries_Read_Long = Read Long  (32 bit)
 */
u8 iSeries_Read_Byte(void *IoAddress)
648
{
649
	u64 BarOffset;
650 651
	u64 dsa;
	struct HvCallPci_LoadReturn ret;
652
	struct iSeries_Device_Node *DevNode =
653
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
654

655 656 657 658 659 660 661 662 663 664 665 666
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
		return 0xff;
	}
667 668
	do {
		++Pci_Io_Read_Count;
669 670
		HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
	} while (CheckReturnCode("RDB", DevNode, ret.rc) != 0);
671

672
	return (u8)ret.value;
673
}
674
EXPORT_SYMBOL(iSeries_Read_Byte);
675 676

u16 iSeries_Read_Word(void *IoAddress)
677
{
678
	u64 BarOffset;
679 680
	u64 dsa;
	struct HvCallPci_LoadReturn ret;
681
	struct iSeries_Device_Node *DevNode =
682
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
683

684 685 686 687 688 689 690 691 692 693 694 695
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
		return 0xffff;
	}
696 697
	do {
		++Pci_Io_Read_Count;
698
		HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
699
				BarOffset, 0);
700
	} while (CheckReturnCode("RDW", DevNode, ret.rc) != 0);
701

702
	return swab16((u16)ret.value);
703
}
704
EXPORT_SYMBOL(iSeries_Read_Word);
705 706

u32 iSeries_Read_Long(void *IoAddress)
707
{
708
	u64 BarOffset;
709 710
	u64 dsa;
	struct HvCallPci_LoadReturn ret;
711
	struct iSeries_Device_Node *DevNode =
712
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
713

714 715 716 717 718 719 720 721 722 723 724 725
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
		return 0xffffffff;
	}
726 727
	do {
		++Pci_Io_Read_Count;
728
		HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
729
				BarOffset, 0);
730
	} while (CheckReturnCode("RDL", DevNode, ret.rc) != 0);
731

732
	return swab32((u32)ret.value);
733
}
734
EXPORT_SYMBOL(iSeries_Read_Long);
735 736 737 738 739 740 741 742

/*
 * Write MM I/O Instructions for the iSeries
 *
 * iSeries_Write_Byte = Write Byte (8 bit)
 * iSeries_Write_Word = Write Word(16 bit)
 * iSeries_Write_Long = Write Long(32 bit)
 */
743
void iSeries_Write_Byte(u8 data, void *IoAddress)
744 745
{
	u64 BarOffset;
746 747
	u64 dsa;
	u64 rc;
748
	struct iSeries_Device_Node *DevNode =
749
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
750

751 752 753 754 755 756 757 758 759 760 761 762
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
		return;
	}
763 764
	do {
		++Pci_Io_Write_Count;
765 766
		rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
	} while (CheckReturnCode("WWB", DevNode, rc) != 0);
767
}
768
EXPORT_SYMBOL(iSeries_Write_Byte);
769

770
void iSeries_Write_Word(u16 data, void *IoAddress)
771
{
772
	u64 BarOffset;
773 774
	u64 dsa;
	u64 rc;
775
	struct iSeries_Device_Node *DevNode =
776
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
777

778 779 780 781 782 783 784 785 786 787 788 789
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
		return;
	}
790 791
	do {
		++Pci_Io_Write_Count;
792 793
		rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
	} while (CheckReturnCode("WWW", DevNode, rc) != 0);
794
}
795
EXPORT_SYMBOL(iSeries_Write_Word);
796

797
void iSeries_Write_Long(u32 data, void *IoAddress)
798
{
799
	u64 BarOffset;
800 801
	u64 dsa;
	u64 rc;
802
	struct iSeries_Device_Node *DevNode =
803
		xlateIoMmAddress(IoAddress, &dsa, &BarOffset);
804

805 806 807 808 809 810 811 812 813 814 815 816
	if (DevNode == NULL) {
		static unsigned long last_jiffies;
		static int num_printed;

		if ((jiffies - last_jiffies) > 60 * HZ) {
			last_jiffies = jiffies;
			num_printed = 0;
		}
		if (num_printed++ < 10)
			printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
		return;
	}
817 818
	do {
		++Pci_Io_Write_Count;
819 820
		rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
	} while (CheckReturnCode("WWL", DevNode, rc) != 0);
821
}
822
EXPORT_SYMBOL(iSeries_Write_Long);
823 824 825

void pcibios_name_device(struct pci_dev *dev)
{
826
}