perf_event.c 45.9 KB
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/* Performance event support for sparc64.
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 *
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 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
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 *
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 * This code is based almost entirely upon the x86 perf event
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 * code, which is:
 *
 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
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 */

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#include <linux/perf_event.h>
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#include <linux/kprobes.h>
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#include <linux/ftrace.h>
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#include <linux/kernel.h>
#include <linux/kdebug.h>
#include <linux/mutex.h>

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#include <asm/stacktrace.h>
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#include <asm/cpudata.h>
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#include <linux/uaccess.h>
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#include <linux/atomic.h>
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#include <asm/nmi.h>
#include <asm/pcr.h>
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#include <asm/cacheflush.h>
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#include "kernel.h"
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#include "kstack.h"

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/* Two classes of sparc64 chips currently exist.  All of which have
 * 32-bit counters which can generate overflow interrupts on the
 * transition from 0xffffffff to 0.
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 *
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 * All chips upto and including SPARC-T3 have two performance
 * counters.  The two 32-bit counters are accessed in one go using a
 * single 64-bit register.
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 *
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 * On these older chips both counters are controlled using a single
 * control register.  The only way to stop all sampling is to clear
 * all of the context (user, supervisor, hypervisor) sampling enable
 * bits.  But these bits apply to both counters, thus the two counters
 * can't be enabled/disabled individually.
 *
 * Furthermore, the control register on these older chips have two
 * event fields, one for each of the two counters.  It's thus nearly
 * impossible to have one counter going while keeping the other one
 * stopped.  Therefore it is possible to get overflow interrupts for
 * counters not currently "in use" and that condition must be checked
 * in the overflow interrupt handler.
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 *
 * So we use a hack, in that we program inactive counters with the
 * "sw_count0" and "sw_count1" events.  These count how many times
 * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
 * unusual way to encode a NOP and therefore will not trigger in
 * normal code.
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 *
 * Starting with SPARC-T4 we have one control register per counter.
 * And the counters are stored in individual registers.  The registers
 * for the counters are 64-bit but only a 32-bit counter is
 * implemented.  The event selections on SPARC-T4 lack any
 * restrictions, therefore we can elide all of the complicated
 * conflict resolution code we have for SPARC-T3 and earlier chips.
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 */

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#define MAX_HWEVENTS			4
#define MAX_PCRS			4
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#define MAX_PERIOD			((1UL << 32) - 1)

#define PIC_UPPER_INDEX			0
#define PIC_LOWER_INDEX			1
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#define PIC_NO_INDEX			-1
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struct cpu_hw_events {
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	/* Number of events currently scheduled onto this cpu.
	 * This tells how many entries in the arrays below
	 * are valid.
	 */
	int			n_events;

	/* Number of new events added since the last hw_perf_disable().
	 * This works because the perf event layer always adds new
	 * events inside of a perf_{disable,enable}() sequence.
	 */
	int			n_added;

	/* Array of events current scheduled on this cpu.  */
	struct perf_event	*event[MAX_HWEVENTS];

	/* Array of encoded longs, specifying the %pcr register
	 * encoding and the mask of PIC counters this even can
	 * be scheduled on.  See perf_event_encode() et al.
	 */
	unsigned long		events[MAX_HWEVENTS];

	/* The current counter index assigned to an event.  When the
	 * event hasn't been programmed into the cpu yet, this will
	 * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
	 * we ought to schedule the event.
	 */
	int			current_idx[MAX_HWEVENTS];

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	/* Software copy of %pcr register(s) on this cpu.  */
	u64			pcr[MAX_HWEVENTS];
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	/* Enabled/disable state.  */
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	int			enabled;
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	unsigned int		txn_flags;
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};
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static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
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/* An event map describes the characteristics of a performance
 * counter event.  In particular it gives the encoding as well as
 * a mask telling which counters the event can be measured on.
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 *
 * The mask is unused on SPARC-T4 and later.
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 */
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struct perf_event_map {
	u16	encoding;
	u8	pic_mask;
#define PIC_NONE	0x00
#define PIC_UPPER	0x01
#define PIC_LOWER	0x02
};

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/* Encode a perf_event_map entry into a long.  */
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static unsigned long perf_event_encode(const struct perf_event_map *pmap)
{
	return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
}

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static u8 perf_event_get_msk(unsigned long val)
{
	return val & 0xff;
}

static u64 perf_event_get_enc(unsigned long val)
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{
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	return val >> 16;
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}

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#define C(x) PERF_COUNT_HW_CACHE_##x

#define CACHE_OP_UNSUPPORTED	0xfffe
#define CACHE_OP_NONSENSE	0xffff

typedef struct perf_event_map cache_map_t
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];

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struct sparc_pmu {
	const struct perf_event_map	*(*event_map)(int);
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	const cache_map_t		*cache_map;
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	int				max_events;
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	u32				(*read_pmc)(int);
	void				(*write_pmc)(int, u64);
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	int				upper_shift;
	int				lower_shift;
	int				event_mask;
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	int				user_bit;
	int				priv_bit;
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	int				hv_bit;
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	int				irq_bit;
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	int				upper_nop;
	int				lower_nop;
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	unsigned int			flags;
#define SPARC_PMU_ALL_EXCLUDES_SAME	0x00000001
#define SPARC_PMU_HAS_CONFLICTS		0x00000002
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	int				max_hw_events;
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	int				num_pcrs;
	int				num_pic_regs;
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};

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static u32 sparc_default_read_pmc(int idx)
{
	u64 val;

	val = pcr_ops->read_pic(0);
	if (idx == PIC_UPPER_INDEX)
		val >>= 32;

	return val & 0xffffffff;
}

static void sparc_default_write_pmc(int idx, u64 val)
{
	u64 shift, mask, pic;

	shift = 0;
	if (idx == PIC_UPPER_INDEX)
		shift = 32;

	mask = ((u64) 0xffffffff) << shift;
	val <<= shift;

	pic = pcr_ops->read_pic(0);
	pic &= ~mask;
	pic |= val;
	pcr_ops->write_pic(0, pic);
}

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static const struct perf_event_map ultra3_perfmon_event_map[] = {
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	[PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
	[PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
};

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static const struct perf_event_map *ultra3_event_map(int event_id)
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{
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	return &ultra3_perfmon_event_map[event_id];
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}

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static const cache_map_t ultra3_cache_map = {
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[C(L1D)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
		[C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(L1I)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
		[ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(LL)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
		[C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(DTLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(ITLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(BPU)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
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[C(NODE)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
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};

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static const struct sparc_pmu ultra3_pmu = {
	.event_map	= ultra3_event_map,
	.cache_map	= &ultra3_cache_map,
	.max_events	= ARRAY_SIZE(ultra3_perfmon_event_map),
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	.read_pmc	= sparc_default_read_pmc,
	.write_pmc	= sparc_default_write_pmc,
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	.upper_shift	= 11,
	.lower_shift	= 4,
	.event_mask	= 0x3f,
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	.user_bit	= PCR_UTRACE,
	.priv_bit	= PCR_STRACE,
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	.upper_nop	= 0x1c,
	.lower_nop	= 0x14,
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	.flags		= (SPARC_PMU_ALL_EXCLUDES_SAME |
			   SPARC_PMU_HAS_CONFLICTS),
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	.max_hw_events	= 2,
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	.num_pcrs	= 1,
	.num_pic_regs	= 1,
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};

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/* Niagara1 is very limited.  The upper PIC is hard-locked to count
 * only instructions, so it is free running which creates all kinds of
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 * problems.  Some hardware designs make one wonder if the creator
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 * even looked at how this stuff gets used by software.
 */
static const struct perf_event_map niagara1_perfmon_event_map[] = {
	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
	[PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
};

static const struct perf_event_map *niagara1_event_map(int event_id)
{
	return &niagara1_perfmon_event_map[event_id];
}

static const cache_map_t niagara1_cache_map = {
[C(L1D)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(L1I)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
		[C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
		[ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(LL)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(DTLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(ITLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(BPU)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
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[C(NODE)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
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};

static const struct sparc_pmu niagara1_pmu = {
	.event_map	= niagara1_event_map,
	.cache_map	= &niagara1_cache_map,
	.max_events	= ARRAY_SIZE(niagara1_perfmon_event_map),
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	.read_pmc	= sparc_default_read_pmc,
	.write_pmc	= sparc_default_write_pmc,
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	.upper_shift	= 0,
	.lower_shift	= 4,
	.event_mask	= 0x7,
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	.user_bit	= PCR_UTRACE,
	.priv_bit	= PCR_STRACE,
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	.upper_nop	= 0x0,
	.lower_nop	= 0x0,
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	.flags		= (SPARC_PMU_ALL_EXCLUDES_SAME |
			   SPARC_PMU_HAS_CONFLICTS),
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	.max_hw_events	= 2,
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	.num_pcrs	= 1,
	.num_pic_regs	= 1,
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};

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static const struct perf_event_map niagara2_perfmon_event_map[] = {
	[PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
};

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static const struct perf_event_map *niagara2_event_map(int event_id)
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{
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	return &niagara2_perfmon_event_map[event_id];
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}

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static const cache_map_t niagara2_cache_map = {
[C(L1D)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(L1I)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
		[ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(LL)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
		[C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(DTLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(ITLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(BPU)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
569 570 571 572 573 574 575 576 577 578 579 580 581 582
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(NODE)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
583 584 585 586 587 588 589 590 591
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
};

592 593
static const struct sparc_pmu niagara2_pmu = {
	.event_map	= niagara2_event_map,
594
	.cache_map	= &niagara2_cache_map,
595
	.max_events	= ARRAY_SIZE(niagara2_perfmon_event_map),
596 597
	.read_pmc	= sparc_default_read_pmc,
	.write_pmc	= sparc_default_write_pmc,
598 599 600
	.upper_shift	= 19,
	.lower_shift	= 6,
	.event_mask	= 0xfff,
601 602 603
	.user_bit	= PCR_UTRACE,
	.priv_bit	= PCR_STRACE,
	.hv_bit		= PCR_N2_HTRACE,
604
	.irq_bit	= 0x30,
605 606
	.upper_nop	= 0x220,
	.lower_nop	= 0x220,
607 608
	.flags		= (SPARC_PMU_ALL_EXCLUDES_SAME |
			   SPARC_PMU_HAS_CONFLICTS),
609
	.max_hw_events	= 2,
610 611
	.num_pcrs	= 1,
	.num_pic_regs	= 1,
612 613
};

614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740
static const struct perf_event_map niagara4_perfmon_event_map[] = {
	[PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
	[PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
	[PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
	[PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
	[PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
};

static const struct perf_event_map *niagara4_event_map(int event_id)
{
	return &niagara4_perfmon_event_map[event_id];
}

static const cache_map_t niagara4_cache_map = {
[C(L1D)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
		[C(RESULT_MISS)] = { (16 << 6) | 0x07 },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
		[C(RESULT_MISS)] = { (16 << 6) | 0x07 },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(L1I)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
		[C(RESULT_MISS)] = { (11 << 6) | 0x03 },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
		[ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(LL)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[C(OP_WRITE)] = {
		[C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[C(OP_PREFETCH)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(DTLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { (17 << 6) | 0x3f },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(ITLB)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { (6 << 6) | 0x3f },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(BPU)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
[C(NODE)] = {
	[C(OP_READ)] = {
		[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
		[C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
		[ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
	},
},
};

static u32 sparc_vt_read_pmc(int idx)
{
	u64 val = pcr_ops->read_pic(idx);

	return val & 0xffffffff;
}

static void sparc_vt_write_pmc(int idx, u64 val)
{
	u64 pcr;

	pcr = pcr_ops->read_pcr(idx);
741 742
	/* ensure ov and ntc are reset */
	pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778

	pcr_ops->write_pic(idx, val & 0xffffffff);

	pcr_ops->write_pcr(idx, pcr);
}

static const struct sparc_pmu niagara4_pmu = {
	.event_map	= niagara4_event_map,
	.cache_map	= &niagara4_cache_map,
	.max_events	= ARRAY_SIZE(niagara4_perfmon_event_map),
	.read_pmc	= sparc_vt_read_pmc,
	.write_pmc	= sparc_vt_write_pmc,
	.upper_shift	= 5,
	.lower_shift	= 5,
	.event_mask	= 0x7ff,
	.user_bit	= PCR_N4_UTRACE,
	.priv_bit	= PCR_N4_STRACE,

	/* We explicitly don't support hypervisor tracing.  The T4
	 * generates the overflow event for precise events via a trap
	 * which will not be generated (ie. it's completely lost) if
	 * we happen to be in the hypervisor when the event triggers.
	 * Essentially, the overflow event reporting is completely
	 * unusable when you have hypervisor mode tracing enabled.
	 */
	.hv_bit		= 0,

	.irq_bit	= PCR_N4_TOE,
	.upper_nop	= 0,
	.lower_nop	= 0,
	.flags		= 0,
	.max_hw_events	= 4,
	.num_pcrs	= 4,
	.num_pic_regs	= 4,
};

779 780 781 782 783
static const struct sparc_pmu sparc_m7_pmu = {
	.event_map	= niagara4_event_map,
	.cache_map	= &niagara4_cache_map,
	.max_events	= ARRAY_SIZE(niagara4_perfmon_event_map),
	.read_pmc	= sparc_vt_read_pmc,
784
	.write_pmc	= sparc_vt_write_pmc,
785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801
	.upper_shift	= 5,
	.lower_shift	= 5,
	.event_mask	= 0x7ff,
	.user_bit	= PCR_N4_UTRACE,
	.priv_bit	= PCR_N4_STRACE,

	/* We explicitly don't support hypervisor tracing. */
	.hv_bit		= 0,

	.irq_bit	= PCR_N4_TOE,
	.upper_nop	= 0,
	.lower_nop	= 0,
	.flags		= 0,
	.max_hw_events	= 4,
	.num_pcrs	= 4,
	.num_pic_regs	= 4,
};
802 803
static const struct sparc_pmu *sparc_pmu __read_mostly;

804
static u64 event_encoding(u64 event_id, int idx)
805 806
{
	if (idx == PIC_UPPER_INDEX)
807
		event_id <<= sparc_pmu->upper_shift;
808
	else
809 810
		event_id <<= sparc_pmu->lower_shift;
	return event_id;
811 812 813 814 815 816 817 818 819 820
}

static u64 mask_for_index(int idx)
{
	return event_encoding(sparc_pmu->event_mask, idx);
}

static u64 nop_for_index(int idx)
{
	return event_encoding(idx == PIC_UPPER_INDEX ?
821 822
			      sparc_pmu->upper_nop :
			      sparc_pmu->lower_nop, idx);
823 824
}

825
static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
826
{
827
	u64 enc, val, mask = mask_for_index(idx);
828
	int pcr_index = 0;
829

830 831 832
	if (sparc_pmu->num_pcrs > 1)
		pcr_index = idx;

833 834
	enc = perf_event_get_enc(cpuc->events[idx]);

835
	val = cpuc->pcr[pcr_index];
836
	val &= ~mask;
837
	val |= event_encoding(enc, idx);
838
	cpuc->pcr[pcr_index] = val;
839

840
	pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
841 842
}

843
static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
844 845 846
{
	u64 mask = mask_for_index(idx);
	u64 nop = nop_for_index(idx);
847
	int pcr_index = 0;
848
	u64 val;
849

850 851 852 853
	if (sparc_pmu->num_pcrs > 1)
		pcr_index = idx;

	val = cpuc->pcr[pcr_index];
854 855
	val &= ~mask;
	val |= nop;
856
	cpuc->pcr[pcr_index] = val;
857

858
	pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
859 860
}

861 862 863 864 865 866 867 868
static u64 sparc_perf_event_update(struct perf_event *event,
				   struct hw_perf_event *hwc, int idx)
{
	int shift = 64 - 32;
	u64 prev_raw_count, new_raw_count;
	s64 delta;

again:
869
	prev_raw_count = local64_read(&hwc->prev_count);
870
	new_raw_count = sparc_pmu->read_pmc(idx);
871

872
	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
873 874 875 876 877 878
			     new_raw_count) != prev_raw_count)
		goto again;

	delta = (new_raw_count << shift) - (prev_raw_count << shift);
	delta >>= shift;

879 880
	local64_add(delta, &event->count);
	local64_sub(delta, &hwc->period_left);
881 882 883 884

	return new_raw_count;
}

885
static int sparc_perf_event_set_period(struct perf_event *event,
886
				       struct hw_perf_event *hwc, int idx)
887
{
888
	s64 left = local64_read(&hwc->period_left);
889 890 891 892 893
	s64 period = hwc->sample_period;
	int ret = 0;

	if (unlikely(left <= -period)) {
		left = period;
894
		local64_set(&hwc->period_left, left);
895 896 897 898 899 900
		hwc->last_period = period;
		ret = 1;
	}

	if (unlikely(left <= 0)) {
		left += period;
901
		local64_set(&hwc->period_left, left);
902 903 904 905 906 907
		hwc->last_period = period;
		ret = 1;
	}
	if (left > MAX_PERIOD)
		left = MAX_PERIOD;

908
	local64_set(&hwc->prev_count, (u64)-left);
909

910
	sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff);
911

912
	perf_event_update_userpage(event);
913 914 915 916

	return ret;
}

917
static void read_in_all_counters(struct cpu_hw_events *cpuc)
918
{
919
	int i;
920

921 922
	for (i = 0; i < cpuc->n_events; i++) {
		struct perf_event *cp = cpuc->event[i];
923

924 925 926 927 928
		if (cpuc->current_idx[i] != PIC_NO_INDEX &&
		    cpuc->current_idx[i] != cp->hw.idx) {
			sparc_perf_event_update(cp, &cp->hw,
						cpuc->current_idx[i]);
			cpuc->current_idx[i] = PIC_NO_INDEX;
929 930
			if (cp->hw.state & PERF_HES_STOPPED)
				cp->hw.state |= PERF_HES_ARCH;
931 932
		}
	}
933 934 935 936 937 938 939 940 941 942 943 944 945 946
}

/* On this PMU all PICs are programmed using a single PCR.  Calculate
 * the combined control register value.
 *
 * For such chips we require that all of the events have the same
 * configuration, so just fetch the settings from the first entry.
 */
static void calculate_single_pcr(struct cpu_hw_events *cpuc)
{
	int i;

	if (!cpuc->n_added)
		goto out;
947

948 949 950 951 952 953 954 955 956 957 958 959 960 961
	/* Assign to counters all unassigned events.  */
	for (i = 0; i < cpuc->n_events; i++) {
		struct perf_event *cp = cpuc->event[i];
		struct hw_perf_event *hwc = &cp->hw;
		int idx = hwc->idx;
		u64 enc;

		if (cpuc->current_idx[i] != PIC_NO_INDEX)
			continue;

		sparc_perf_event_set_period(cp, hwc, idx);
		cpuc->current_idx[i] = idx;

		enc = perf_event_get_enc(cpuc->events[i]);
962
		cpuc->pcr[0] &= ~mask_for_index(idx);
963
		if (hwc->state & PERF_HES_ARCH) {
964
			cpuc->pcr[0] |= nop_for_index(idx);
965
		} else {
966
			cpuc->pcr[0] |= event_encoding(enc, idx);
967 968
			hwc->state = 0;
		}
969 970
	}
out:
971 972 973
	cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
}

974 975
static void sparc_pmu_start(struct perf_event *event, int flags);

976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
/* On this PMU each PIC has it's own PCR control register.  */
static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
{
	int i;

	if (!cpuc->n_added)
		goto out;

	for (i = 0; i < cpuc->n_events; i++) {
		struct perf_event *cp = cpuc->event[i];
		struct hw_perf_event *hwc = &cp->hw;
		int idx = hwc->idx;

		if (cpuc->current_idx[i] != PIC_NO_INDEX)
			continue;

		cpuc->current_idx[i] = idx;

994 995 996
		if (cp->hw.state & PERF_HES_ARCH)
			continue;

997
		sparc_pmu_start(cp, PERF_EF_RELOAD);
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
	}
out:
	for (i = 0; i < cpuc->n_events; i++) {
		struct perf_event *cp = cpuc->event[i];
		int idx = cp->hw.idx;

		cpuc->pcr[idx] |= cp->hw.config_base;
	}
}

/* If performance event entries have been added, move existing events
 * around (if necessary) and then assign new entries to counters.
 */
static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)
{
	if (cpuc->n_added)
		read_in_all_counters(cpuc);

	if (sparc_pmu->num_pcrs == 1) {
		calculate_single_pcr(cpuc);
	} else {
		calculate_multiple_pcrs(cpuc);
	}
1021 1022
}

1023
static void sparc_pmu_enable(struct pmu *pmu)
1024
{
1025
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1026
	int i;
1027

1028 1029
	if (cpuc->enabled)
		return;
1030

1031 1032
	cpuc->enabled = 1;
	barrier();
1033

1034 1035
	if (cpuc->n_events)
		update_pcrs_for_enable(cpuc);
1036

1037 1038
	for (i = 0; i < sparc_pmu->num_pcrs; i++)
		pcr_ops->write_pcr(i, cpuc->pcr[i]);
1039 1040
}

1041
static void sparc_pmu_disable(struct pmu *pmu)
1042
{
1043
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1044
	int i;
1045 1046 1047 1048 1049 1050 1051

	if (!cpuc->enabled)
		return;

	cpuc->enabled = 0;
	cpuc->n_added = 0;

1052 1053
	for (i = 0; i < sparc_pmu->num_pcrs; i++) {
		u64 val = cpuc->pcr[i];
1054

1055 1056 1057 1058 1059
		val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit |
			 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
		cpuc->pcr[i] = val;
		pcr_ops->write_pcr(i, cpuc->pcr[i]);
	}
1060 1061
}

1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
static int active_event_index(struct cpu_hw_events *cpuc,
			      struct perf_event *event)
{
	int i;

	for (i = 0; i < cpuc->n_events; i++) {
		if (cpuc->event[i] == event)
			break;
	}
	BUG_ON(i == cpuc->n_events);
	return cpuc->current_idx[i];
}

static void sparc_pmu_start(struct perf_event *event, int flags)
{
1077
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	int idx = active_event_index(cpuc, event);

	if (flags & PERF_EF_RELOAD) {
		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
		sparc_perf_event_set_period(event, &event->hw, idx);
	}

	event->hw.state = 0;

	sparc_pmu_enable_event(cpuc, &event->hw, idx);
1088 1089

	perf_event_update_userpage(event);
1090 1091 1092 1093
}

static void sparc_pmu_stop(struct perf_event *event, int flags)
{
1094
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
	int idx = active_event_index(cpuc, event);

	if (!(event->hw.state & PERF_HES_STOPPED)) {
		sparc_pmu_disable_event(cpuc, &event->hw, idx);
		event->hw.state |= PERF_HES_STOPPED;
	}

	if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
		sparc_perf_event_update(event, &event->hw, idx);
		event->hw.state |= PERF_HES_UPTODATE;
	}
}

static void sparc_pmu_del(struct perf_event *event, int _flags)
1109
{
1110
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1111 1112
	unsigned long flags;
	int i;
1113

1114 1115 1116 1117
	local_irq_save(flags);

	for (i = 0; i < cpuc->n_events; i++) {
		if (event == cpuc->event[i]) {
1118 1119 1120 1121
			/* Absorb the final count and turn off the
			 * event.
			 */
			sparc_pmu_stop(event, PERF_EF_UPDATE);
1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133

			/* Shift remaining entries down into
			 * the existing slot.
			 */
			while (++i < cpuc->n_events) {
				cpuc->event[i - 1] = cpuc->event[i];
				cpuc->events[i - 1] = cpuc->events[i];
				cpuc->current_idx[i - 1] =
					cpuc->current_idx[i];
			}

			perf_event_update_userpage(event);
1134

1135 1136 1137 1138
			cpuc->n_events--;
			break;
		}
	}
1139

1140 1141 1142
	local_irq_restore(flags);
}

1143
static void sparc_pmu_read(struct perf_event *event)
1144
{
1145
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1146
	int idx = active_event_index(cpuc, event);
1147
	struct hw_perf_event *hwc = &event->hw;
1148

1149
	sparc_perf_event_update(event, hwc, idx);
1150 1151
}

1152
static atomic_t active_events = ATOMIC_INIT(0);
1153 1154
static DEFINE_MUTEX(pmc_grab_mutex);

1155 1156
static void perf_stop_nmi_watchdog(void *unused)
{
1157
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1158
	int i;
1159 1160

	stop_nmi_watchdog(NULL);
1161 1162
	for (i = 0; i < sparc_pmu->num_pcrs; i++)
		cpuc->pcr[i] = pcr_ops->read_pcr(i);
1163 1164
}

1165
static void perf_event_grab_pmc(void)
1166
{
1167
	if (atomic_inc_not_zero(&active_events))
1168 1169 1170
		return;

	mutex_lock(&pmc_grab_mutex);
1171
	if (atomic_read(&active_events) == 0) {
1172
		if (atomic_read(&nmi_active) > 0) {
1173
			on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
1174 1175
			BUG_ON(atomic_read(&nmi_active) != 0);
		}
1176
		atomic_inc(&active_events);
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	}
	mutex_unlock(&pmc_grab_mutex);
}

1181
static void perf_event_release_pmc(void)
1182
{
1183
	if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
1184 1185 1186 1187 1188 1189
		if (atomic_read(&nmi_active) == 0)
			on_each_cpu(start_nmi_watchdog, NULL, 1);
		mutex_unlock(&pmc_grab_mutex);
	}
}

1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
static const struct perf_event_map *sparc_map_cache_event(u64 config)
{
	unsigned int cache_type, cache_op, cache_result;
	const struct perf_event_map *pmap;

	if (!sparc_pmu->cache_map)
		return ERR_PTR(-ENOENT);

	cache_type = (config >>  0) & 0xff;
	if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
		return ERR_PTR(-EINVAL);

	cache_op = (config >>  8) & 0xff;
	if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
		return ERR_PTR(-EINVAL);

	cache_result = (config >> 16) & 0xff;
	if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
		return ERR_PTR(-EINVAL);

	pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);

	if (pmap->encoding == CACHE_OP_UNSUPPORTED)
		return ERR_PTR(-ENOENT);

	if (pmap->encoding == CACHE_OP_NONSENSE)
		return ERR_PTR(-EINVAL);

	return pmap;
}

1221
static void hw_perf_event_destroy(struct perf_event *event)
1222
{
1223
	perf_event_release_pmc();
1224 1225
}

1226 1227 1228
/* Make sure all events can be scheduled into the hardware at
 * the same time.  This is simplified by the fact that we only
 * need to support 2 simultaneous HW events.
1229 1230 1231 1232 1233 1234
 *
 * As a side effect, the evts[]->hw.idx values will be assigned
 * on success.  These are pending indexes.  When the events are
 * actually programmed into the chip, these values will propagate
 * to the per-cpu cpuc->current_idx[] slots, see the code in
 * maybe_change_configuration() for details.
1235
 */
1236 1237
static int sparc_check_constraints(struct perf_event **evts,
				   unsigned long *events, int n_ev)
1238
{
1239 1240 1241 1242 1243 1244 1245 1246 1247
	u8 msk0 = 0, msk1 = 0;
	int idx0 = 0;

	/* This case is possible when we are invoked from
	 * hw_perf_group_sched_in().
	 */
	if (!n_ev)
		return 0;

1248
	if (n_ev > sparc_pmu->max_hw_events)
1249 1250
		return -1;

1251 1252 1253 1254 1255 1256 1257 1258
	if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {
		int i;

		for (i = 0; i < n_ev; i++)
			evts[i]->hw.idx = i;
		return 0;
	}

1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
	msk0 = perf_event_get_msk(events[0]);
	if (n_ev == 1) {
		if (msk0 & PIC_LOWER)
			idx0 = 1;
		goto success;
	}
	BUG_ON(n_ev != 2);
	msk1 = perf_event_get_msk(events[1]);

	/* If both events can go on any counter, OK.  */
	if (msk0 == (PIC_UPPER | PIC_LOWER) &&
	    msk1 == (PIC_UPPER | PIC_LOWER))
		goto success;

	/* If one event is limited to a specific counter,
	 * and the other can go on both, OK.
	 */
	if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
	    msk1 == (PIC_UPPER | PIC_LOWER)) {
		if (msk0 & PIC_LOWER)
			idx0 = 1;
		goto success;
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	}

1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
	if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
	    msk0 == (PIC_UPPER | PIC_LOWER)) {
		if (msk1 & PIC_UPPER)
			idx0 = 1;
		goto success;
	}

	/* If the events are fixed to different counters, OK.  */
	if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
	    (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
		if (msk0 & PIC_LOWER)
			idx0 = 1;
		goto success;
	}

	/* Otherwise, there is a conflict.  */
1299
	return -1;
1300 1301 1302 1303 1304 1305

success:
	evts[0]->hw.idx = idx0;
	if (n_ev == 2)
		evts[1]->hw.idx = idx0 ^ 1;
	return 0;
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}

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static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
{
	int eu = 0, ek = 0, eh = 0;
	struct perf_event *event;
	int i, n, first;

1314 1315 1316
	if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))
		return 0;

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	n = n_prev + n_new;
	if (n <= 1)
		return 0;

	first = 1;
	for (i = 0; i < n; i++) {
		event = evts[i];
		if (first) {
			eu = event->attr.exclude_user;
			ek = event->attr.exclude_kernel;
			eh = event->attr.exclude_hv;
			first = 0;
		} else if (event->attr.exclude_user != eu ||
			   event->attr.exclude_kernel != ek ||
			   event->attr.exclude_hv != eh) {
			return -EAGAIN;
		}
	}

	return 0;
}

static int collect_events(struct perf_event *group, int max_count,
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			  struct perf_event *evts[], unsigned long *events,
			  int *current_idx)
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{
	struct perf_event *event;
	int n = 0;

	if (!is_software_event(group)) {
		if (n >= max_count)
			return -1;
		evts[n] = group;
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		events[n] = group->hw.event_base;
		current_idx[n++] = PIC_NO_INDEX;
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	}
	list_for_each_entry(event, &group->sibling_list, group_entry) {
		if (!is_software_event(event) &&
		    event->state != PERF_EVENT_STATE_OFF) {
			if (n >= max_count)
				return -1;
			evts[n] = event;
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			events[n] = event->hw.event_base;
			current_idx[n++] = PIC_NO_INDEX;
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		}
	}
	return n;
}

1366
static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1367
{
1368
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1369 1370 1371 1372 1373 1374
	int n0, ret = -EAGAIN;
	unsigned long flags;

	local_irq_save(flags);

	n0 = cpuc->n_events;
1375
	if (n0 >= sparc_pmu->max_hw_events)
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		goto out;

	cpuc->event[n0] = event;
	cpuc->events[n0] = event->hw.event_base;
	cpuc->current_idx[n0] = PIC_NO_INDEX;

1382
	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1383
	if (!(ef_flags & PERF_EF_START))
1384
		event->hw.state |= PERF_HES_ARCH;
1385

1386 1387
	/*
	 * If group events scheduling transaction was started,
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1388
	 * skip the schedulability test here, it will be performed
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	 * at commit time(->commit_txn) as a whole
	 */
1391
	if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
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		goto nocheck;

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	if (check_excludes(cpuc->event, n0, 1))
		goto out;
	if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
		goto out;

1399
nocheck:
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	cpuc->n_events++;
	cpuc->n_added++;

	ret = 0;
out:
	local_irq_restore(flags);
	return ret;
}

1409
static int sparc_pmu_event_init(struct perf_event *event)
1410
{
1411
	struct perf_event_attr *attr = &event->attr;
1412
	struct perf_event *evts[MAX_HWEVENTS];
1413
	struct hw_perf_event *hwc = &event->hw;
1414
	unsigned long events[MAX_HWEVENTS];
1415
	int current_idx_dmy[MAX_HWEVENTS];
1416
	const struct perf_event_map *pmap;
1417
	int n;
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	if (atomic_read(&nmi_active) < 0)
		return -ENODEV;

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	/* does not support taken branch sampling */
	if (has_branch_stack(event))
		return -EOPNOTSUPP;

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	switch (attr->type) {
	case PERF_TYPE_HARDWARE:
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		if (attr->config >= sparc_pmu->max_events)
			return -EINVAL;
		pmap = sparc_pmu->event_map(attr->config);
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		break;

	case PERF_TYPE_HW_CACHE:
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		pmap = sparc_map_cache_event(attr->config);
		if (IS_ERR(pmap))
			return PTR_ERR(pmap);
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		break;

	case PERF_TYPE_RAW:
1440 1441
		pmap = NULL;
		break;
1442

1443 1444 1445 1446 1447
	default:
		return -ENOENT;

	}

1448 1449 1450
	if (pmap) {
		hwc->event_base = perf_event_encode(pmap);
	} else {
1451 1452
		/*
		 * User gives us "(encoding << 16) | pic_mask" for
1453 1454 1455 1456 1457
		 * PERF_TYPE_RAW events.
		 */
		hwc->event_base = attr->config;
	}

1458
	/* We save the enable bits in the config_base.  */
1459
	hwc->config_base = sparc_pmu->irq_bit;
1460
	if (!attr->exclude_user)
1461
		hwc->config_base |= sparc_pmu->user_bit;
1462
	if (!attr->exclude_kernel)
1463
		hwc->config_base |= sparc_pmu->priv_bit;
1464 1465
	if (!attr->exclude_hv)
		hwc->config_base |= sparc_pmu->hv_bit;
1466

1467 1468 1469
	n = 0;
	if (event->group_leader != event) {
		n = collect_events(event->group_leader,
1470
				   sparc_pmu->max_hw_events - 1,
1471
				   evts, events, current_idx_dmy);
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		if (n < 0)
			return -EINVAL;
	}
1475
	events[n] = hwc->event_base;
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	evts[n] = event;

	if (check_excludes(evts, n, 1))
		return -EINVAL;

1481
	if (sparc_check_constraints(evts, events, n + 1))
1482 1483
		return -EINVAL;

1484 1485
	hwc->idx = PIC_NO_INDEX;

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	/* Try to do all error checking before this point, as unwinding
	 * state after grabbing the PMC is difficult.
	 */
	perf_event_grab_pmc();
	event->destroy = hw_perf_event_destroy;

1492 1493 1494
	if (!hwc->sample_period) {
		hwc->sample_period = MAX_PERIOD;
		hwc->last_period = hwc->sample_period;
1495
		local64_set(&hwc->period_left, hwc->sample_period);
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	}

	return 0;
}

1501 1502 1503 1504 1505
/*
 * Start group events scheduling transaction
 * Set the flag to make pmu::enable() not perform the
 * schedulability test, it will be performed at commit time
 */
1506
static void sparc_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1507
{
1508
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1509

1510 1511 1512 1513 1514 1515
	WARN_ON_ONCE(cpuhw->txn_flags);		/* txn already in flight */

	cpuhw->txn_flags = txn_flags;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;

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	perf_pmu_disable(pmu);
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}

/*
 * Stop group events scheduling transaction
 * Clear the flag and pmu::enable() will perform the
 * schedulability test.
 */
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1524
static void sparc_pmu_cancel_txn(struct pmu *pmu)
1525
{
1526
	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
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	unsigned int txn_flags;

	WARN_ON_ONCE(!cpuhw->txn_flags);	/* no txn in flight */

	txn_flags = cpuhw->txn_flags;
	cpuhw->txn_flags = 0;
	if (txn_flags & ~PERF_PMU_TXN_ADD)
		return;
1535

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	perf_pmu_enable(pmu);
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}

/*
 * Commit group events scheduling transaction
 * Perform the group schedulability test as a whole
 * Return 0 if success
 */
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static int sparc_pmu_commit_txn(struct pmu *pmu)
1545
{
1546
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1547 1548 1549 1550 1551
	int n;

	if (!sparc_pmu)
		return -EINVAL;

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	WARN_ON_ONCE(!cpuc->txn_flags);	/* no txn in flight */

	if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
		cpuc->txn_flags = 0;
		return 0;
	}

1559 1560 1561 1562 1563 1564
	n = cpuc->n_events;
	if (check_excludes(cpuc->event, 0, n))
		return -EINVAL;
	if (sparc_check_constraints(cpuc->event, cpuc->events, n))
		return -EAGAIN;

1565
	cpuc->txn_flags = 0;
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	perf_pmu_enable(pmu);
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	return 0;
}

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static struct pmu pmu = {
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	.pmu_enable	= sparc_pmu_enable,
	.pmu_disable	= sparc_pmu_disable,
1573
	.event_init	= sparc_pmu_event_init,
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	.add		= sparc_pmu_add,
	.del		= sparc_pmu_del,
	.start		= sparc_pmu_start,
	.stop		= sparc_pmu_stop,
1578
	.read		= sparc_pmu_read,
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	.start_txn	= sparc_pmu_start_txn,
	.cancel_txn	= sparc_pmu_cancel_txn,
	.commit_txn	= sparc_pmu_commit_txn,
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};

1584
void perf_event_print_debug(void)
1585 1586
{
	unsigned long flags;
1587
	int cpu, i;
1588 1589 1590 1591 1592 1593 1594 1595 1596

	if (!sparc_pmu)
		return;

	local_irq_save(flags);

	cpu = smp_processor_id();

	pr_info("\n");
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	for (i = 0; i < sparc_pmu->num_pcrs; i++)
		pr_info("CPU#%d: PCR%d[%016llx]\n",
			cpu, i, pcr_ops->read_pcr(i));
	for (i = 0; i < sparc_pmu->num_pic_regs; i++)
		pr_info("CPU#%d: PIC%d[%016llx]\n",
			cpu, i, pcr_ops->read_pic(i));
1603 1604 1605 1606

	local_irq_restore(flags);
}

1607
static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1608
					    unsigned long cmd, void *__args)
1609 1610 1611
{
	struct die_args *args = __args;
	struct perf_sample_data data;
1612
	struct cpu_hw_events *cpuc;
1613
	struct pt_regs *regs;
1614
	int i;
1615

1616
	if (!atomic_read(&active_events))
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
		return NOTIFY_DONE;

	switch (cmd) {
	case DIE_NMI:
		break;

	default:
		return NOTIFY_DONE;
	}

	regs = args->regs;

1629
	cpuc = this_cpu_ptr(&cpu_hw_events);
1630 1631 1632 1633 1634 1635 1636 1637

	/* If the PMU has the TOE IRQ enable bits, we need to do a
	 * dummy write to the %pcr to clear the overflow bits and thus
	 * the interrupt.
	 *
	 * Do this before we peek at the counters to determine
	 * overflow so we don't lose any events.
	 */
1638 1639 1640
	if (sparc_pmu->irq_bit &&
	    sparc_pmu->num_pcrs == 1)
		pcr_ops->write_pcr(0, cpuc->pcr[0]);
1641

1642 1643 1644
	for (i = 0; i < cpuc->n_events; i++) {
		struct perf_event *event = cpuc->event[i];
		int idx = cpuc->current_idx[i];
1645
		struct hw_perf_event *hwc;
1646 1647
		u64 val;

1648 1649 1650 1651
		if (sparc_pmu->irq_bit &&
		    sparc_pmu->num_pcrs > 1)
			pcr_ops->write_pcr(idx, cpuc->pcr[idx]);

1652 1653
		hwc = &event->hw;
		val = sparc_perf_event_update(event, hwc, idx);
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		if (val & (1ULL << 31))
			continue;

1657
		perf_sample_data_init(&data, 0, hwc->last_period);
1658
		if (!sparc_perf_event_set_period(event, hwc, idx))
1659 1660
			continue;

1661
		if (perf_event_overflow(event, &data, regs))
1662
			sparc_pmu_stop(event, 0);
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	}

	return NOTIFY_STOP;
}

1668 1669
static __read_mostly struct notifier_block perf_event_nmi_notifier = {
	.notifier_call		= perf_event_nmi_handler,
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};

static bool __init supported_pmu(void)
{
1674 1675 1676 1677 1678
	if (!strcmp(sparc_pmu_type, "ultra3") ||
	    !strcmp(sparc_pmu_type, "ultra3+") ||
	    !strcmp(sparc_pmu_type, "ultra3i") ||
	    !strcmp(sparc_pmu_type, "ultra4+")) {
		sparc_pmu = &ultra3_pmu;
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		return true;
	}
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	if (!strcmp(sparc_pmu_type, "niagara")) {
		sparc_pmu = &niagara1_pmu;
		return true;
	}
1685 1686
	if (!strcmp(sparc_pmu_type, "niagara2") ||
	    !strcmp(sparc_pmu_type, "niagara3")) {
1687 1688 1689
		sparc_pmu = &niagara2_pmu;
		return true;
	}
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	if (!strcmp(sparc_pmu_type, "niagara4") ||
	    !strcmp(sparc_pmu_type, "niagara5")) {
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		sparc_pmu = &niagara4_pmu;
		return true;
	}
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	if (!strcmp(sparc_pmu_type, "sparc-m7")) {
		sparc_pmu = &sparc_m7_pmu;
		return true;
	}
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	return false;
}

1702
static int __init init_hw_perf_events(void)
1703
{
1704 1705
	int err;

1706
	pr_info("Performance events: ");
1707

1708 1709
	err = pcr_arch_init();
	if (err || !supported_pmu()) {
1710
		pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1711
		return 0;
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	}

	pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);

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	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1717
	register_die_notifier(&perf_event_nmi_notifier);
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	return 0;
1720
}
1721
pure_initcall(init_hw_perf_events);
1722

1723 1724
void perf_callchain_kernel(struct perf_callchain_entry *entry,
			   struct pt_regs *regs)
1725 1726
{
	unsigned long ksp, fp;
1727 1728 1729
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
	int graph = 0;
#endif
1730

1731 1732
	stack_trace_flush();

1733
	perf_callchain_store(entry, regs->tpc);
1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756

	ksp = regs->u_regs[UREG_I6];
	fp = ksp + STACK_BIAS;
	do {
		struct sparc_stackf *sf;
		struct pt_regs *regs;
		unsigned long pc;

		if (!kstack_valid(current_thread_info(), fp))
			break;

		sf = (struct sparc_stackf *) fp;
		regs = (struct pt_regs *) (sf + 1);

		if (kstack_is_trap_frame(current_thread_info(), regs)) {
			if (user_mode(regs))
				break;
			pc = regs->tpc;
			fp = regs->u_regs[UREG_I6] + STACK_BIAS;
		} else {
			pc = sf->callers_pc;
			fp = (unsigned long)sf->fp + STACK_BIAS;
		}
1757
		perf_callchain_store(entry, pc);
1758 1759 1760 1761 1762
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
		if ((pc + 8UL) == (unsigned long) &return_to_handler) {
			int index = current->curr_ret_stack;
			if (current->ret_stack && index >= graph) {
				pc = current->ret_stack[index - graph].ret;
1763
				perf_callchain_store(entry, pc);
1764 1765 1766 1767
				graph++;
			}
		}
#endif
1768 1769 1770
	} while (entry->nr < PERF_MAX_STACK_DEPTH);
}

1771 1772 1773 1774 1775 1776 1777 1778 1779 1780
static inline int
valid_user_frame(const void __user *fp, unsigned long size)
{
	/* addresses should be at least 4-byte aligned */
	if (((unsigned long) fp) & 3)
		return 0;

	return (__range_not_ok(fp, size, TASK_SIZE) == 0);
}

1781 1782
static void perf_callchain_user_64(struct perf_callchain_entry *entry,
				   struct pt_regs *regs)
1783 1784 1785
{
	unsigned long ufp;

1786
	ufp = regs->u_regs[UREG_FP] + STACK_BIAS;
1787
	do {
1788 1789
		struct sparc_stackf __user *usf;
		struct sparc_stackf sf;
1790 1791
		unsigned long pc;

1792
		usf = (struct sparc_stackf __user *)ufp;
1793 1794 1795
		if (!valid_user_frame(usf, sizeof(sf)))
			break;

1796 1797 1798 1799 1800
		if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
			break;

		pc = sf.callers_pc;
		ufp = (unsigned long)sf.fp + STACK_BIAS;
1801
		perf_callchain_store(entry, pc);
1802 1803 1804
	} while (entry->nr < PERF_MAX_STACK_DEPTH);
}

1805 1806
static void perf_callchain_user_32(struct perf_callchain_entry *entry,
				   struct pt_regs *regs)
1807 1808 1809
{
	unsigned long ufp;

1810
	ufp = regs->u_regs[UREG_FP] & 0xffffffffUL;
1811 1812 1813
	do {
		unsigned long pc;

1814
		if (thread32_stack_is_64bit(ufp)) {
1815 1816
			struct sparc_stackf __user *usf;
			struct sparc_stackf sf;
1817

1818
			ufp += STACK_BIAS;
1819
			usf = (struct sparc_stackf __user *)ufp;
1820 1821 1822 1823 1824
			if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
				break;
			pc = sf.callers_pc & 0xffffffff;
			ufp = ((unsigned long) sf.fp) & 0xffffffff;
		} else {
1825 1826 1827
			struct sparc_stackf32 __user *usf;
			struct sparc_stackf32 sf;
			usf = (struct sparc_stackf32 __user *)ufp;
1828 1829 1830 1831 1832
			if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
				break;
			pc = sf.callers_pc;
			ufp = (unsigned long)sf.fp;
		}
1833
		perf_callchain_store(entry, pc);
1834 1835 1836
	} while (entry->nr < PERF_MAX_STACK_DEPTH);
}

1837 1838
void
perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1839
{
1840 1841
	u64 saved_fault_address = current_thread_info()->fault_address;
	u8 saved_fault_code = get_thread_fault_code();
1842 1843
	mm_segment_t old_fs;

1844 1845 1846 1847 1848
	perf_callchain_store(entry, regs->tpc);

	if (!current->mm)
		return;

1849 1850 1851
	old_fs = get_fs();
	set_fs(USER_DS);

1852
	flushw_user();
1853 1854 1855

	pagefault_disable();

1856 1857 1858 1859
	if (test_thread_flag(TIF_32BIT))
		perf_callchain_user_32(entry, regs);
	else
		perf_callchain_user_64(entry, regs);
1860 1861

	pagefault_enable();
1862 1863

	set_fs(old_fs);
1864 1865
	set_thread_fault_code(saved_fault_code);
	current_thread_info()->fault_address = saved_fault_address;
1866
}