intel_uncore.c 63.5 KB
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/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "i915_drv.h"
#include "intel_drv.h"
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#include "i915_vgpu.h"
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#include <asm/iosf_mbi.h>
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#include <linux/pm_runtime.h>

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#define FORCEWAKE_ACK_TIMEOUT_MS 50
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#define GT_FIFO_TIMEOUT_MS	 10
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#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
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static const char * const forcewake_domain_names[] = {
	"render",
	"blitter",
	"media",
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	"vdbox0",
	"vdbox1",
	"vdbox2",
	"vdbox3",
	"vebox0",
	"vebox1",
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};

const char *
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intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
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{
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	BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
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	if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
		return forcewake_domain_names[id];

	WARN_ON(id);

	return "unknown";
}

static inline void
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fw_domain_reset(struct drm_i915_private *i915,
		const struct intel_uncore_forcewake_domain *d)
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{
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	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
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}

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static inline void
fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
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{
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	d->wake_count++;
	hrtimer_start_range_ns(&d->timer,
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			       NSEC_PER_MSEC,
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			       NSEC_PER_MSEC,
			       HRTIMER_MODE_REL);
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}

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static inline int
__wait_for_ack(const struct drm_i915_private *i915,
	       const struct intel_uncore_forcewake_domain *d,
	       const u32 ack,
	       const u32 value)
{
	return wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) & ack) == value,
			       FORCEWAKE_ACK_TIMEOUT_MS);
}

static inline int
wait_ack_clear(const struct drm_i915_private *i915,
	       const struct intel_uncore_forcewake_domain *d,
	       const u32 ack)
{
	return __wait_for_ack(i915, d, ack, 0);
}

static inline int
wait_ack_set(const struct drm_i915_private *i915,
	     const struct intel_uncore_forcewake_domain *d,
	     const u32 ack)
{
	return __wait_for_ack(i915, d, ack, ack);
}

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static inline void
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fw_domain_wait_ack_clear(const struct drm_i915_private *i915,
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			 const struct intel_uncore_forcewake_domain *d)
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{
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	if (wait_ack_clear(i915, d, FORCEWAKE_KERNEL))
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		DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
			  intel_uncore_forcewake_domain_to_str(d->id));
}
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enum ack_type {
	ACK_CLEAR = 0,
	ACK_SET
};

static int
fw_domain_wait_ack_with_fallback(const struct drm_i915_private *i915,
				 const struct intel_uncore_forcewake_domain *d,
				 const enum ack_type type)
{
	const u32 ack_bit = FORCEWAKE_KERNEL;
	const u32 value = type == ACK_SET ? ack_bit : 0;
	unsigned int pass;
	bool ack_detected;

	/*
	 * There is a possibility of driver's wake request colliding
	 * with hardware's own wake requests and that can cause
	 * hardware to not deliver the driver's ack message.
	 *
	 * Use a fallback bit toggle to kick the gpu state machine
	 * in the hope that the original ack will be delivered along with
	 * the fallback ack.
	 *
	 * This workaround is described in HSDES #1604254524
	 */

	pass = 1;
	do {
		wait_ack_clear(i915, d, FORCEWAKE_KERNEL_FALLBACK);

		__raw_i915_write32(i915, d->reg_set,
				   _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
		/* Give gt some time to relax before the polling frenzy */
		udelay(10 * pass);
		wait_ack_set(i915, d, FORCEWAKE_KERNEL_FALLBACK);

		ack_detected = (__raw_i915_read32(i915, d->reg_ack) & ack_bit) == value;

		__raw_i915_write32(i915, d->reg_set,
				   _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
	} while (!ack_detected && pass++ < 10);

	DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
			 intel_uncore_forcewake_domain_to_str(d->id),
			 type == ACK_SET ? "set" : "clear",
			 __raw_i915_read32(i915, d->reg_ack),
			 pass);

	return ack_detected ? 0 : -ETIMEDOUT;
}

static inline void
fw_domain_wait_ack_clear_fallback(const struct drm_i915_private *i915,
				  const struct intel_uncore_forcewake_domain *d)
{
	if (likely(!wait_ack_clear(i915, d, FORCEWAKE_KERNEL)))
		return;

	if (fw_domain_wait_ack_with_fallback(i915, d, ACK_CLEAR))
		fw_domain_wait_ack_clear(i915, d);
}

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static inline void
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fw_domain_get(struct drm_i915_private *i915,
	      const struct intel_uncore_forcewake_domain *d)
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{
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	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_set);
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}
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static inline void
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fw_domain_wait_ack_set(const struct drm_i915_private *i915,
		       const struct intel_uncore_forcewake_domain *d)
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{
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	if (wait_ack_set(i915, d, FORCEWAKE_KERNEL))
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		DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
			  intel_uncore_forcewake_domain_to_str(d->id));
}
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static inline void
fw_domain_wait_ack_set_fallback(const struct drm_i915_private *i915,
				const struct intel_uncore_forcewake_domain *d)
{
	if (likely(!wait_ack_set(i915, d, FORCEWAKE_KERNEL)))
		return;

	if (fw_domain_wait_ack_with_fallback(i915, d, ACK_SET))
		fw_domain_wait_ack_set(i915, d);
}

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static inline void
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fw_domain_put(const struct drm_i915_private *i915,
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	      const struct intel_uncore_forcewake_domain *d)
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{
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	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_clear);
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}

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static void
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fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
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{
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	struct intel_uncore_forcewake_domain *d;
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	unsigned int tmp;
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	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);

	for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
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		fw_domain_wait_ack_clear(i915, d);
		fw_domain_get(i915, d);
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	}
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	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
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		fw_domain_wait_ack_set(i915, d);

	i915->uncore.fw_domains_active |= fw_domains;
}

static void
fw_domains_get_with_fallback(struct drm_i915_private *i915,
			     enum forcewake_domains fw_domains)
{
	struct intel_uncore_forcewake_domain *d;
	unsigned int tmp;

	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);

	for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
		fw_domain_wait_ack_clear_fallback(i915, d);
		fw_domain_get(i915, d);
	}

	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
		fw_domain_wait_ack_set_fallback(i915, d);
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	i915->uncore.fw_domains_active |= fw_domains;
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}
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static void
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fw_domains_put(struct drm_i915_private *i915, enum forcewake_domains fw_domains)
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{
	struct intel_uncore_forcewake_domain *d;
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	unsigned int tmp;

	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);
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	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
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		fw_domain_put(i915, d);
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	i915->uncore.fw_domains_active &= ~fw_domains;
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}
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static void
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fw_domains_reset(struct drm_i915_private *i915,
		 enum forcewake_domains fw_domains)
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{
	struct intel_uncore_forcewake_domain *d;
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	unsigned int tmp;
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	if (!fw_domains)
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		return;
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	GEM_BUG_ON(fw_domains & ~i915->uncore.fw_domains);

	for_each_fw_domain_masked(d, fw_domains, i915, tmp)
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		fw_domain_reset(i915, d);
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}

static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
{
	/* w/a for a sporadic read returning 0 by waiting for the GT
	 * thread to wake up.
	 */
	if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
				GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
		DRM_ERROR("GT thread status wait timed out\n");
}

static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
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					      enum forcewake_domains fw_domains)
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{
	fw_domains_get(dev_priv, fw_domains);
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	/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
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	__gen6_gt_wait_for_thread_c0(dev_priv);
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}

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static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
{
	u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);

	return count & GT_FIFO_FREE_ENTRIES_MASK;
}

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static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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	u32 n;
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	/* On VLV, FIFO will be shared by both SW and HW.
	 * So, we need to read the FREE_ENTRIES everytime */
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	if (IS_VALLEYVIEW(dev_priv))
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		n = fifo_free_entries(dev_priv);
	else
		n = dev_priv->uncore.fifo_count;

	if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
		if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
				    GT_FIFO_NUM_RESERVED_ENTRIES,
				    GT_FIFO_TIMEOUT_MS)) {
			DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n);
			return;
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		}
	}

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	dev_priv->uncore.fifo_count = n - 1;
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}

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static enum hrtimer_restart
intel_uncore_fw_release_timer(struct hrtimer *timer)
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{
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	struct intel_uncore_forcewake_domain *domain =
	       container_of(timer, struct intel_uncore_forcewake_domain, timer);
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	struct drm_i915_private *dev_priv =
		container_of(domain, struct drm_i915_private, uncore.fw_domain[domain->id]);
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	unsigned long irqflags;
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	assert_rpm_device_not_suspended(dev_priv);
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	if (xchg(&domain->active, false))
		return HRTIMER_RESTART;

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	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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	if (WARN_ON(domain->wake_count == 0))
		domain->wake_count++;

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	if (--domain->wake_count == 0)
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		dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
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	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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	return HRTIMER_NORESTART;
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}

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/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */
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static void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore)
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{
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	unsigned long irqflags;
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	struct intel_uncore_forcewake_domain *domain;
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	int retry_count = 100;
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	enum forcewake_domains fw, active_domains;
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	iosf_mbi_assert_punit_acquired();

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	/* Hold uncore.lock across reset to prevent any register access
	 * with forcewake not set correctly. Wait until all pending
	 * timers are run before holding.
	 */
	while (1) {
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		unsigned int tmp;

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		active_domains = 0;
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		for_each_fw_domain(domain, dev_priv, tmp) {
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			smp_store_mb(domain->active, false);
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			if (hrtimer_cancel(&domain->timer) == 0)
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				continue;
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			intel_uncore_fw_release_timer(&domain->timer);
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		}
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		spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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		for_each_fw_domain(domain, dev_priv, tmp) {
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			if (hrtimer_active(&domain->timer))
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				active_domains |= domain->mask;
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		}
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		if (active_domains == 0)
			break;
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		if (--retry_count == 0) {
			DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
			break;
		}
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		spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
		cond_resched();
	}
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	WARN_ON(active_domains);

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	fw = dev_priv->uncore.fw_domains_active;
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	if (fw)
		dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
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	fw_domains_reset(dev_priv, dev_priv->uncore.fw_domains);
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	if (restore) { /* If reset with a user forcewake, try to restore */
		if (fw)
			dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);

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		if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
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			dev_priv->uncore.fifo_count =
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				fifo_free_entries(dev_priv);
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	}

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	if (!restore)
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		assert_forcewakes_inactive(dev_priv);
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	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
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}

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static u64 gen9_edram_size(struct drm_i915_private *dev_priv)
{
	const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
	const unsigned int sets[4] = { 1, 1, 2, 2 };
	const u32 cap = dev_priv->edram_cap;

	return EDRAM_NUM_BANKS(cap) *
		ways[EDRAM_WAYS_IDX(cap)] *
		sets[EDRAM_SETS_IDX(cap)] *
		1024 * 1024;
}

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u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv)
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{
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	if (!HAS_EDRAM(dev_priv))
		return 0;

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	/* The needed capability bits for size calculation
	 * are not there with pre gen9 so return 128MB always.
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	 */
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	if (INTEL_GEN(dev_priv) < 9)
		return 128 * 1024 * 1024;
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	return gen9_edram_size(dev_priv);
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}
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static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
{
	if (IS_HASWELL(dev_priv) ||
	    IS_BROADWELL(dev_priv) ||
	    INTEL_GEN(dev_priv) >= 9) {
		dev_priv->edram_cap = __raw_i915_read32(dev_priv,
							HSW_EDRAM_CAP);

		/* NB: We can't write IDICR yet because we do not have gt funcs
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		 * set up */
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	} else {
		dev_priv->edram_cap = 0;
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	}
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	if (HAS_EDRAM(dev_priv))
		DRM_INFO("Found %lluMB of eDRAM\n",
			 intel_uncore_edram_size(dev_priv) / (1024 * 1024));
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}

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static bool
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fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
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{
	u32 dbg;

	dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
	if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
		return false;

	__raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

	return true;
}

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static bool
vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
{
	u32 cer;

	cer = __raw_i915_read32(dev_priv, CLAIM_ER);
	if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
		return false;

	__raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);

	return true;
}

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static bool
gen6_check_for_fifo_debug(struct drm_i915_private *dev_priv)
{
	u32 fifodbg;

	fifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);

	if (unlikely(fifodbg)) {
		DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
		__raw_i915_write32(dev_priv, GTFIFODBG, fifodbg);
	}

	return fifodbg;
}

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static bool
check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
{
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	bool ret = false;

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	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
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		ret |= fpga_check_for_unclaimed_mmio(dev_priv);
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	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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		ret |= vlv_check_for_unclaimed_mmio(dev_priv);

	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv))
		ret |= gen6_check_for_fifo_debug(dev_priv);
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	return ret;
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}

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static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
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					  bool restore_forcewake)
{
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	/* clear out unclaimed reg detection bit */
	if (check_for_unclaimed_mmio(dev_priv))
		DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
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	/* WaDisableShadowRegForCpd:chv */
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	if (IS_CHERRYVIEW(dev_priv)) {
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		__raw_i915_write32(dev_priv, GTFIFOCTL,
				   __raw_i915_read32(dev_priv, GTFIFOCTL) |
				   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
				   GT_FIFO_CTL_RC6_POLICY_STALL);
	}

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	iosf_mbi_punit_acquire();
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	intel_uncore_forcewake_reset(dev_priv, restore_forcewake);
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	iosf_mbi_punit_release();
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}

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void intel_uncore_suspend(struct drm_i915_private *dev_priv)
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{
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	iosf_mbi_punit_acquire();
	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
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		&dev_priv->uncore.pmic_bus_access_nb);
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	intel_uncore_forcewake_reset(dev_priv, false);
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	iosf_mbi_punit_release();
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}

void intel_uncore_resume_early(struct drm_i915_private *dev_priv)
{
	__intel_uncore_early_sanitize(dev_priv, true);
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	iosf_mbi_register_pmic_bus_access_notifier(
		&dev_priv->uncore.pmic_bus_access_nb);
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	i915_check_and_clear_faults(dev_priv);
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}

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void intel_uncore_runtime_resume(struct drm_i915_private *dev_priv)
{
	iosf_mbi_register_pmic_bus_access_notifier(
		&dev_priv->uncore.pmic_bus_access_nb);
}

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void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
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{
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	/* BIOS often leaves RC6 enabled, but disable it for hw init */
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	intel_sanitize_gt_powersave(dev_priv);
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}

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static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
					 enum forcewake_domains fw_domains)
{
	struct intel_uncore_forcewake_domain *domain;
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	unsigned int tmp;
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	fw_domains &= dev_priv->uncore.fw_domains;

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	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
		if (domain->wake_count++) {
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			fw_domains &= ~domain->mask;
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			domain->active = true;
		}
	}
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	if (fw_domains)
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		dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
}

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/**
 * intel_uncore_forcewake_get - grab forcewake domain references
 * @dev_priv: i915 device instance
 * @fw_domains: forcewake domains to get reference on
 *
 * This function can be used get GT's forcewake domain references.
 * Normal register access will handle the forcewake domains automatically.
 * However if some sequence requires the GT to not power down a particular
 * forcewake domains this function should be called at the beginning of the
 * sequence. And subsequently the reference should be dropped by symmetric
 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
609
 */
610
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
611
				enum forcewake_domains fw_domains)
612 613 614
{
	unsigned long irqflags;

615 616 617
	if (!dev_priv->uncore.funcs.force_wake_get)
		return;

618
	assert_rpm_wakelock_held(dev_priv);
619

620
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
621
	__intel_uncore_forcewake_get(dev_priv, fw_domains);
622 623 624
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}

625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642
/**
 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
 * @dev_priv: i915 device instance
 *
 * This function is a wrapper around intel_uncore_forcewake_get() to acquire
 * the GT powerwell and in the process disable our debugging for the
 * duration of userspace's bypass.
 */
void intel_uncore_forcewake_user_get(struct drm_i915_private *dev_priv)
{
	spin_lock_irq(&dev_priv->uncore.lock);
	if (!dev_priv->uncore.user_forcewake.count++) {
		intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);

		/* Save and disable mmio debugging for the user bypass */
		dev_priv->uncore.user_forcewake.saved_mmio_check =
			dev_priv->uncore.unclaimed_mmio_check;
		dev_priv->uncore.user_forcewake.saved_mmio_debug =
643
			i915_modparams.mmio_debug;
644 645

		dev_priv->uncore.unclaimed_mmio_check = 0;
646
		i915_modparams.mmio_debug = 0;
647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
	}
	spin_unlock_irq(&dev_priv->uncore.lock);
}

/**
 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
 * @dev_priv: i915 device instance
 *
 * This function complements intel_uncore_forcewake_user_get() and releases
 * the GT powerwell taken on behalf of the userspace bypass.
 */
void intel_uncore_forcewake_user_put(struct drm_i915_private *dev_priv)
{
	spin_lock_irq(&dev_priv->uncore.lock);
	if (!--dev_priv->uncore.user_forcewake.count) {
		if (intel_uncore_unclaimed_mmio(dev_priv))
			dev_info(dev_priv->drm.dev,
				 "Invalid mmio detected during user access\n");

		dev_priv->uncore.unclaimed_mmio_check =
			dev_priv->uncore.user_forcewake.saved_mmio_check;
668
		i915_modparams.mmio_debug =
669 670 671 672 673 674 675
			dev_priv->uncore.user_forcewake.saved_mmio_debug;

		intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
	}
	spin_unlock_irq(&dev_priv->uncore.lock);
}

676
/**
677
 * intel_uncore_forcewake_get__locked - grab forcewake domain references
678
 * @dev_priv: i915 device instance
679
 * @fw_domains: forcewake domains to get reference on
680
 *
681 682
 * See intel_uncore_forcewake_get(). This variant places the onus
 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
683
 */
684 685 686
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains fw_domains)
{
687
	lockdep_assert_held(&dev_priv->uncore.lock);
688 689 690 691 692 693 694 695 696

	if (!dev_priv->uncore.funcs.force_wake_get)
		return;

	__intel_uncore_forcewake_get(dev_priv, fw_domains);
}

static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
					 enum forcewake_domains fw_domains)
697
{
698
	struct intel_uncore_forcewake_domain *domain;
699
	unsigned int tmp;
700

701 702
	fw_domains &= dev_priv->uncore.fw_domains;

703
	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp) {
704 705 706
		if (WARN_ON(domain->wake_count == 0))
			continue;

707 708
		if (--domain->wake_count) {
			domain->active = true;
709
			continue;
710
		}
711

712
		fw_domain_arm_timer(domain);
713
	}
714
}
715

716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
/**
 * intel_uncore_forcewake_put - release a forcewake domain reference
 * @dev_priv: i915 device instance
 * @fw_domains: forcewake domains to put references
 *
 * This function drops the device-level forcewakes for specified
 * domains obtained by intel_uncore_forcewake_get().
 */
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
				enum forcewake_domains fw_domains)
{
	unsigned long irqflags;

	if (!dev_priv->uncore.funcs.force_wake_put)
		return;

	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
	__intel_uncore_forcewake_put(dev_priv, fw_domains);
734 735 736
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}

737 738 739 740 741 742 743 744 745 746 747
/**
 * intel_uncore_forcewake_put__locked - grab forcewake domain references
 * @dev_priv: i915 device instance
 * @fw_domains: forcewake domains to get reference on
 *
 * See intel_uncore_forcewake_put(). This variant places the onus
 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
 */
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains fw_domains)
{
748
	lockdep_assert_held(&dev_priv->uncore.lock);
749 750 751 752 753 754 755

	if (!dev_priv->uncore.funcs.force_wake_put)
		return;

	__intel_uncore_forcewake_put(dev_priv, fw_domains);
}

756
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
757 758 759 760
{
	if (!dev_priv->uncore.funcs.force_wake_get)
		return;

761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777
	WARN(dev_priv->uncore.fw_domains_active,
	     "Expected all fw_domains to be inactive, but %08x are still on\n",
	     dev_priv->uncore.fw_domains_active);
}

void assert_forcewakes_active(struct drm_i915_private *dev_priv,
			      enum forcewake_domains fw_domains)
{
	if (!dev_priv->uncore.funcs.force_wake_get)
		return;

	assert_rpm_wakelock_held(dev_priv);

	fw_domains &= dev_priv->uncore.fw_domains;
	WARN(fw_domains & ~dev_priv->uncore.fw_domains_active,
	     "Expected %08x fw_domains to be active, but %08x are off\n",
	     fw_domains, fw_domains & ~dev_priv->uncore.fw_domains_active);
778 779
}

780
/* We give fast paths for the really cool registers */
781
#define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
782

783 784 785
#define GEN11_NEEDS_FORCE_WAKE(reg) \
	((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))

786 787 788 789 790 791 792 793 794 795
#define __gen6_reg_read_fw_domains(offset) \
({ \
	enum forcewake_domains __fwd; \
	if (NEEDS_FORCE_WAKE(offset)) \
		__fwd = FORCEWAKE_RENDER; \
	else \
		__fwd = 0; \
	__fwd; \
})

796
static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
797 798 799 800 801 802 803 804 805
{
	if (offset < entry->start)
		return -1;
	else if (offset > entry->end)
		return 1;
	else
		return 0;
}

806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824
/* Copied and "macroized" from lib/bsearch.c */
#define BSEARCH(key, base, num, cmp) ({                                 \
	unsigned int start__ = 0, end__ = (num);                        \
	typeof(base) result__ = NULL;                                   \
	while (start__ < end__) {                                       \
		unsigned int mid__ = start__ + (end__ - start__) / 2;   \
		int ret__ = (cmp)((key), (base) + mid__);               \
		if (ret__ < 0) {                                        \
			end__ = mid__;                                  \
		} else if (ret__ > 0) {                                 \
			start__ = mid__ + 1;                            \
		} else {                                                \
			result__ = (base) + mid__;                      \
			break;                                          \
		}                                                       \
	}                                                               \
	result__;                                                       \
})

825
static enum forcewake_domains
826
find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
827
{
828
	const struct intel_forcewake_range *entry;
829

830 831 832
	entry = BSEARCH(offset,
			dev_priv->uncore.fw_domains_table,
			dev_priv->uncore.fw_domains_table_entries,
833
			fw_range_cmp);
834

835 836 837
	if (!entry)
		return 0;

838 839 840 841 842 843 844 845
	/*
	 * The list of FW domains depends on the SKU in gen11+ so we
	 * can't determine it statically. We use FORCEWAKE_ALL and
	 * translate it here to the list of available domains.
	 */
	if (entry->domains == FORCEWAKE_ALL)
		return dev_priv->uncore.fw_domains;

846 847 848 849 850
	WARN(entry->domains & ~dev_priv->uncore.fw_domains,
	     "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
	     entry->domains & ~dev_priv->uncore.fw_domains, offset);

	return entry->domains;
851 852 853 854
}

#define GEN_FW_RANGE(s, e, d) \
	{ .start = (s), .end = (e), .domains = (d) }
855

856
#define HAS_FWTABLE(dev_priv) \
857
	(INTEL_GEN(dev_priv) >= 9 || \
858 859 860
	 IS_CHERRYVIEW(dev_priv) || \
	 IS_VALLEYVIEW(dev_priv))

861
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
862 863 864 865 866 867
static const struct intel_forcewake_range __vlv_fw_ranges[] = {
	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
	GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
868
	GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
869 870
	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
871

872
#define __fwtable_reg_read_fw_domains(offset) \
873 874
({ \
	enum forcewake_domains __fwd = 0; \
875
	if (NEEDS_FORCE_WAKE((offset))) \
876
		__fwd = find_fw_domain(dev_priv, offset); \
877 878 879
	__fwd; \
})

880 881 882 883 884 885 886 887
#define __gen11_fwtable_reg_read_fw_domains(offset) \
({ \
	enum forcewake_domains __fwd = 0; \
	if (GEN11_NEEDS_FORCE_WAKE((offset))) \
		__fwd = find_fw_domain(dev_priv, offset); \
	__fwd; \
})

888
/* *Must* be sorted by offset! See intel_shadow_table_check(). */
889
static const i915_reg_t gen8_shadowed_regs[] = {
890 891 892 893 894 895
	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
	GEN6_RPNSWREQ,			/* 0xA008 */
	GEN6_RC_VIDEO_FREQ,		/* 0xA00C */
	RING_TAIL(GEN6_BSD_RING_BASE),	/* 0x12000 (base) */
	RING_TAIL(VEBOX_RING_BASE),	/* 0x1a000 (base) */
	RING_TAIL(BLT_RING_BASE),	/* 0x22000 (base) */
896 897 898
	/* TODO: Other registers are not yet used */
};

899 900 901 902 903 904 905 906 907 908 909 910 911 912
static const i915_reg_t gen11_shadowed_regs[] = {
	RING_TAIL(RENDER_RING_BASE),		/* 0x2000 (base) */
	GEN6_RPNSWREQ,				/* 0xA008 */
	GEN6_RC_VIDEO_FREQ,			/* 0xA00C */
	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */
	RING_TAIL(GEN11_BSD_RING_BASE),		/* 0x1C0000 (base) */
	RING_TAIL(GEN11_BSD2_RING_BASE),	/* 0x1C4000 (base) */
	RING_TAIL(GEN11_VEBOX_RING_BASE),	/* 0x1C8000 (base) */
	RING_TAIL(GEN11_BSD3_RING_BASE),	/* 0x1D0000 (base) */
	RING_TAIL(GEN11_BSD4_RING_BASE),	/* 0x1D4000 (base) */
	RING_TAIL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8000 (base) */
	/* TODO: Other registers are not yet used */
};

913
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
914
{
915
	u32 offset = i915_mmio_reg_offset(*reg);
916

917
	if (key < offset)
918
		return -1;
919
	else if (key > offset)
920 921 922 923 924
		return 1;
	else
		return 0;
}

925 926 927 928 929 930
#define __is_genX_shadowed(x) \
static bool is_gen##x##_shadowed(u32 offset) \
{ \
	const i915_reg_t *regs = gen##x##_shadowed_regs; \
	return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
		       mmio_reg_cmp); \
931 932
}

933 934 935
__is_genX_shadowed(8)
__is_genX_shadowed(11)

936 937 938 939 940 941 942 943 944 945
#define __gen8_reg_write_fw_domains(offset) \
({ \
	enum forcewake_domains __fwd; \
	if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
		__fwd = FORCEWAKE_RENDER; \
	else \
		__fwd = 0; \
	__fwd; \
})

946
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
947 948
static const struct intel_forcewake_range __chv_fw_ranges[] = {
	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
949
	GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
950
	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
951
	GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
952
	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
953
	GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
954
	GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA),
955 956
	GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
957
	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
958 959
	GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
960 961 962 963 964
	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
	GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA),
	GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA),
	GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
};
965

966
#define __fwtable_reg_write_fw_domains(offset) \
967 968
({ \
	enum forcewake_domains __fwd = 0; \
969
	if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
970
		__fwd = find_fw_domain(dev_priv, offset); \
971 972 973
	__fwd; \
})

974 975 976 977 978 979 980 981
#define __gen11_fwtable_reg_write_fw_domains(offset) \
({ \
	enum forcewake_domains __fwd = 0; \
	if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
		__fwd = find_fw_domain(dev_priv, offset); \
	__fwd; \
})

982
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
983
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
984
	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
985 986
	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
987
	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
988
	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
989
	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
990
	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
991
	GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER),
992
	GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA),
993
	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
994
	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
995
	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
996
	GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER),
997
	GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA),
998
	GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER),
999
	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
1000
	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
1001
	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
1002
	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
1003
	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
1004
	GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER),
1005
	GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA),
1006
	GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER),
1007
	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
1008
	GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER),
1009
	GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
1010
	GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER),
1011
	GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA),
1012
	GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER),
1013
	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
1014
	GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER),
1015 1016
	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
1017

1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
};

1052 1053 1054 1055 1056 1057
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
	 * the chip from rc6 before touching it for real. MI_MODE is masked,
	 * hence harmless to write 0 into. */
1058
	__raw_i915_write32(dev_priv, MI_MODE, 0);
1059 1060 1061
}

static void
1062 1063 1064 1065
__unclaimed_reg_debug(struct drm_i915_private *dev_priv,
		      const i915_reg_t reg,
		      const bool read,
		      const bool before)
1066
{
1067 1068 1069
	if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
		 "Unclaimed %s register 0x%x\n",
		 read ? "read from" : "write to",
1070
		 i915_mmio_reg_offset(reg)))
1071 1072
		/* Only report the first N failures */
		i915_modparams.mmio_debug--;
1073 1074
}

1075 1076 1077 1078 1079 1080
static inline void
unclaimed_reg_debug(struct drm_i915_private *dev_priv,
		    const i915_reg_t reg,
		    const bool read,
		    const bool before)
{
1081
	if (likely(!i915_modparams.mmio_debug))
1082 1083 1084 1085 1086
		return;

	__unclaimed_reg_debug(dev_priv, reg, read, before);
}

1087
#define GEN2_READ_HEADER(x) \
1088
	u##x val = 0; \
1089
	assert_rpm_wakelock_held(dev_priv);
1090

1091
#define GEN2_READ_FOOTER \
1092 1093 1094
	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
	return val

1095
#define __gen2_read(x) \
1096
static u##x \
1097
gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1098
	GEN2_READ_HEADER(x); \
1099
	val = __raw_i915_read##x(dev_priv, reg); \
1100
	GEN2_READ_FOOTER; \
1101 1102 1103 1104
}

#define __gen5_read(x) \
static u##x \
1105
gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1106
	GEN2_READ_HEADER(x); \
1107 1108
	ilk_dummy_write(dev_priv); \
	val = __raw_i915_read##x(dev_priv, reg); \
1109
	GEN2_READ_FOOTER; \
1110 1111
}

1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
__gen5_read(8)
__gen5_read(16)
__gen5_read(32)
__gen5_read(64)
__gen2_read(8)
__gen2_read(16)
__gen2_read(32)
__gen2_read(64)

#undef __gen5_read
#undef __gen2_read

#undef GEN2_READ_FOOTER
#undef GEN2_READ_HEADER

#define GEN6_READ_HEADER(x) \
1128
	u32 offset = i915_mmio_reg_offset(reg); \
1129 1130
	unsigned long irqflags; \
	u##x val = 0; \
1131
	assert_rpm_wakelock_held(dev_priv); \
1132 1133
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
	unclaimed_reg_debug(dev_priv, reg, true, true)
1134 1135

#define GEN6_READ_FOOTER \
1136
	unclaimed_reg_debug(dev_priv, reg, true, false); \
1137 1138 1139 1140
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
	trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
	return val

1141 1142
static noinline void ___force_wake_auto(struct drm_i915_private *dev_priv,
					enum forcewake_domains fw_domains)
1143 1144
{
	struct intel_uncore_forcewake_domain *domain;
1145 1146 1147
	unsigned int tmp;

	GEM_BUG_ON(fw_domains & ~dev_priv->uncore.fw_domains);
1148

1149
	for_each_fw_domain_masked(domain, fw_domains, dev_priv, tmp)
1150 1151 1152 1153 1154 1155 1156 1157
		fw_domain_arm_timer(domain);

	dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
}

static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
				     enum forcewake_domains fw_domains)
{
1158 1159 1160
	if (WARN_ON(!fw_domains))
		return;

1161 1162 1163
	/* Turn on all requested but inactive supported forcewake domains. */
	fw_domains &= dev_priv->uncore.fw_domains;
	fw_domains &= ~dev_priv->uncore.fw_domains_active;
1164

1165 1166
	if (fw_domains)
		___force_wake_auto(dev_priv, fw_domains);
1167 1168
}

1169
#define __gen_read(func, x) \
1170
static u##x \
1171
func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
1172
	enum forcewake_domains fw_engine; \
1173
	GEN6_READ_HEADER(x); \
1174
	fw_engine = __##func##_reg_read_fw_domains(offset); \
1175
	if (fw_engine) \
1176
		__force_wake_auto(dev_priv, fw_engine); \
1177
	val = __raw_i915_read##x(dev_priv, reg); \
1178
	GEN6_READ_FOOTER; \
1179
}
1180 1181
#define __gen6_read(x) __gen_read(gen6, x)
#define __fwtable_read(x) __gen_read(fwtable, x)
1182
#define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
1183

1184 1185 1186 1187
__gen11_fwtable_read(8)
__gen11_fwtable_read(16)
__gen11_fwtable_read(32)
__gen11_fwtable_read(64)
1188 1189 1190 1191
__fwtable_read(8)
__fwtable_read(16)
__fwtable_read(32)
__fwtable_read(64)
1192 1193 1194 1195 1196
__gen6_read(8)
__gen6_read(16)
__gen6_read(32)
__gen6_read(64)

1197
#undef __gen11_fwtable_read
1198
#undef __fwtable_read
1199
#undef __gen6_read
1200 1201
#undef GEN6_READ_FOOTER
#undef GEN6_READ_HEADER
1202

1203
#define GEN2_WRITE_HEADER \
1204
	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1205
	assert_rpm_wakelock_held(dev_priv); \
1206

1207
#define GEN2_WRITE_FOOTER
1208

1209
#define __gen2_write(x) \
1210
static void \
1211
gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1212
	GEN2_WRITE_HEADER; \
1213
	__raw_i915_write##x(dev_priv, reg, val); \
1214
	GEN2_WRITE_FOOTER; \
1215 1216 1217 1218
}

#define __gen5_write(x) \
static void \
1219
gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1220
	GEN2_WRITE_HEADER; \
1221 1222
	ilk_dummy_write(dev_priv); \
	__raw_i915_write##x(dev_priv, reg, val); \
1223
	GEN2_WRITE_FOOTER; \
1224 1225
}

1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239
__gen5_write(8)
__gen5_write(16)
__gen5_write(32)
__gen2_write(8)
__gen2_write(16)
__gen2_write(32)

#undef __gen5_write
#undef __gen2_write

#undef GEN2_WRITE_FOOTER
#undef GEN2_WRITE_HEADER

#define GEN6_WRITE_HEADER \
1240
	u32 offset = i915_mmio_reg_offset(reg); \
1241 1242
	unsigned long irqflags; \
	trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1243
	assert_rpm_wakelock_held(dev_priv); \
1244 1245
	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
	unclaimed_reg_debug(dev_priv, reg, false, true)
1246 1247

#define GEN6_WRITE_FOOTER \
1248
	unclaimed_reg_debug(dev_priv, reg, false, false); \
1249 1250
	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)

1251 1252
#define __gen6_write(x) \
static void \
1253
gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1254
	GEN6_WRITE_HEADER; \
1255 1256
	if (NEEDS_FORCE_WAKE(offset)) \
		__gen6_gt_wait_for_fifo(dev_priv); \
1257
	__raw_i915_write##x(dev_priv, reg, val); \
1258
	GEN6_WRITE_FOOTER; \
1259 1260
}

1261
#define __gen_write(func, x) \
1262
static void \
1263
func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1264
	enum forcewake_domains fw_engine; \
1265
	GEN6_WRITE_HEADER; \
1266
	fw_engine = __##func##_reg_write_fw_domains(offset); \
1267
	if (fw_engine) \
1268
		__force_wake_auto(dev_priv, fw_engine); \
1269
	__raw_i915_write##x(dev_priv, reg, val); \
1270
	GEN6_WRITE_FOOTER; \
1271
}
1272 1273
#define __gen8_write(x) __gen_write(gen8, x)
#define __fwtable_write(x) __gen_write(fwtable, x)
1274
#define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
1275

1276 1277 1278
__gen11_fwtable_write(8)
__gen11_fwtable_write(16)
__gen11_fwtable_write(32)
1279 1280 1281
__fwtable_write(8)
__fwtable_write(16)
__fwtable_write(32)
1282 1283 1284
__gen8_write(8)
__gen8_write(16)
__gen8_write(32)
1285 1286 1287 1288
__gen6_write(8)
__gen6_write(16)
__gen6_write(32)

1289
#undef __gen11_fwtable_write
1290
#undef __fwtable_write
1291
#undef __gen8_write
1292
#undef __gen6_write
1293 1294
#undef GEN6_WRITE_FOOTER
#undef GEN6_WRITE_HEADER
1295

1296
#define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \
1297
do { \
1298 1299 1300
	(i915)->uncore.funcs.mmio_writeb = x##_write8; \
	(i915)->uncore.funcs.mmio_writew = x##_write16; \
	(i915)->uncore.funcs.mmio_writel = x##_write32; \
1301 1302
} while (0)

1303
#define ASSIGN_READ_MMIO_VFUNCS(i915, x) \
1304
do { \
1305 1306 1307 1308
	(i915)->uncore.funcs.mmio_readb = x##_read8; \
	(i915)->uncore.funcs.mmio_readw = x##_read16; \
	(i915)->uncore.funcs.mmio_readl = x##_read32; \
	(i915)->uncore.funcs.mmio_readq = x##_read64; \
1309 1310
} while (0)

1311 1312

static void fw_domain_init(struct drm_i915_private *dev_priv,
1313
			   enum forcewake_domain_id domain_id,
1314 1315
			   i915_reg_t reg_set,
			   i915_reg_t reg_ack)
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
{
	struct intel_uncore_forcewake_domain *d;

	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
		return;

	d = &dev_priv->uncore.fw_domain[domain_id];

	WARN_ON(d->wake_count);

1326 1327 1328
	WARN_ON(!i915_mmio_reg_valid(reg_set));
	WARN_ON(!i915_mmio_reg_valid(reg_ack));

1329 1330 1331 1332 1333 1334
	d->wake_count = 0;
	d->reg_set = reg_set;
	d->reg_ack = reg_ack;

	d->id = domain_id;

1335 1336 1337
	BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
	BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
	BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
1338 1339 1340 1341 1342 1343 1344
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));

1345

1346
	d->mask = BIT(domain_id);
1347

1348 1349
	hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
	d->timer.function = intel_uncore_fw_release_timer;
1350

1351
	dev_priv->uncore.fw_domains |= BIT(domain_id);
1352

1353
	fw_domain_reset(dev_priv, d);
1354 1355
}

1356
static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
1357
{
1358
	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
1359 1360
		return;

1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	if (IS_GEN6(dev_priv)) {
		dev_priv->uncore.fw_reset = 0;
		dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
		dev_priv->uncore.fw_clear = 0;
	} else {
		/* WaRsClearFWBitsAtReset:bdw,skl */
		dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
		dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
	}

1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399
	if (INTEL_GEN(dev_priv) >= 11) {
		int i;

		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE_RENDER_GEN9,
			       FORCEWAKE_ACK_RENDER_GEN9);
		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
			       FORCEWAKE_BLITTER_GEN9,
			       FORCEWAKE_ACK_BLITTER_GEN9);
		for (i = 0; i < I915_MAX_VCS; i++) {
			if (!HAS_ENGINE(dev_priv, _VCS(i)))
				continue;

			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
				       FORCEWAKE_MEDIA_VDBOX_GEN11(i),
				       FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
		}
		for (i = 0; i < I915_MAX_VECS; i++) {
			if (!HAS_ENGINE(dev_priv, _VECS(i)))
				continue;

			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
				       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
		}
	} else if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
1400 1401
		dev_priv->uncore.funcs.force_wake_get =
			fw_domains_get_with_fallback;
1402 1403 1404 1405 1406 1407 1408 1409 1410
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE_RENDER_GEN9,
			       FORCEWAKE_ACK_RENDER_GEN9);
		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
			       FORCEWAKE_BLITTER_GEN9,
			       FORCEWAKE_ACK_BLITTER_GEN9);
		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
			       FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1411
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1412
		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1413
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1414 1415 1416 1417
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
		fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
			       FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1418
	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1419 1420
		dev_priv->uncore.funcs.force_wake_get =
			fw_domains_get_with_thread_status;
1421
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1422 1423
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1424
	} else if (IS_IVYBRIDGE(dev_priv)) {
1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435
		u32 ecobus;

		/* IVB configs may use multi-threaded forcewake */

		/* A small trick here - if the bios hasn't configured
		 * MT forcewake, and if the device is in RC6, then
		 * force_wake_mt_get will not wake the device and the
		 * ECOBUS read will return zero. Which will be
		 * (correctly) interpreted by the test below as MT
		 * forcewake being disabled.
		 */
1436 1437
		dev_priv->uncore.funcs.force_wake_get =
			fw_domains_get_with_thread_status;
1438
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1439

1440 1441
		/* We need to init first for ECOBUS access and then
		 * determine later if we want to reinit, in case of MT access is
1442 1443 1444
		 * not working. In this stage we don't know which flavour this
		 * ivb is, so it is better to reset also the gen6 fw registers
		 * before the ecobus check.
1445
		 */
1446 1447 1448 1449

		__raw_i915_write32(dev_priv, FORCEWAKE, 0);
		__raw_posting_read(dev_priv, ECOBUS);

1450 1451
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1452

1453
		spin_lock_irq(&dev_priv->uncore.lock);
1454
		fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_RENDER);
1455
		ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1456
		fw_domains_put(dev_priv, FORCEWAKE_RENDER);
1457
		spin_unlock_irq(&dev_priv->uncore.lock);
1458

1459
		if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1460 1461
			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
			DRM_INFO("when using vblank-synced partial screen updates.\n");
1462 1463
			fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
				       FORCEWAKE, FORCEWAKE_ACK);
1464
		}
1465
	} else if (IS_GEN6(dev_priv)) {
1466
		dev_priv->uncore.funcs.force_wake_get =
1467
			fw_domains_get_with_thread_status;
1468
		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1469 1470
		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
			       FORCEWAKE, FORCEWAKE_ACK);
1471
	}
1472 1473 1474

	/* All future platforms are expected to require complex power gating */
	WARN_ON(dev_priv->uncore.fw_domains == 0);
1475 1476
}

1477 1478 1479 1480 1481 1482 1483
#define ASSIGN_FW_DOMAINS_TABLE(d) \
{ \
	dev_priv->uncore.fw_domains_table = \
			(struct intel_forcewake_range *)(d); \
	dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
}

1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
					 unsigned long action, void *data)
{
	struct drm_i915_private *dev_priv = container_of(nb,
			struct drm_i915_private, uncore.pmic_bus_access_nb);

	switch (action) {
	case MBI_PMIC_BUS_ACCESS_BEGIN:
		/*
		 * forcewake all now to make sure that we don't need to do a
		 * forcewake later which on systems where this notifier gets
		 * called requires the punit to access to the shared pmic i2c
		 * bus, which will be busy after this notification, leading to:
		 * "render: timed out waiting for forcewake ack request."
		 * errors.
1499 1500 1501 1502 1503
		 *
		 * The notifier is unregistered during intel_runtime_suspend(),
		 * so it's ok to access the HW here without holding a RPM
		 * wake reference -> disable wakeref asserts for the time of
		 * the access.
1504
		 */
1505
		disable_rpm_wakeref_asserts(dev_priv);
1506
		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1507
		enable_rpm_wakeref_asserts(dev_priv);
1508 1509 1510 1511 1512 1513 1514 1515 1516
		break;
	case MBI_PMIC_BUS_ACCESS_END:
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
		break;
	}

	return NOTIFY_OK;
}

1517
void intel_uncore_init(struct drm_i915_private *dev_priv)
1518
{
1519
	i915_check_vgpu(dev_priv);
1520

1521
	intel_uncore_edram_detect(dev_priv);
1522 1523
	intel_uncore_fw_domains_init(dev_priv);
	__intel_uncore_early_sanitize(dev_priv, false);
1524

1525
	dev_priv->uncore.unclaimed_mmio_check = 1;
1526 1527
	dev_priv->uncore.pmic_bus_access_nb.notifier_call =
		i915_pmic_bus_access_notifier;
1528

1529
	if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
1530 1531
		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
1532
	} else if (IS_GEN5(dev_priv)) {
1533 1534
		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
1535
	} else if (IS_GEN(dev_priv, 6, 7)) {
1536
		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
1537 1538 1539

		if (IS_VALLEYVIEW(dev_priv)) {
			ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges);
1540
			ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1541
		} else {
1542
			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
1543
		}
1544
	} else if (IS_GEN8(dev_priv)) {
1545
		if (IS_CHERRYVIEW(dev_priv)) {
1546
			ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
1547 1548
			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
			ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1549 1550

		} else {
1551 1552
			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
1553
		}
1554
	} else if (IS_GEN(dev_priv, 9, 10)) {
1555
		ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
1556 1557
		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
		ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
1558 1559 1560 1561
	} else {
		ASSIGN_FW_DOMAINS_TABLE(__gen11_fw_ranges);
		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen11_fwtable);
		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen11_fwtable);
1562
	}
1563

1564 1565
	iosf_mbi_register_pmic_bus_access_notifier(
		&dev_priv->uncore.pmic_bus_access_nb);
1566 1567
}

1568
void intel_uncore_fini(struct drm_i915_private *dev_priv)
1569 1570
{
	/* Paranoia: make sure we have disabled everything before we exit. */
1571
	intel_uncore_sanitize(dev_priv);
1572 1573 1574 1575

	iosf_mbi_punit_acquire();
	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
		&dev_priv->uncore.pmic_bus_access_nb);
1576
	intel_uncore_forcewake_reset(dev_priv, false);
1577
	iosf_mbi_punit_release();
1578 1579
}

1580 1581 1582 1583 1584 1585 1586 1587
static const struct reg_whitelist {
	i915_reg_t offset_ldw;
	i915_reg_t offset_udw;
	u16 gen_mask;
	u8 size;
} reg_read_whitelist[] = { {
	.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
	.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1588
	.gen_mask = INTEL_GEN_MASK(4, 11),
1589 1590
	.size = 8
} };
1591 1592 1593 1594

int i915_reg_read_ioctl(struct drm_device *dev,
			void *data, struct drm_file *file)
{
1595
	struct drm_i915_private *dev_priv = to_i915(dev);
1596
	struct drm_i915_reg_read *reg = data;
1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
	struct reg_whitelist const *entry;
	unsigned int flags;
	int remain;
	int ret = 0;

	entry = reg_read_whitelist;
	remain = ARRAY_SIZE(reg_read_whitelist);
	while (remain) {
		u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);

		GEM_BUG_ON(!is_power_of_2(entry->size));
		GEM_BUG_ON(entry->size > 8);
		GEM_BUG_ON(entry_offset & (entry->size - 1));

		if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
		    entry_offset == (reg->offset & -entry->size))
1613
			break;
1614 1615
		entry++;
		remain--;
1616 1617
	}

1618
	if (!remain)
1619 1620
		return -EINVAL;

1621
	flags = reg->offset & (entry->size - 1);
1622

1623
	intel_runtime_pm_get(dev_priv);
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635
	if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
		reg->val = I915_READ64_2x32(entry->offset_ldw,
					    entry->offset_udw);
	else if (entry->size == 8 && flags == 0)
		reg->val = I915_READ64(entry->offset_ldw);
	else if (entry->size == 4 && flags == 0)
		reg->val = I915_READ(entry->offset_ldw);
	else if (entry->size == 2 && flags == 0)
		reg->val = I915_READ16(entry->offset_ldw);
	else if (entry->size == 1 && flags == 0)
		reg->val = I915_READ8(entry->offset_ldw);
	else
1636 1637
		ret = -EINVAL;
	intel_runtime_pm_put(dev_priv);
1638

1639
	return ret;
1640 1641
}

1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
static void gen3_stop_engine(struct intel_engine_cs *engine)
{
	struct drm_i915_private *dev_priv = engine->i915;
	const u32 base = engine->mmio_base;
	const i915_reg_t mode = RING_MI_MODE(base);

	I915_WRITE_FW(mode, _MASKED_BIT_ENABLE(STOP_RING));
	if (intel_wait_for_register_fw(dev_priv,
				       mode,
				       MODE_IDLE,
				       MODE_IDLE,
				       500))
		DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
				 engine->name);

1657
	I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base)));
1658
	POSTING_READ_FW(RING_HEAD(base)); /* paranoia */
1659

1660 1661
	I915_WRITE_FW(RING_HEAD(base), 0);
	I915_WRITE_FW(RING_TAIL(base), 0);
1662
	POSTING_READ_FW(RING_TAIL(base));
1663

1664 1665 1666
	/* The ring must be empty before it is disabled */
	I915_WRITE_FW(RING_CTL(base), 0);

1667 1668 1669 1670 1671 1672 1673 1674
	/* Check acts as a post */
	if (I915_READ_FW(RING_HEAD(base)) != 0)
		DRM_DEBUG_DRIVER("%s: ring head not parked\n",
				 engine->name);
}

static void i915_stop_engines(struct drm_i915_private *dev_priv,
			      unsigned engine_mask)
1675 1676 1677 1678
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

1679 1680 1681
	if (INTEL_GEN(dev_priv) < 3)
		return;

1682 1683
	for_each_engine_masked(engine, dev_priv, engine_mask, id)
		gen3_stop_engine(engine);
1684 1685
}

1686
static bool i915_in_reset(struct pci_dev *pdev)
1687 1688
{
	u8 gdrst;
1689

1690
	pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1691
	return gdrst & GRDOM_RESET_STATUS;
1692 1693
}

1694
static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1695
{
1696
	struct pci_dev *pdev = dev_priv->drm.pdev;
1697
	int err;
1698

1699
	/* Assert reset for at least 20 usec, and wait for acknowledgement. */
1700
	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1701
	usleep_range(50, 200);
1702 1703 1704
	err = wait_for(i915_in_reset(pdev), 500);

	/* Clear the reset request. */
1705
	pci_write_config_byte(pdev, I915_GDRST, 0);
1706 1707 1708
	usleep_range(50, 200);
	if (!err)
		err = wait_for(!i915_in_reset(pdev), 500);
1709

1710
	return err;
1711 1712
}

1713
static bool g4x_reset_complete(struct pci_dev *pdev)
1714 1715
{
	u8 gdrst;
1716

1717
	pci_read_config_byte(pdev, I915_GDRST, &gdrst);
1718
	return (gdrst & GRDOM_RESET_ENABLE) == 0;
1719 1720
}

1721
static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1722
{
1723
	struct pci_dev *pdev = dev_priv->drm.pdev;
1724

1725 1726
	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
	return wait_for(g4x_reset_complete(pdev), 500);
1727 1728
}

1729
static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
1730
{
1731
	struct pci_dev *pdev = dev_priv->drm.pdev;
1732 1733 1734
	int ret;

	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
1735 1736
	I915_WRITE(VDECCLK_GATE_D,
		   I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1737 1738
	POSTING_READ(VDECCLK_GATE_D);

1739
	pci_write_config_byte(pdev, I915_GDRST,
1740
			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1741
	ret =  wait_for(g4x_reset_complete(pdev), 500);
1742 1743
	if (ret) {
		DRM_DEBUG_DRIVER("Wait for media reset failed\n");
1744
		goto out;
1745
	}
1746

1747 1748 1749 1750 1751 1752 1753
	pci_write_config_byte(pdev, I915_GDRST,
			      GRDOM_RENDER | GRDOM_RESET_ENABLE);
	ret =  wait_for(g4x_reset_complete(pdev), 500);
	if (ret) {
		DRM_DEBUG_DRIVER("Wait for render reset failed\n");
		goto out;
	}
1754

1755
out:
1756
	pci_write_config_byte(pdev, I915_GDRST, 0);
1757 1758 1759 1760 1761

	I915_WRITE(VDECCLK_GATE_D,
		   I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
	POSTING_READ(VDECCLK_GATE_D);

1762
	return ret;
1763 1764
}

1765 1766
static int ironlake_do_reset(struct drm_i915_private *dev_priv,
			     unsigned engine_mask)
1767 1768 1769
{
	int ret;

1770
	I915_WRITE(ILK_GDSR, ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1771 1772 1773
	ret = intel_wait_for_register(dev_priv,
				      ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
				      500);
1774 1775 1776 1777
	if (ret) {
		DRM_DEBUG_DRIVER("Wait for render reset failed\n");
		goto out;
	}
1778

1779
	I915_WRITE(ILK_GDSR, ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1780 1781 1782
	ret = intel_wait_for_register(dev_priv,
				      ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
				      500);
1783 1784 1785 1786
	if (ret) {
		DRM_DEBUG_DRIVER("Wait for media reset failed\n");
		goto out;
	}
1787

1788
out:
1789
	I915_WRITE(ILK_GDSR, 0);
1790 1791
	POSTING_READ(ILK_GDSR);
	return ret;
1792 1793
}

1794 1795 1796
/* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
				u32 hw_domain_mask)
1797
{
1798 1799
	int err;

1800 1801 1802 1803
	/* GEN6_GDRST is not in the gt power well, no need to check
	 * for fifo space for the write or forcewake the chip for
	 * the read
	 */
1804
	__raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
1805

1806
	/* Wait for the device to ack the reset requests */
1807
	err = intel_wait_for_register_fw(dev_priv,
1808 1809
					  GEN6_GDRST, hw_domain_mask, 0,
					  500);
1810 1811 1812 1813 1814
	if (err)
		DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
				 hw_domain_mask);

	return err;
1815 1816 1817 1818
}

/**
 * gen6_reset_engines - reset individual engines
1819
 * @dev_priv: i915 device
1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
 *
 * This function will reset the individual engines that are set in engine_mask.
 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
 *
 * Note: It is responsibility of the caller to handle the difference between
 * asking full domain reset versus reset for all available individual engines.
 *
 * Returns 0 on success, nonzero on error.
 */
1830 1831
static int gen6_reset_engines(struct drm_i915_private *dev_priv,
			      unsigned engine_mask)
1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
{
	struct intel_engine_cs *engine;
	const u32 hw_engine_mask[I915_NUM_ENGINES] = {
		[RCS] = GEN6_GRDOM_RENDER,
		[BCS] = GEN6_GRDOM_BLT,
		[VCS] = GEN6_GRDOM_MEDIA,
		[VCS2] = GEN8_GRDOM_MEDIA2,
		[VECS] = GEN6_GRDOM_VECS,
	};
	u32 hw_mask;

	if (engine_mask == ALL_ENGINES) {
		hw_mask = GEN6_GRDOM_FULL;
	} else {
1846 1847
		unsigned int tmp;

1848
		hw_mask = 0;
1849
		for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
1850 1851 1852
			hw_mask |= hw_engine_mask[engine->id];
	}

1853
	return gen6_hw_domain_reset(dev_priv, hw_mask);
1854 1855
}

1856
/**
1857
 * __intel_wait_for_register_fw - wait until register matches expected state
1858 1859 1860 1861
 * @dev_priv: the i915 device
 * @reg: the register to read
 * @mask: mask to apply to register value
 * @value: expected value
1862 1863 1864
 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
 * @slow_timeout_ms: slow timeout in millisecond
 * @out_value: optional placeholder to hold registry value
1865 1866
 *
 * This routine waits until the target register @reg contains the expected
1867 1868 1869 1870
 * @value after applying the @mask, i.e. it waits until ::
 *
 *     (I915_READ_FW(reg) & mask) == value
 *
1871
 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1872
 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1873
 * must be not larger than 20,0000 microseconds.
1874 1875 1876 1877 1878 1879 1880 1881
 *
 * Note that this routine assumes the caller holds forcewake asserted, it is
 * not suitable for very long waits. See intel_wait_for_register() if you
 * wish to wait without holding forcewake for the duration (i.e. you expect
 * the wait to be slow).
 *
 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
 */
1882 1883
int __intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
				 i915_reg_t reg,
1884 1885 1886 1887
				 u32 mask,
				 u32 value,
				 unsigned int fast_timeout_us,
				 unsigned int slow_timeout_ms,
1888
				 u32 *out_value)
1889
{
1890
	u32 uninitialized_var(reg_value);
1891 1892 1893
#define done (((reg_value = I915_READ_FW(reg)) & mask) == value)
	int ret;

1894
	/* Catch any overuse of this function */
1895 1896
	might_sleep_if(slow_timeout_ms);
	GEM_BUG_ON(fast_timeout_us > 20000);
1897

1898 1899
	ret = -ETIMEDOUT;
	if (fast_timeout_us && fast_timeout_us <= 20000)
1900
		ret = _wait_for_atomic(done, fast_timeout_us, 0);
1901
	if (ret && slow_timeout_ms)
1902
		ret = wait_for(done, slow_timeout_ms);
1903

1904 1905
	if (out_value)
		*out_value = reg_value;
1906

1907 1908 1909 1910 1911
	return ret;
#undef done
}

/**
1912
 * __intel_wait_for_register - wait until register matches expected state
1913 1914 1915 1916
 * @dev_priv: the i915 device
 * @reg: the register to read
 * @mask: mask to apply to register value
 * @value: expected value
1917 1918 1919
 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
 * @slow_timeout_ms: slow timeout in millisecond
 * @out_value: optional placeholder to hold registry value
1920 1921
 *
 * This routine waits until the target register @reg contains the expected
1922 1923 1924 1925
 * @value after applying the @mask, i.e. it waits until ::
 *
 *     (I915_READ(reg) & mask) == value
 *
1926 1927 1928 1929
 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
 *
 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
 */
1930
int __intel_wait_for_register(struct drm_i915_private *dev_priv,
1931
			    i915_reg_t reg,
1932 1933
			    u32 mask,
			    u32 value,
1934 1935 1936
			    unsigned int fast_timeout_us,
			    unsigned int slow_timeout_ms,
			    u32 *out_value)
1937
{
1938 1939
	unsigned fw =
		intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);
1940
	u32 reg_value;
1941 1942
	int ret;

1943 1944 1945 1946 1947 1948 1949
	might_sleep();

	spin_lock_irq(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv, fw);

	ret = __intel_wait_for_register_fw(dev_priv,
					   reg, mask, value,
1950
					   fast_timeout_us, 0, &reg_value);
1951 1952 1953 1954

	intel_uncore_forcewake_put__locked(dev_priv, fw);
	spin_unlock_irq(&dev_priv->uncore.lock);

1955
	if (ret)
1956 1957 1958 1959 1960 1961
		ret = __wait_for(reg_value = I915_READ_NOTRACE(reg),
				 (reg_value & mask) == value,
				 slow_timeout_ms * 1000, 10, 1000);

	if (out_value)
		*out_value = reg_value;
1962 1963

	return ret;
1964 1965
}

1966
static int gen8_reset_engine_start(struct intel_engine_cs *engine)
1967
{
1968
	struct drm_i915_private *dev_priv = engine->i915;
1969 1970 1971 1972 1973
	int ret;

	I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
		      _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));

1974 1975 1976 1977 1978
	ret = intel_wait_for_register_fw(dev_priv,
					 RING_RESET_CTL(engine->mmio_base),
					 RESET_CTL_READY_TO_RESET,
					 RESET_CTL_READY_TO_RESET,
					 700);
1979 1980 1981 1982 1983 1984
	if (ret)
		DRM_ERROR("%s: reset request timeout\n", engine->name);

	return ret;
}

1985
static void gen8_reset_engine_cancel(struct intel_engine_cs *engine)
1986
{
1987
	struct drm_i915_private *dev_priv = engine->i915;
1988 1989 1990

	I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
		      _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1991 1992
}

1993 1994
static int gen8_reset_engines(struct drm_i915_private *dev_priv,
			      unsigned engine_mask)
1995 1996
{
	struct intel_engine_cs *engine;
1997
	unsigned int tmp;
1998

1999
	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
2000
		if (gen8_reset_engine_start(engine))
2001 2002
			goto not_ready;

2003
	return gen6_reset_engines(dev_priv, engine_mask);
2004 2005

not_ready:
2006
	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
2007
		gen8_reset_engine_cancel(engine);
2008 2009 2010 2011

	return -EIO;
}

2012 2013 2014
typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask);

static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
2015
{
2016
	if (!i915_modparams.reset)
2017 2018
		return NULL;

2019
	if (INTEL_GEN(dev_priv) >= 8)
2020
		return gen8_reset_engines;
2021
	else if (INTEL_GEN(dev_priv) >= 6)
2022
		return gen6_reset_engines;
2023
	else if (IS_GEN5(dev_priv))
2024
		return ironlake_do_reset;
2025
	else if (IS_G4X(dev_priv))
2026
		return g4x_do_reset;
2027
	else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
2028
		return g33_do_reset;
2029
	else if (INTEL_GEN(dev_priv) >= 3)
2030
		return i915_do_reset;
2031
	else
2032 2033 2034
		return NULL;
}

2035
int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
2036
{
2037
	reset_func reset = intel_get_gpu_reset(dev_priv);
2038
	int retry;
2039
	int ret;
2040

2041 2042
	might_sleep();

2043 2044 2045 2046
	/* If the power well sleeps during the reset, the reset
	 * request may be dropped and never completes (causing -EIO).
	 */
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2047
	for (retry = 0; retry < 3; retry++) {
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061

		/* We stop engines, otherwise we might get failed reset and a
		 * dead gpu (on elk). Also as modern gpu as kbl can suffer
		 * from system hang if batchbuffer is progressing when
		 * the reset is issued, regardless of READY_TO_RESET ack.
		 * Thus assume it is best to stop engines on all gens
		 * where we have a gpu reset.
		 *
		 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
		 *
		 * FIXME: Wa for more modern gens needs to be validated
		 */
		i915_stop_engines(dev_priv, engine_mask);

2062 2063 2064
		ret = -ENODEV;
		if (reset)
			ret = reset(dev_priv, engine_mask);
2065 2066 2067 2068 2069
		if (ret != -ETIMEDOUT)
			break;

		cond_resched();
	}
2070 2071 2072
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	return ret;
2073 2074
}

2075
bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
2076
{
2077
	return intel_get_gpu_reset(dev_priv) != NULL;
2078 2079
}

2080 2081 2082
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
{
	return (dev_priv->info.has_reset_engine &&
2083
		i915_modparams.reset >= 2);
2084 2085
}

2086
int intel_reset_guc(struct drm_i915_private *dev_priv)
2087 2088 2089
{
	int ret;

2090
	GEM_BUG_ON(!HAS_GUC(dev_priv));
2091 2092 2093 2094 2095 2096 2097 2098

	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
	ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

	return ret;
}

2099
bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
2100
{
2101
	return check_for_unclaimed_mmio(dev_priv);
2102
}
2103

2104
bool
2105 2106
intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
{
2107
	if (unlikely(i915_modparams.mmio_debug ||
2108
		     dev_priv->uncore.unclaimed_mmio_check <= 0))
2109
		return false;
2110 2111 2112 2113 2114

	if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
		DRM_DEBUG("Unclaimed register detected, "
			  "enabling oneshot unclaimed register reporting. "
			  "Please use i915.mmio_debug=N for more information.\n");
2115
		i915_modparams.mmio_debug++;
2116
		dev_priv->uncore.unclaimed_mmio_check--;
2117
		return true;
2118
	}
2119 2120

	return false;
2121
}
2122 2123 2124 2125 2126

static enum forcewake_domains
intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
				i915_reg_t reg)
{
2127
	u32 offset = i915_mmio_reg_offset(reg);
2128 2129
	enum forcewake_domains fw_domains;

2130 2131 2132
	if (INTEL_GEN(dev_priv) >= 11) {
		fw_domains = __gen11_fwtable_reg_read_fw_domains(offset);
	} else if (HAS_FWTABLE(dev_priv)) {
2133 2134 2135 2136 2137 2138
		fw_domains = __fwtable_reg_read_fw_domains(offset);
	} else if (INTEL_GEN(dev_priv) >= 6) {
		fw_domains = __gen6_reg_read_fw_domains(offset);
	} else {
		WARN_ON(!IS_GEN(dev_priv, 2, 5));
		fw_domains = 0;
2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	}

	WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);

	return fw_domains;
}

static enum forcewake_domains
intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
				 i915_reg_t reg)
{
2150
	u32 offset = i915_mmio_reg_offset(reg);
2151 2152
	enum forcewake_domains fw_domains;

2153 2154 2155
	if (INTEL_GEN(dev_priv) >= 11) {
		fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
	} else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
2156 2157 2158 2159
		fw_domains = __fwtable_reg_write_fw_domains(offset);
	} else if (IS_GEN8(dev_priv)) {
		fw_domains = __gen8_reg_write_fw_domains(offset);
	} else if (IS_GEN(dev_priv, 6, 7)) {
2160
		fw_domains = FORCEWAKE_RENDER;
2161 2162 2163
	} else {
		WARN_ON(!IS_GEN(dev_priv, 2, 5));
		fw_domains = 0;
2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192
	}

	WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains);

	return fw_domains;
}

/**
 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
 * 				    a register
 * @dev_priv: pointer to struct drm_i915_private
 * @reg: register in question
 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
 *
 * Returns a set of forcewake domains required to be taken with for example
 * intel_uncore_forcewake_get for the specified register to be accessible in the
 * specified mode (read, write or read/write) with raw mmio accessors.
 *
 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
 * callers to do FIFO management on their own or risk losing writes.
 */
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op)
{
	enum forcewake_domains fw_domains = 0;

	WARN_ON(!op);

2193 2194 2195
	if (intel_vgpu_active(dev_priv))
		return 0;

2196 2197 2198 2199 2200 2201 2202 2203
	if (op & FW_REG_READ)
		fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg);

	if (op & FW_REG_WRITE)
		fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg);

	return fw_domains;
}
2204 2205

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2206
#include "selftests/mock_uncore.c"
2207 2208
#include "selftests/intel_uncore.c"
#endif