msm8996.dtsi 84.2 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interconnect/qcom,msm8996.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,apr.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

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	clocks {
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		xo_board: xo-board {
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			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
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		};
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		sleep_clk: sleep-clk {
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			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
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		};
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	};

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	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
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			cpu-idle-states = <&CPU_SLEEP_0>;
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			capacity-dmips-mhz = <1024>;
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			clocks = <&kryocc 0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
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			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x1>;
			enable-method = "psci";
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			cpu-idle-states = <&CPU_SLEEP_0>;
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			capacity-dmips-mhz = <1024>;
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			clocks = <&kryocc 0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
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			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
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			cpu-idle-states = <&CPU_SLEEP_0>;
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			capacity-dmips-mhz = <1024>;
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			clocks = <&kryocc 1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
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			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU3: cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x101>;
			enable-method = "psci";
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			cpu-idle-states = <&CPU_SLEEP_0>;
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			capacity-dmips-mhz = <1024>;
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			clocks = <&kryocc 1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
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			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};
			};
		};
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		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				idle-state-name = "standalone-power-collapse";
				arm,psci-suspend-param = <0x00000004>;
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				entry-latency-us = <130>;
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				exit-latency-us = <80>;
				min-residency-us = <300>;
			};
		};
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	};

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	cluster0_opp: opp-table-cluster0 {
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		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		/* Nominal fmax for now */
		opp-307200000 {
			opp-hz = /bits/ 64 <307200000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-422400000 {
			opp-hz = /bits/ 64 <422400000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-556800000 {
			opp-hz = /bits/ 64 <556800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-652800000 {
			opp-hz = /bits/ 64 <652800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-729600000 {
			opp-hz = /bits/ 64 <729600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-844800000 {
			opp-hz = /bits/ 64 <844800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-960000000 {
			opp-hz = /bits/ 64 <960000000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1036800000 {
			opp-hz = /bits/ 64 <1036800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1113600000 {
			opp-hz = /bits/ 64 <1113600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1190400000 {
			opp-hz = /bits/ 64 <1190400000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1228800000 {
			opp-hz = /bits/ 64 <1228800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1324800000 {
			opp-hz = /bits/ 64 <1324800000>;
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			opp-supported-hw = <0xd>;
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			clock-latency-ns = <200000>;
		};
		opp-1363200000 {
			opp-hz = /bits/ 64 <1363200000>;
			opp-supported-hw = <0x2>;
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			clock-latency-ns = <200000>;
		};
		opp-1401600000 {
			opp-hz = /bits/ 64 <1401600000>;
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			opp-supported-hw = <0xd>;
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			clock-latency-ns = <200000>;
		};
		opp-1478400000 {
			opp-hz = /bits/ 64 <1478400000>;
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			opp-supported-hw = <0x9>;
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			clock-latency-ns = <200000>;
		};
		opp-1497600000 {
			opp-hz = /bits/ 64 <1497600000>;
			opp-supported-hw = <0x04>;
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			clock-latency-ns = <200000>;
		};
		opp-1593600000 {
			opp-hz = /bits/ 64 <1593600000>;
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			opp-supported-hw = <0x9>;
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			clock-latency-ns = <200000>;
		};
	};

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	cluster1_opp: opp-table-cluster1 {
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		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		/* Nominal fmax for now */
		opp-307200000 {
			opp-hz = /bits/ 64 <307200000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-403200000 {
			opp-hz = /bits/ 64 <403200000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-480000000 {
			opp-hz = /bits/ 64 <480000000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-556800000 {
			opp-hz = /bits/ 64 <556800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-652800000 {
			opp-hz = /bits/ 64 <652800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-729600000 {
			opp-hz = /bits/ 64 <729600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-806400000 {
			opp-hz = /bits/ 64 <806400000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-883200000 {
			opp-hz = /bits/ 64 <883200000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-940800000 {
			opp-hz = /bits/ 64 <940800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1036800000 {
			opp-hz = /bits/ 64 <1036800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1113600000 {
			opp-hz = /bits/ 64 <1113600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1190400000 {
			opp-hz = /bits/ 64 <1190400000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1248000000 {
			opp-hz = /bits/ 64 <1248000000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1324800000 {
			opp-hz = /bits/ 64 <1324800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1401600000 {
			opp-hz = /bits/ 64 <1401600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1478400000 {
			opp-hz = /bits/ 64 <1478400000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1555200000 {
			opp-hz = /bits/ 64 <1555200000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1632000000 {
			opp-hz = /bits/ 64 <1632000000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1708800000 {
			opp-hz = /bits/ 64 <1708800000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
		opp-1785600000 {
			opp-hz = /bits/ 64 <1785600000>;
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			opp-supported-hw = <0xf>;
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			clock-latency-ns = <200000>;
		};
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		opp-1804800000 {
			opp-hz = /bits/ 64 <1804800000>;
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			opp-supported-hw = <0xe>;
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			clock-latency-ns = <200000>;
		};
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		opp-1824000000 {
			opp-hz = /bits/ 64 <1824000000>;
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			opp-supported-hw = <0x1>;
			clock-latency-ns = <200000>;
		};
		opp-1900800000 {
			opp-hz = /bits/ 64 <1900800000>;
			opp-supported-hw = <0x4>;
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			clock-latency-ns = <200000>;
		};
		opp-1920000000 {
			opp-hz = /bits/ 64 <1920000000>;
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			opp-supported-hw = <0x1>;
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			clock-latency-ns = <200000>;
		};
		opp-1996800000 {
			opp-hz = /bits/ 64 <1996800000>;
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			opp-supported-hw = <0x1>;
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			clock-latency-ns = <200000>;
		};
		opp-2073600000 {
			opp-hz = /bits/ 64 <2073600000>;
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			opp-supported-hw = <0x1>;
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			clock-latency-ns = <200000>;
		};
		opp-2150400000 {
			opp-hz = /bits/ 64 <2150400000>;
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			opp-supported-hw = <0x1>;
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			clock-latency-ns = <200000>;
		};
	};

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	firmware {
		scm {
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			compatible = "qcom,scm-msm8996", "qcom,scm";
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			qcom,dload-mode = <&tcsr_2 0x13000>;
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		};
	};
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	memory@80000000 {
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		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
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		reg = <0x0 0x80000000 0x0 0x0>;
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	};
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	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};
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	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
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		hyp_mem: memory@85800000 {
			reg = <0x0 0x85800000 0x0 0x600000>;
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			no-map;
		};
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		xbl_mem: memory@85e00000 {
			reg = <0x0 0x85e00000 0x0 0x200000>;
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			no-map;
		};
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		smem_mem: smem-mem@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
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			no-map;
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		};

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		tz_mem: memory@86200000 {
			reg = <0x0 0x86200000 0x0 0x2600000>;
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			no-map;
		};
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		rmtfs_mem: rmtfs {
			compatible = "qcom,rmtfs-mem";

			size = <0x0 0x200000>;
			alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
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			no-map;
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			qcom,client-id = <1>;
			qcom,vmid = <15>;
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		};
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		mpss_mem: mpss@88800000 {
			reg = <0x0 0x88800000 0x0 0x6200000>;
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			no-map;
		};
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		adsp_mem: adsp@8ea00000 {
			reg = <0x0 0x8ea00000 0x0 0x1b00000>;
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			no-map;
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		};

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		slpi_mem: slpi@90500000 {
			reg = <0x0 0x90500000 0x0 0xa00000>;
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			no-map;
		};
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		gpu_mem: gpu@90f00000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x90f00000 0x0 0x100000>;
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			no-map;
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		};
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		venus_mem: venus@91000000 {
			reg = <0x0 0x91000000 0x0 0x500000>;
			no-map;
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		};
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		mba_mem: mba@91500000 {
			reg = <0x0 0x91500000 0x0 0x200000>;
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			no-map;
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		};
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	};
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	rpm-glink {
		compatible = "qcom,glink-rpm";
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		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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		qcom,rpm-msg-ram = <&rpm_msg_ram>;
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		mboxes = <&apcs_glb 0>;
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		rpm_requests: rpm-requests {
			compatible = "qcom,rpm-msm8996";
			qcom,glink-channels = "rpm_requests";
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			rpmcc: qcom,rpmcc {
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				compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
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				#clock-cells = <1>;
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				clocks = <&xo_board>;
				clock-names = "xo";
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			};

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			rpmpd: power-controller {
				compatible = "qcom,msm8996-rpmpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmpd_opp_table>;

				rpmpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmpd_opp1: opp1 {
						opp-level = <1>;
					};

					rpmpd_opp2: opp2 {
						opp-level = <2>;
					};

					rpmpd_opp3: opp3 {
						opp-level = <3>;
					};

					rpmpd_opp4: opp4 {
						opp-level = <4>;
					};

					rpmpd_opp5: opp5 {
						opp-level = <5>;
					};

					rpmpd_opp6: opp6 {
						opp-level = <6>;
					};
				};
			};
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		};
	};

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	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};
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	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
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		interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
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		mboxes = <&apcs_glb 10>;
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		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;
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		adsp_smp2p_out: master-kernel {
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			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
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		};

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		adsp_smp2p_in: slave-kernel {
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			qcom,entry-name = "slave-kernel";
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			interrupt-controller;
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			#interrupt-cells = <2>;
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		};
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	};
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	smp2p-mpss {
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		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
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		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
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		mboxes = <&apcs_glb 14>;
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		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;
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		mpss_smp2p_out: master-kernel {
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			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
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		};

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		mpss_smp2p_in: slave-kernel {
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			qcom,entry-name = "slave-kernel";
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			interrupt-controller;
			#interrupt-cells = <2>;
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		};
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	};
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	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
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		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
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		mboxes = <&apcs_glb 26>;
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		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;
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		slpi_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		slpi_smp2p_in: slave-kernel {
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			qcom,entry-name = "slave-kernel";
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			interrupt-controller;
			#interrupt-cells = <2>;
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		};
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	};
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	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";
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		pcie_phy: phy-wrapper@34000 {
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			compatible = "qcom,msm8996-qmp-pcie-phy";
			reg = <0x00034000 0x488>;
			#address-cells = <1>;
			#size-cells = <1>;
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			ranges = <0x0 0x00034000 0x4000>;
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			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
				<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
				<&gcc GCC_PCIE_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";
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			resets = <&gcc GCC_PCIE_PHY_BCR>,
				<&gcc GCC_PCIE_PHY_COM_BCR>,
				<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
			reset-names = "phy", "common", "cfg";
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			status = "disabled";
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			pciephy_0: phy@1000 {
				reg = <0x1000 0x130>,
				      <0x1200 0x200>,
				      <0x1400 0x1dc>;
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				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
				clock-names = "pipe0";
				resets = <&gcc GCC_PCIE_0_PHY_BCR>;
				reset-names = "lane0";
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				#clock-cells = <0>;
				clock-output-names = "pcie_0_pipe_clk_src";

				#phy-cells = <0>;
640
			};
641

642 643 644 645
			pciephy_1: phy@2000 {
				reg = <0x2000 0x130>,
				      <0x2200 0x200>,
				      <0x2400 0x1dc>;
646

647 648 649 650
				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
				clock-names = "pipe1";
				resets = <&gcc GCC_PCIE_1_PHY_BCR>;
				reset-names = "lane1";
651 652 653 654 655

				#clock-cells = <0>;
				clock-output-names = "pcie_1_pipe_clk_src";

				#phy-cells = <0>;
656 657
			};

658 659 660 661
			pciephy_2: phy@3000 {
				reg = <0x3000 0x130>,
				      <0x3200 0x200>,
				      <0x3400 0x1dc>;
662

663 664 665 666
				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
				clock-names = "pipe2";
				resets = <&gcc GCC_PCIE_2_PHY_BCR>;
				reset-names = "lane2";
667 668 669 670 671

				#clock-cells = <0>;
				clock-output-names = "pcie_2_pipe_clk_src";

				#phy-cells = <0>;
672 673
			};
		};
674

675
		rpm_msg_ram: sram@68000 {
676 677 678
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00068000 0x6000>;
		};
679

680
		qfprom@74000 {
681
			compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
682 683 684
			reg = <0x00074000 0x8ff>;
			#address-cells = <1>;
			#size-cells = <1>;
685

686 687 688 689
			qusb2p_hstx_trim: hstx_trim@24e {
				reg = <0x24e 0x2>;
				bits = <5 4>;
			};
690

691 692 693
			qusb2s_hstx_trim: hstx_trim@24f {
				reg = <0x24f 0x1>;
				bits = <1 4>;
694 695
			};

696
			speedbin_efuse: speedbin@133 {
697 698
				reg = <0x133 0x1>;
				bits = <5 3>;
699 700 701
			};
		};

702 703 704 705 706 707
		rng: rng@83000 {
			compatible = "qcom,prng-ee";
			reg = <0x00083000 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};
708

709 710 711 712 713 714
		gcc: clock-controller@300000 {
			compatible = "qcom,gcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x00300000 0x90000>;
715

716 717
			clocks = <&rpmcc RPM_SMD_BB_CLK1>,
				 <&rpmcc RPM_SMD_LN_BB_CLK>,
718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
				 <&sleep_clk>,
				 <&pciephy_0>,
				 <&pciephy_1>,
				 <&pciephy_2>,
				 <&ssusb_phy_0>,
				 <0>, <0>, <0>;
			clock-names = "cxo",
				      "cxo2",
				      "sleep_clk",
				      "pcie_0_pipe_clk_src",
				      "pcie_1_pipe_clk_src",
				      "pcie_2_pipe_clk_src",
				      "usb3_phy_pipe_clk_src",
				      "ufs_rx_symbol_0_clk_src",
				      "ufs_rx_symbol_1_clk_src",
				      "ufs_tx_symbol_0_clk_src";
734
		};
735

736 737 738 739 740 741 742 743 744
		bimc: interconnect@408000 {
			compatible = "qcom,msm8996-bimc";
			reg = <0x00408000 0x5a000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
		};

745
		tsens0: thermal-sensor@4a9000 {
746
			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
747 748 749
			reg = <0x004a9000 0x1000>, /* TM */
			      <0x004a8000 0x1000>; /* SROT */
			#qcom,sensors = <13>;
750 751 752
			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
753 754
			#thermal-sensor-cells = <1>;
		};
755

756
		tsens1: thermal-sensor@4ad000 {
757
			compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
758 759 760
			reg = <0x004ad000 0x1000>, /* TM */
			      <0x004ac000 0x1000>; /* SROT */
			#qcom,sensors = <8>;
761 762 763
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
764 765
			#thermal-sensor-cells = <1>;
		};
766

767
		cryptobam: dma-controller@644000 {
768 769 770 771 772 773 774
			compatible = "qcom,bam-v1.7.0";
			reg = <0x00644000 0x24000>;
			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_CE1_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
775
			qcom,controlled-remotely;
776 777 778 779 780 781 782 783 784 785 786 787 788
		};

		crypto: crypto@67a000 {
			compatible = "qcom,crypto-v5.4";
			reg = <0x0067a000 0x6000>;
			clocks = <&gcc GCC_CE1_AHB_CLK>,
				 <&gcc GCC_CE1_AXI_CLK>,
				 <&gcc GCC_CE1_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 6>, <&cryptobam 7>;
			dma-names = "rx", "tx";
		};

789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856
		cnoc: interconnect@500000 {
			compatible = "qcom,msm8996-cnoc";
			reg = <0x00500000 0x1000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
				 <&rpmcc RPM_SMD_CNOC_A_CLK>;
		};

		snoc: interconnect@524000 {
			compatible = "qcom,msm8996-snoc";
			reg = <0x00524000 0x1c000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
		};

		a0noc: interconnect@543000 {
			compatible = "qcom,msm8996-a0noc";
			reg = <0x00543000 0x6000>;
			#interconnect-cells = <1>;
			clock-names = "aggre0_snoc_axi",
				      "aggre0_cnoc_ahb",
				      "aggre0_noc_mpu_cfg";
			clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
				 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
				 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
			power-domains = <&gcc AGGRE0_NOC_GDSC>;
		};

		a1noc: interconnect@562000 {
			compatible = "qcom,msm8996-a1noc";
			reg = <0x00562000 0x5000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
				 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
		};

		a2noc: interconnect@583000 {
			compatible = "qcom,msm8996-a2noc";
			reg = <0x00583000 0x7000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
				 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
		};

		mnoc: interconnect@5a4000 {
			compatible = "qcom,msm8996-mnoc";
			reg = <0x005a4000 0x1c000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a", "iface";
			clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
				 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
				 <&mmcc AHB_CLK_SRC>;
		};

		pnoc: interconnect@5c0000 {
			compatible = "qcom,msm8996-pnoc";
			reg = <0x005c0000 0x3000>;
			#interconnect-cells = <1>;
			clock-names = "bus", "bus_a";
			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
		};

857 858
		tcsr_mutex: hwlock@740000 {
			compatible = "qcom,tcsr-mutex";
859
			reg = <0x00740000 0x20000>;
860
			#hwlock-cells = <1>;
861 862
		};

863
		tcsr_1: syscon@760000 {
864 865 866 867 868
			compatible = "qcom,tcsr-msm8996", "syscon";
			reg = <0x00760000 0x20000>;
		};

		tcsr_2: syscon@7a0000 {
869 870 871
			compatible = "qcom,tcsr-msm8996", "syscon";
			reg = <0x007a0000 0x18000>;
		};
872

873 874 875 876 877 878
		mmcc: clock-controller@8c0000 {
			compatible = "qcom,mmcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x008c0000 0x40000>;
879 880 881 882 883
			clocks = <&xo_board>,
				 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
				 <&gcc GPLL0>,
				 <&dsi0_phy 1>,
				 <&dsi0_phy 0>,
884 885
				 <&dsi1_phy 1>,
				 <&dsi1_phy 0>,
886
				 <&hdmi_phy>;
887 888 889 890 891 892 893 894
			clock-names = "xo",
				      "gcc_mmss_noc_cfg_ahb_clk",
				      "gpll0",
				      "dsi0pll",
				      "dsi0pllbyte",
				      "dsi1pll",
				      "dsi1pllbyte",
				      "hdmipll";
895 896 897 898 899 900 901 902 903 904 905
			assigned-clocks = <&mmcc MMPLL9_PLL>,
					  <&mmcc MMPLL1_PLL>,
					  <&mmcc MMPLL3_PLL>,
					  <&mmcc MMPLL4_PLL>,
					  <&mmcc MMPLL5_PLL>;
			assigned-clock-rates = <624000000>,
					       <810000000>,
					       <980000000>,
					       <960000000>,
					       <825000000>;
		};
906

907 908
		mdss: mdss@900000 {
			compatible = "qcom,mdss";
909

910 911 912 913 914 915
			reg = <0x00900000 0x1000>,
			      <0x009b0000 0x1040>,
			      <0x009b8000 0x1040>;
			reg-names = "mdss_phys",
				    "vbif_phys",
				    "vbif_nrt_phys";
916

917 918
			power-domains = <&mmcc MDSS_GDSC>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
919

920 921
			interrupt-controller;
			#interrupt-cells = <1>;
922

923 924 925
			clocks = <&mmcc MDSS_AHB_CLK>,
				 <&mmcc MDSS_MDP_CLK>;
			clock-names = "iface", "core";
926

927 928 929
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
930

931 932
			status = "disabled";

933 934 935 936
			mdp: mdp@901000 {
				compatible = "qcom,mdp5";
				reg = <0x00901000 0x90000>;
				reg-names = "mdp_phys";
937

938
				interrupt-parent = <&mdss>;
939
				interrupts = <0>;
940

941 942 943 944 945 946 947 948 949 950
				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MDSS_MDP_CLK>,
					 <&mmcc SMMU_MDP_AXI_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				clock-names = "iface",
					      "bus",
					      "core",
					      "iommu",
					      "vsync";
951

952
				iommus = <&mdp_smmu 0>;
953

954 955 956 957 958
				assigned-clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				assigned-clock-rates = <300000000>,
					 <19200000>;

959 960 961 962 963
				interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
						<&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
						<&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
				interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";

964 965 966
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
967

968 969 970 971 972
					port@0 {
						reg = <0>;
						mdp5_intf3_out: endpoint {
							remote-endpoint = <&hdmi_in>;
						};
973
					};
974 975 976 977 978 979 980

					port@1 {
						reg = <1>;
						mdp5_intf1_out: endpoint {
							remote-endpoint = <&dsi0_in>;
						};
					};
981 982 983 984 985 986 987

					port@2 {
						reg = <2>;
						mdp5_intf2_out: endpoint {
							remote-endpoint = <&dsi1_in>;
						};
					};
988 989 990
				};
			};

991 992 993 994 995 996
			dsi0: dsi@994000 {
				compatible = "qcom,mdss-dsi-ctrl";
				reg = <0x00994000 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
997
				interrupts = <4>;
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012

				clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_BYTE0_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MMSS_MISC_AHB_CLK>,
					 <&mmcc MDSS_PCLK0_CLK>,
					 <&mmcc MDSS_ESC0_CLK>;
				clock-names = "mdp_core",
					      "byte",
					      "iface",
					      "bus",
					      "core_mmss",
					      "pixel",
					      "core";
1013 1014
				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
				assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040

				phys = <&dsi0_phy>;
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						dsi0_in: endpoint {
							remote-endpoint = <&mdp5_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;
						dsi0_out: endpoint {
						};
					};
				};
			};

1041
			dsi0_phy: phy@994400 {
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
				compatible = "qcom,dsi-phy-14nm";
				reg = <0x00994400 0x100>,
				      <0x00994500 0x300>,
				      <0x00994800 0x188>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

1053
				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
1054 1055 1056 1057
				clock-names = "iface", "ref";
				status = "disabled";
			};

1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079
			dsi1: dsi@996000 {
				compatible = "qcom,mdss-dsi-ctrl";
				reg = <0x00996000 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4>;

				clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_BYTE1_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MMSS_MISC_AHB_CLK>,
					 <&mmcc MDSS_PCLK1_CLK>,
					 <&mmcc MDSS_ESC1_CLK>;
				clock-names = "mdp_core",
					      "byte",
					      "iface",
					      "bus",
					      "core_mmss",
					      "pixel",
					      "core";
1080 1081
				assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
				assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107

				phys = <&dsi1_phy>;
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						dsi1_in: endpoint {
							remote-endpoint = <&mdp5_intf2_out>;
						};
					};

					port@1 {
						reg = <1>;
						dsi1_out: endpoint {
						};
					};
				};
			};

1108
			dsi1_phy: phy@996400 {
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
				compatible = "qcom,dsi-phy-14nm";
				reg = <0x00996400 0x100>,
				      <0x00996500 0x300>,
				      <0x00996800 0x188>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
				clock-names = "iface", "ref";
				status = "disabled";
			};

1125 1126 1127 1128 1129 1130 1131 1132
			hdmi: hdmi-tx@9a0000 {
				compatible = "qcom,hdmi-tx-8996";
				reg =	<0x009a0000 0x50c>,
					<0x00070000 0x6158>,
					<0x009e0000 0xfff>;
				reg-names = "core_physical",
					    "qfprom_physical",
					    "hdcp_physical";
1133

1134
				interrupt-parent = <&mdss>;
1135
				interrupts = <8>;
1136

1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
				clocks = <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_HDMI_CLK>,
					 <&mmcc MDSS_HDMI_AHB_CLK>,
					 <&mmcc MDSS_EXTPCLK_CLK>;
				clock-names =
					"mdp_core",
					"iface",
					"core",
					"alt_iface",
					"extp";
1148

1149 1150
				phys = <&hdmi_phy>;
				#sound-dai-cells = <1>;
1151

1152 1153
				status = "disabled";

1154 1155 1156
				ports {
					#address-cells = <1>;
					#size-cells = <0>;
1157

1158 1159 1160 1161 1162
					port@0 {
						reg = <0>;
						hdmi_in: endpoint {
							remote-endpoint = <&mdp5_intf3_out>;
						};
1163 1164 1165 1166
					};
				};
			};

1167
			hdmi_phy: phy@9a0600 {
1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
				#phy-cells = <0>;
				compatible = "qcom,hdmi-phy-8996";
				reg = <0x009a0600 0x1c4>,
				      <0x009a0a00 0x124>,
				      <0x009a0c00 0x124>,
				      <0x009a0e00 0x124>,
				      <0x009a1000 0x124>,
				      <0x009a1200 0x0c8>;
				reg-names = "hdmi_pll",
					    "hdmi_tx_l0",
					    "hdmi_tx_l1",
					    "hdmi_tx_l2",
					    "hdmi_tx_l3",
					    "hdmi_phy";
1182

1183
				clocks = <&mmcc MDSS_AHB_CLK>,
1184 1185
					 <&gcc GCC_HDMI_CLKREF_CLK>,
					 <&xo_board>;
1186
				clock-names = "iface",
1187 1188 1189 1190
					      "ref",
					      "xo";

				#clock-cells = <0>;
1191 1192

				status = "disabled";
1193 1194
			};
		};
1195 1196

		gpu: gpu@b00000 {
1197
			compatible = "qcom,adreno-530.2", "qcom,adreno";
1198

1199 1200
			reg = <0x00b00000 0x3f000>;
			reg-names = "kgsl_3d0_reg_memory";
1201

1202
			interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1203

1204 1205 1206 1207 1208
			clocks = <&mmcc GPU_GX_GFX3D_CLK>,
				<&mmcc GPU_AHB_CLK>,
				<&mmcc GPU_GX_RBBMTIMER_CLK>,
				<&gcc GCC_BIMC_GFX_CLK>,
				<&gcc GCC_MMSS_BIMC_GFX_CLK>;
1209

1210 1211 1212 1213 1214
			clock-names = "core",
				"iface",
				"rbbmtimer",
				"mem",
				"mem_iface";
1215

1216 1217 1218
			interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
			interconnect-names = "gfx-mem";

1219
			power-domains = <&mmcc GPU_GX_GDSC>;
1220
			iommus = <&adreno_smmu 0>;
1221

1222
			nvmem-cells = <&speedbin_efuse>;
1223
			nvmem-cell-names = "speed_bin";
1224

1225
			operating-points-v2 = <&gpu_opp_table>;
1226

1227 1228
			status = "disabled";

1229 1230
			#cooling-cells = <2>;

1231
			gpu_opp_table: opp-table {
1232
				compatible = "operating-points-v2";
1233

1234
				/*
1235 1236 1237
				 * 624Mhz is only available on speed bins 0 and 3.
				 * 560Mhz is only available on speed bins 0, 2 and 3.
				 * All the rest are available on all bins of the hardware.
1238 1239 1240
				 */
				opp-624000000 {
					opp-hz = /bits/ 64 <624000000>;
1241
					opp-supported-hw = <0x09>;
1242 1243 1244
				};
				opp-560000000 {
					opp-hz = /bits/ 64 <560000000>;
1245
					opp-supported-hw = <0x0d>;
1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
				};
				opp-510000000 {
					opp-hz = /bits/ 64 <510000000>;
					opp-supported-hw = <0xFF>;
				};
				opp-401800000 {
					opp-hz = /bits/ 64 <401800000>;
					opp-supported-hw = <0xFF>;
				};
				opp-315000000 {
					opp-hz = /bits/ 64 <315000000>;
					opp-supported-hw = <0xFF>;
				};
				opp-214000000 {
					opp-hz = /bits/ 64 <214000000>;
					opp-supported-hw = <0xFF>;
				};
				opp-133000000 {
					opp-hz = /bits/ 64 <133000000>;
					opp-supported-hw = <0xFF>;
1266 1267 1268
				};
			};

1269
			zap-shader {
1270
				memory-region = <&gpu_mem>;
1271 1272
			};
		};
1273

1274
		tlmm: pinctrl@1010000 {
1275 1276 1277 1278
			compatible = "qcom,msm8996-pinctrl";
			reg = <0x01010000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
1279
			gpio-ranges = <&tlmm 0 0 150>;
1280 1281 1282
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
1283

1284 1285
			blsp1_spi1_default: blsp1-spi1-default-state {
				spi-pins {
1286 1287 1288 1289 1290 1291
					pins = "gpio0", "gpio1", "gpio3";
					function = "blsp_spi1";
					drive-strength = <12>;
					bias-disable;
				};

1292
				cs-pins {
1293 1294 1295 1296 1297 1298 1299 1300
					pins = "gpio2";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
					output-high;
				};
			};

1301
			blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1302 1303 1304 1305 1306 1307
				pins = "gpio0", "gpio1", "gpio2", "gpio3";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-down;
			};

1308
			blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1309 1310 1311 1312 1313 1314
				pins = "gpio4", "gpio5";
				function = "blsp_uart8";
				drive-strength = <16>;
				bias-disable;
			};

1315
			blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1316 1317 1318 1319 1320 1321
				pins = "gpio4", "gpio5";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1322
			blsp2_i2c2_default: blsp2-i2c2-state {
1323 1324 1325 1326 1327 1328
				pins = "gpio6", "gpio7";
				function = "blsp_i2c8";
				drive-strength = <16>;
				bias-disable;
			};

1329
			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1330 1331 1332 1333 1334 1335
				pins = "gpio6", "gpio7";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
			blsp1_i2c6_default: blsp1-i2c6-state {
				pins = "gpio27", "gpio28";
				function = "blsp_i2c6";
				drive-strength = <16>;
				bias-disable;
			};

			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
				pins = "gpio27", "gpio28";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-up;
			};

1350
			cci0_default: cci0-default-state {
1351 1352 1353 1354 1355 1356 1357
				pins = "gpio17", "gpio18";
				function = "cci_i2c";
				drive-strength = <16>;
				bias-disable;
			};

			camera0_state_on:
1358 1359
			camera_rear_default: camera-rear-default-state {
				camera0_mclk: mclk0-pins {
1360 1361 1362 1363 1364 1365
					pins = "gpio13";
					function = "cam_mclk";
					drive-strength = <16>;
					bias-disable;
				};

1366
				camera0_rst: rst-pins {
1367 1368 1369 1370 1371 1372
					pins = "gpio25";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};

1373
				camera0_pwdn: pwdn-pins {
1374 1375 1376 1377 1378 1379 1380
					pins = "gpio26";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};
			};

1381
			cci1_default: cci1-default-state {
1382 1383 1384 1385 1386 1387 1388
				pins = "gpio19", "gpio20";
				function = "cci_i2c";
				drive-strength = <16>;
				bias-disable;
			};

			camera1_state_on:
1389 1390
			camera_board_default: camera-board-default-state {
				mclk1-pins {
1391 1392 1393 1394 1395 1396
					pins = "gpio14";
					function = "cam_mclk";
					drive-strength = <16>;
					bias-disable;
				};

1397
				pwdn-pins {
1398 1399 1400 1401 1402 1403
					pins = "gpio98";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};

1404
				rst-pins {
1405 1406 1407 1408 1409 1410 1411 1412
					pins = "gpio104";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};
			};

			camera2_state_on:
1413 1414
			camera_front_default: camera-front-default-state {
				camera2_mclk: mclk2-pins {
1415 1416 1417 1418 1419 1420
					pins = "gpio15";
					function = "cam_mclk";
					drive-strength = <16>;
					bias-disable;
				};

1421
				camera2_rst: rst-pins {
1422 1423 1424 1425 1426 1427
					pins = "gpio23";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};

1428
				pwdn-pins {
1429 1430 1431 1432 1433 1434 1435
					pins = "gpio133";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
				};
			};

1436 1437
			pcie0_state_on: pcie0-state-on-state {
				perst-pins {
1438 1439 1440 1441 1442 1443
					pins = "gpio35";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

1444
				clkreq-pins {
1445 1446 1447 1448 1449 1450
					pins = "gpio36";
					function = "pci_e0";
					drive-strength = <2>;
					bias-pull-up;
				};

1451
				wake-pins {
1452 1453 1454 1455 1456 1457 1458
					pins = "gpio37";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

1459 1460
			pcie0_state_off: pcie0-state-off-state {
				perst-pins {
1461 1462 1463 1464 1465 1466
					pins = "gpio35";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

1467
				clkreq-pins {
1468 1469 1470 1471 1472 1473
					pins = "gpio36";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};

1474
				wake-pins {
1475 1476 1477 1478 1479 1480 1481
					pins = "gpio37";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};

1482
			blsp1_uart2_default: blsp1-uart2-default-state {
1483 1484 1485 1486 1487 1488
				pins = "gpio41", "gpio42", "gpio43", "gpio44";
				function = "blsp_uart2";
				drive-strength = <16>;
				bias-disable;
			};

1489
			blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1490 1491 1492 1493 1494 1495
				pins = "gpio41", "gpio42", "gpio43", "gpio44";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1496
			blsp1_i2c3_default: blsp1-i2c3-default-state {
1497 1498 1499
				pins = "gpio47", "gpio48";
				function = "blsp_i2c3";
				drive-strength = <16>;
1500
				bias-disable;
1501 1502
			};

1503
			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1504 1505 1506
				pins = "gpio47", "gpio48";
				function = "gpio";
				drive-strength = <2>;
1507
				bias-disable;
1508 1509
			};

1510
			blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1511 1512 1513 1514 1515 1516
				pins = "gpio49", "gpio50", "gpio51", "gpio52";
				function = "blsp_uart9";
				drive-strength = <16>;
				bias-disable;
			};

1517
			blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1518 1519 1520 1521 1522 1523
				pins = "gpio49", "gpio50", "gpio51", "gpio52";
				function = "blsp_uart9";
				drive-strength = <2>;
				bias-disable;
			};

1524
			blsp2_i2c3_default: blsp2-i2c3-state-state {
1525 1526 1527 1528 1529 1530
				pins = "gpio51", "gpio52";
				function = "blsp_i2c9";
				drive-strength = <16>;
				bias-disable;
			};

1531
			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1532 1533 1534 1535 1536 1537
				pins = "gpio51", "gpio52";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1538
			wcd_intr_default: wcd-intr-default-state {
1539 1540 1541 1542 1543 1544 1545
				pins = "gpio54";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-down;
				input-enable;
			};

1546
			blsp2_i2c1_default: blsp2-i2c1-state {
1547 1548 1549 1550 1551 1552
				pins = "gpio55", "gpio56";
				function = "blsp_i2c7";
				drive-strength = <16>;
				bias-disable;
			};

1553
			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1554 1555 1556 1557 1558 1559
				pins = "gpio55", "gpio56";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1560
			blsp2_i2c5_default: blsp2-i2c5-state {
1561 1562 1563 1564 1565 1566 1567 1568
				pins = "gpio60", "gpio61";
				function = "blsp_i2c11";
				drive-strength = <2>;
				bias-disable;
			};

			/* Sleep state for BLSP2_I2C5 is missing.. */

1569
			cdc_reset_active: cdc-reset-active-state {
1570 1571 1572 1573 1574 1575 1576
				pins = "gpio64";
				function = "gpio";
				drive-strength = <16>;
				bias-pull-down;
				output-high;
			};

1577
			cdc_reset_sleep: cdc-reset-sleep-state {
1578 1579 1580 1581 1582 1583 1584
				pins = "gpio64";
				function = "gpio";
				drive-strength = <16>;
				bias-disable;
				output-low;
			};

1585
			blsp2_spi6_default: blsp2-spi6-default-state {
1586
				spi-pins {
1587 1588 1589 1590 1591 1592
					pins = "gpio85", "gpio86", "gpio88";
					function = "blsp_spi12";
					drive-strength = <12>;
					bias-disable;
				};

1593
				cs-pins {
1594 1595 1596 1597 1598 1599 1600 1601
					pins = "gpio87";
					function = "gpio";
					drive-strength = <16>;
					bias-disable;
					output-high;
				};
			};

1602
			blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1603 1604 1605 1606 1607 1608
				pins = "gpio85", "gpio86", "gpio87", "gpio88";
				function = "gpio";
				drive-strength = <2>;
				bias-pull-down;
			};

1609
			blsp2_i2c6_default: blsp2-i2c6-state {
1610 1611 1612 1613 1614 1615
				pins = "gpio87", "gpio88";
				function = "blsp_i2c12";
				drive-strength = <16>;
				bias-disable;
			};

1616
			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1617 1618 1619 1620 1621 1622
				pins = "gpio87", "gpio88";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

1623 1624
			pcie1_state_on: pcie1-on-state {
				perst-pins {
1625 1626 1627 1628 1629 1630
					pins = "gpio130";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

1631
				clkreq-pins {
1632 1633 1634 1635 1636 1637
					pins = "gpio131";
					function = "pci_e1";
					drive-strength = <2>;
					bias-pull-up;
				};

1638
				wake-pins {
1639 1640 1641 1642 1643 1644 1645
					pins = "gpio132";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

1646
			pcie1_state_off: pcie1-off-state {
1647
				/* Perst is missing? */
1648
				clkreq-pins {
1649 1650 1651 1652 1653 1654
					pins = "gpio131";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};

1655
				wake-pins {
1656 1657 1658 1659 1660 1661 1662
					pins = "gpio132";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};

1663 1664
			pcie2_state_on: pcie2-on-state {
				perst-pins {
1665 1666 1667 1668 1669 1670
					pins = "gpio114";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

1671
				clkreq-pins {
1672 1673 1674 1675 1676 1677
					pins = "gpio115";
					function = "pci_e2";
					drive-strength = <2>;
					bias-pull-up;
				};

1678
				wake-pins {
1679 1680 1681 1682 1683 1684 1685
					pins = "gpio116";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

1686
			pcie2_state_off: pcie2-off-state {
1687
				/* Perst is missing? */
1688
				clkreq-pins {
1689 1690 1691 1692 1693 1694
					pins = "gpio115";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};

1695
				wake-pins {
1696 1697 1698 1699 1700 1701 1702
					pins = "gpio116";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};

1703 1704
			sdc1_state_on: sdc1-on-state {
				clk-pins {
1705 1706 1707 1708 1709
					pins = "sdc1_clk";
					bias-disable;
					drive-strength = <16>;
				};

1710
				cmd-pins {
1711 1712 1713 1714 1715
					pins = "sdc1_cmd";
					bias-pull-up;
					drive-strength = <10>;
				};

1716
				data-pins {
1717 1718 1719 1720 1721
					pins = "sdc1_data";
					bias-pull-up;
					drive-strength = <10>;
				};

1722
				rclk-pins {
1723 1724 1725 1726 1727
					pins = "sdc1_rclk";
					bias-pull-down;
				};
			};

1728 1729
			sdc1_state_off: sdc1-off-state {
				clk-pins {
1730 1731 1732 1733 1734
					pins = "sdc1_clk";
					bias-disable;
					drive-strength = <2>;
				};

1735
				cmd-pins {
1736 1737 1738 1739 1740
					pins = "sdc1_cmd";
					bias-pull-up;
					drive-strength = <2>;
				};

1741
				data-pins {
1742 1743 1744 1745 1746
					pins = "sdc1_data";
					bias-pull-up;
					drive-strength = <2>;
				};

1747
				rclk-pins {
1748 1749 1750 1751 1752
					pins = "sdc1_rclk";
					bias-pull-down;
				};
			};

1753 1754
			sdc2_state_on: sdc2-on-state {
				clk-pins {
1755 1756 1757 1758 1759
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <16>;
				};

1760
				cmd-pins {
1761 1762 1763 1764 1765
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <10>;
				};

1766
				data-pins {
1767 1768 1769 1770 1771 1772
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <10>;
				};
			};

1773 1774
			sdc2_state_off: sdc2-off-state {
				clk-pins {
1775 1776 1777 1778 1779
					pins = "sdc2_clk";
					bias-disable;
					drive-strength = <2>;
				};

1780
				cmd-pins {
1781 1782 1783 1784 1785
					pins = "sdc2_cmd";
					bias-pull-up;
					drive-strength = <2>;
				};

1786
				data-pins {
1787 1788 1789 1790 1791
					pins = "sdc2_data";
					bias-pull-up;
					drive-strength = <2>;
				};
			};
1792
		};
1793

1794 1795 1796 1797 1798
		sram@290000 {
			compatible = "qcom,rpm-stats";
			reg = <0x00290000 0x10000>;
		};

1799
		spmi_bus: spmi@400f000 {
1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0400f000 0x1000>,
			      <0x04400000 0x800000>,
			      <0x04c00000 0x800000>,
			      <0x05800000 0x200000>,
			      <0x0400a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
1815 1816
		};

1817 1818 1819 1820 1821 1822
		agnoc@0 {
			power-domains = <&gcc AGGRE0_NOC_GDSC>;
			compatible = "simple-pm-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
1823

1824
			pcie0: pcie@600000 {
1825
				compatible = "qcom,pcie-msm8996";
1826 1827 1828 1829
				status = "disabled";
				power-domains = <&gcc PCIE0_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;
1830

1831 1832 1833 1834 1835
				reg = <0x00600000 0x2000>,
				      <0x0c000000 0xf1d>,
				      <0x0c000f20 0xa8>,
				      <0x0c100000 0x100000>;
				reg-names = "parf", "dbi", "elbi","config";
1836

1837 1838
				phys = <&pciephy_0>;
				phy-names = "pciephy";
1839

1840 1841 1842 1843
				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
					<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1844

1845 1846
				device_type = "pci";

1847 1848 1849 1850 1851 1852 1853 1854
				interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1855

1856
				pinctrl-names = "default", "sleep";
1857 1858
				pinctrl-0 = <&pcie0_state_on>;
				pinctrl-1 = <&pcie0_state_off>;
1859

1860
				linux,pci-domain = <0>;
1861

1862 1863 1864 1865 1866
				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
					<&gcc GCC_PCIE_0_AUX_CLK>,
					<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1867

1868
				clock-names = "pipe",
1869 1870 1871 1872
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";
1873

1874
			};
1875

1876
			pcie1: pcie@608000 {
1877
				compatible = "qcom,pcie-msm8996";
1878 1879 1880
				power-domains = <&gcc PCIE1_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;
1881

1882
				status = "disabled";
1883

1884 1885 1886 1887
				reg = <0x00608000 0x2000>,
				      <0x0d000000 0xf1d>,
				      <0x0d000f20 0xa8>,
				      <0x0d100000 0x100000>;
1888

1889
				reg-names = "parf", "dbi", "elbi","config";
1890

1891 1892
				phys = <&pciephy_1>;
				phy-names = "pciephy";
1893

1894 1895 1896 1897
				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
					<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1898

1899 1900
				device_type = "pci";

1901 1902 1903 1904 1905 1906 1907 1908 1909 1910
				interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

				pinctrl-names = "default", "sleep";
1911 1912
				pinctrl-0 = <&pcie1_state_on>;
				pinctrl-1 = <&pcie1_state_off>;
1913 1914 1915 1916 1917 1918 1919 1920 1921

				linux,pci-domain = <1>;

				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
					<&gcc GCC_PCIE_1_AUX_CLK>,
					<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_1_SLV_AXI_CLK>;

1922
				clock-names = "pipe",
1923 1924 1925 1926 1927 1928 1929
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";
			};

			pcie2: pcie@610000 {
1930
				compatible = "qcom,pcie-msm8996";
1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961
				power-domains = <&gcc PCIE2_GDSC>;
				bus-range = <0x00 0xff>;
				num-lanes = <1>;
				status = "disabled";
				reg = <0x00610000 0x2000>,
				      <0x0e000000 0xf1d>,
				      <0x0e000f20 0xa8>,
				      <0x0e100000 0x100000>;

				reg-names = "parf", "dbi", "elbi","config";

				phys = <&pciephy_2>;
				phy-names = "pciephy";

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
					<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;

				device_type = "pci";

				interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "msi";
				#interrupt-cells = <1>;
				interrupt-map-mask = <0 0 0 0x7>;
				interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
						<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
						<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
						<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

				pinctrl-names = "default", "sleep";
1962 1963
				pinctrl-0 = <&pcie2_state_on>;
				pinctrl-1 = <&pcie2_state_off>;
1964 1965 1966 1967 1968 1969 1970 1971

				linux,pci-domain = <2>;
				clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
					<&gcc GCC_PCIE_2_AUX_CLK>,
					<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
					<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
					<&gcc GCC_PCIE_2_SLV_AXI_CLK>;

1972
				clock-names = "pipe",
1973 1974 1975 1976 1977 1978 1979 1980
						"aux",
						"cfg",
						"bus_master",
						"bus_slave";
			};
		};

		ufshc: ufshc@624000 {
1981 1982
			compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
				     "jedec,ufs-2.0";
1983 1984 1985
			reg = <0x00624000 0x2500>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

1986
			phys = <&ufsphy_lane>;
1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029
			phy-names = "ufsphy";

			power-domains = <&gcc UFS_GDSC>;

			clock-names =
				"core_clk_src",
				"core_clk",
				"bus_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro_src",
				"core_clk_unipro",
				"core_clk_ice",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk";
			clocks =
				<&gcc UFS_AXI_CLK_SRC>,
				<&gcc GCC_UFS_AXI_CLK>,
				<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
				<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
				<&gcc GCC_UFS_AHB_CLK>,
				<&gcc UFS_ICE_CORE_CLK_SRC>,
				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
				<&gcc GCC_UFS_ICE_CORE_CLK>,
				<&rpmcc RPM_SMD_LN_BB_CLK>,
				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
			freq-table-hz =
				<100000000 200000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>,
				<150000000 300000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			lanes-per-direction = <1>;
			#reset-cells = <1>;
2030
			status = "disabled";
2031 2032 2033
		};

		ufsphy: phy@627000 {
2034 2035 2036 2037 2038 2039 2040 2041 2042
			compatible = "qcom,msm8996-qmp-ufs-phy";
			reg = <0x00627000 0x1c4>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_UFS_CLKREF_CLK>;
			clock-names = "ref";

2043
			resets = <&ufshc 0>;
2044
			reset-names = "ufsphy";
2045
			status = "disabled";
2046

2047
			ufsphy_lane: phy@627400 {
2048 2049 2050 2051 2052
				reg = <0x627400 0x12c>,
				      <0x627600 0x200>,
				      <0x627c00 0x1b4>;
				#phy-cells = <0>;
			};
2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
		};

		camss: camss@a00000 {
			compatible = "qcom,msm8996-camss";
			reg = <0x00a34000 0x1000>,
			      <0x00a00030 0x4>,
			      <0x00a35000 0x1000>,
			      <0x00a00038 0x4>,
			      <0x00a36000 0x1000>,
			      <0x00a00040 0x4>,
			      <0x00a30000 0x100>,
			      <0x00a30400 0x100>,
			      <0x00a30800 0x100>,
			      <0x00a30c00 0x100>,
			      <0x00a31000 0x500>,
			      <0x00a00020 0x10>,
			      <0x00a10000 0x1000>,
			      <0x00a14000 0x1000>;
			reg-names = "csiphy0",
				"csiphy0_clk_mux",
				"csiphy1",
				"csiphy1_clk_mux",
				"csiphy2",
				"csiphy2_clk_mux",
				"csid0",
				"csid1",
				"csid2",
				"csid3",
				"ispif",
				"csi_clk_mux",
				"vfe0",
				"vfe1";
2085 2086 2087 2088 2089 2090 2091 2092 2093 2094
			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2095 2096 2097 2098 2099 2100 2101 2102 2103 2104
			interrupt-names = "csiphy0",
				"csiphy1",
				"csiphy2",
				"csid0",
				"csid1",
				"csid2",
				"csid3",
				"ispif",
				"vfe0",
				"vfe1";
2105 2106
			power-domains = <&mmcc VFE0_GDSC>,
					<&mmcc VFE1_GDSC>;
2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187
			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
				<&mmcc CAMSS_ISPIF_AHB_CLK>,
				<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
				<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
				<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
				<&mmcc CAMSS_CSI0_AHB_CLK>,
				<&mmcc CAMSS_CSI0_CLK>,
				<&mmcc CAMSS_CSI0PHY_CLK>,
				<&mmcc CAMSS_CSI0PIX_CLK>,
				<&mmcc CAMSS_CSI0RDI_CLK>,
				<&mmcc CAMSS_CSI1_AHB_CLK>,
				<&mmcc CAMSS_CSI1_CLK>,
				<&mmcc CAMSS_CSI1PHY_CLK>,
				<&mmcc CAMSS_CSI1PIX_CLK>,
				<&mmcc CAMSS_CSI1RDI_CLK>,
				<&mmcc CAMSS_CSI2_AHB_CLK>,
				<&mmcc CAMSS_CSI2_CLK>,
				<&mmcc CAMSS_CSI2PHY_CLK>,
				<&mmcc CAMSS_CSI2PIX_CLK>,
				<&mmcc CAMSS_CSI2RDI_CLK>,
				<&mmcc CAMSS_CSI3_AHB_CLK>,
				<&mmcc CAMSS_CSI3_CLK>,
				<&mmcc CAMSS_CSI3PHY_CLK>,
				<&mmcc CAMSS_CSI3PIX_CLK>,
				<&mmcc CAMSS_CSI3RDI_CLK>,
				<&mmcc CAMSS_AHB_CLK>,
				<&mmcc CAMSS_VFE0_CLK>,
				<&mmcc CAMSS_CSI_VFE0_CLK>,
				<&mmcc CAMSS_VFE0_AHB_CLK>,
				<&mmcc CAMSS_VFE0_STREAM_CLK>,
				<&mmcc CAMSS_VFE1_CLK>,
				<&mmcc CAMSS_CSI_VFE1_CLK>,
				<&mmcc CAMSS_VFE1_AHB_CLK>,
				<&mmcc CAMSS_VFE1_STREAM_CLK>,
				<&mmcc CAMSS_VFE_AHB_CLK>,
				<&mmcc CAMSS_VFE_AXI_CLK>;
			clock-names = "top_ahb",
				"ispif_ahb",
				"csiphy0_timer",
				"csiphy1_timer",
				"csiphy2_timer",
				"csi0_ahb",
				"csi0",
				"csi0_phy",
				"csi0_pix",
				"csi0_rdi",
				"csi1_ahb",
				"csi1",
				"csi1_phy",
				"csi1_pix",
				"csi1_rdi",
				"csi2_ahb",
				"csi2",
				"csi2_phy",
				"csi2_pix",
				"csi2_rdi",
				"csi3_ahb",
				"csi3",
				"csi3_phy",
				"csi3_pix",
				"csi3_rdi",
				"ahb",
				"vfe0",
				"csi_vfe0",
				"vfe0_ahb",
				"vfe0_stream",
				"vfe1",
				"csi_vfe1",
				"vfe1_ahb",
				"vfe1_stream",
				"vfe_ahb",
				"vfe_axi";
			iommus = <&vfe_smmu 0>,
				 <&vfe_smmu 1>,
				 <&vfe_smmu 2>,
				 <&vfe_smmu 3>;
			status = "disabled";
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
2188 2189
		};

2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226
		cci: cci@a0c000 {
			compatible = "qcom,msm8996-cci";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xa0c000 0x1000>;
			interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
			power-domains = <&mmcc CAMSS_GDSC>;
			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
				 <&mmcc CAMSS_CCI_AHB_CLK>,
				 <&mmcc CAMSS_CCI_CLK>,
				 <&mmcc CAMSS_AHB_CLK>;
			clock-names = "camss_top_ahb",
				      "cci_ahb",
				      "cci",
				      "camss_ahb";
			assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
					  <&mmcc CAMSS_CCI_CLK>;
			assigned-clock-rates = <80000000>, <37500000>;
			pinctrl-names = "default";
			pinctrl-0 = <&cci0_default &cci1_default>;
			status = "disabled";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cci_i2c1: i2c-bus@1 {
				reg = <1>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

2227
		adreno_smmu: iommu@b40000 {
2228
			compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2229 2230 2231 2232 2233 2234 2235 2236
			reg = <0x00b40000 0x10000>;

			#global-interrupts = <1>;
			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;

2237 2238 2239
			clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
				 <&mmcc GPU_AHB_CLK>;
			clock-names = "bus", "iface";
2240 2241

			power-domains = <&mmcc GPU_GDSC>;
2242 2243
		};

2244
		venus: video-codec@c00000 {
2245 2246 2247 2248 2249 2250 2251 2252 2253
			compatible = "qcom,msm8996-venus";
			reg = <0x00c00000 0xff000>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&mmcc VENUS_GDSC>;
			clocks = <&mmcc VIDEO_CORE_CLK>,
				 <&mmcc VIDEO_AHB_CLK>,
				 <&mmcc VIDEO_AXI_CLK>,
				 <&mmcc VIDEO_MAXI_CLK>;
			clock-names = "core", "iface", "bus", "mbus";
2254 2255 2256
			interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
					<&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
			interconnect-names = "video-mem", "cpu-cfg";
2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276
			iommus = <&venus_smmu 0x00>,
				 <&venus_smmu 0x01>,
				 <&venus_smmu 0x0a>,
				 <&venus_smmu 0x07>,
				 <&venus_smmu 0x0e>,
				 <&venus_smmu 0x0f>,
				 <&venus_smmu 0x08>,
				 <&venus_smmu 0x09>,
				 <&venus_smmu 0x0b>,
				 <&venus_smmu 0x0c>,
				 <&venus_smmu 0x0d>,
				 <&venus_smmu 0x10>,
				 <&venus_smmu 0x11>,
				 <&venus_smmu 0x21>,
				 <&venus_smmu 0x28>,
				 <&venus_smmu 0x29>,
				 <&venus_smmu 0x2b>,
				 <&venus_smmu 0x2c>,
				 <&venus_smmu 0x2d>,
				 <&venus_smmu 0x31>;
2277
			memory-region = <&venus_mem>;
2278
			status = "disabled";
2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292

			video-decoder {
				compatible = "venus-decoder";
				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
				clock-names = "core";
				power-domains = <&mmcc VENUS_CORE0_GDSC>;
			};

			video-encoder {
				compatible = "venus-encoder";
				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
				clock-names = "core";
				power-domains = <&mmcc VENUS_CORE1_GDSC>;
			};
2293 2294
		};

2295 2296 2297 2298 2299 2300 2301 2302 2303
		mdp_smmu: iommu@d00000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0x00d00000 0x10000>;

			#global-interrupts = <1>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
2304 2305 2306
			clocks = <&mmcc SMMU_MDP_AXI_CLK>,
				 <&mmcc SMMU_MDP_AHB_CLK>;
			clock-names = "bus", "iface";
2307 2308

			power-domains = <&mmcc MDSS_GDSC>;
2309 2310
		};

2311
		venus_smmu: iommu@d40000 {
2312
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2313
			reg = <0x00d40000 0x20000>;
2314 2315 2316 2317 2318 2319 2320 2321 2322 2323
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2324 2325 2326
			clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
				 <&mmcc SMMU_VIDEO_AHB_CLK>;
			clock-names = "bus", "iface";
2327 2328
			#iommu-cells = <1>;
			status = "okay";
2329 2330
		};

2331 2332 2333 2334 2335 2336 2337 2338 2339
		vfe_smmu: iommu@da0000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0x00da0000 0x10000>;

			#global-interrupts = <1>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2340 2341 2342
			clocks = <&mmcc SMMU_VFE_AXI_CLK>,
				 <&mmcc SMMU_VFE_AHB_CLK>;
			clock-names = "bus", "iface";
2343
			#iommu-cells = <1>;
2344 2345
		};

2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
		lpass_q6_smmu: iommu@1600000 {
			compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
			reg = <0x01600000 0x20000>;
			#iommu-cells = <1>;
			power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;

			#global-interrupts = <1>;
			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
		                <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;

2367 2368 2369
			clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
				 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
			clock-names = "bus", "iface";
2370 2371
		};

2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
		slpi_pil: remoteproc@1c00000 {
			compatible = "qcom,msm8996-slpi-pil";
			reg = <0x01c00000 0x4000>;

			interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			clocks = <&xo_board>,
				 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
			clock-names = "xo", "aggre2";

			memory-region = <&slpi_mem>;

			qcom,smem-states = <&slpi_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			power-domains = <&rpmpd MSM8996_VDDSSCX>;
			power-domain-names = "ssc_cx";

			status = "disabled";

			smd-edge {
				interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;

				label = "dsps";
				mboxes = <&apcs_glb 25>;
				qcom,smd-edge = <3>;
				qcom,remote-pid = <3>;
			};
		};

		mss_pil: remoteproc@2080000 {
			compatible = "qcom,msm8996-mss-pil";
			reg = <0x2080000 0x100>,
			      <0x2180000 0x020>;
			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
					      <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
					      <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack",
					  "shutdown-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&xo_board>,
				 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
				 <&rpmcc RPM_SMD_PCNOC_CLK>,
				 <&rpmcc RPM_SMD_QDSS_CLK>;
			clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
				      "snoc_axi", "mnoc_axi", "pnoc", "qdss";

			resets = <&gcc GCC_MSS_RESTART>;
			reset-names = "mss_restart";

			power-domains = <&rpmpd MSM8996_VDDCX>,
					<&rpmpd MSM8996_VDDMX>;
			power-domain-names = "cx", "mx";

			qcom,smem-states = <&mpss_smp2p_out 0>;
			qcom,smem-state-names = "stop";

2449
			qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470

			status = "disabled";

			mba {
				memory-region = <&mba_mem>;
			};

			mpss {
				memory-region = <&mpss_mem>;
			};

			smd-edge {
				interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;

				label = "mpss";
				mboxes = <&apcs_glb 12>;
				qcom,smd-edge = <0>;
				qcom,remote-pid = <1>;
			};
		};

2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487
		stm@3002000 {
			compatible = "arm,coresight-stm", "arm,primecell";
			reg = <0x3002000 0x1000>,
			      <0x8280000 0x180000>;
			reg-names = "stm-base", "stm-stimulus-base";

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					stm_out: endpoint {
						remote-endpoint =
						  <&funnel0_in>;
					};
				};
			};
2488 2489
		};

2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
		tpiu@3020000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x3020000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint =
						  <&replicator_out1>;
					};
				};
			};
		};

		funnel@3021000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3021000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2513

2514 2515 2516
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;
2517

2518 2519 2520 2521 2522 2523 2524 2525
				port@7 {
					reg = <7>;
					funnel0_in: endpoint {
						remote-endpoint =
						  <&stm_out>;
					};
				};
			};
2526

2527 2528 2529 2530 2531 2532 2533 2534
			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint =
						  <&merge_funnel_in0>;
					};
				};
			};
2535 2536
		};

2537 2538 2539
		funnel@3022000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3022000 0x1000>;
2540

2541 2542
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2543

2544 2545 2546
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;
2547

2548 2549 2550 2551 2552 2553 2554
				port@6 {
					reg = <6>;
					funnel1_in: endpoint {
						remote-endpoint =
						  <&apss_merge_funnel_out>;
					};
				};
2555 2556
			};

2557 2558 2559 2560 2561 2562 2563
			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint =
						  <&merge_funnel_in1>;
					};
				};
2564
			};
2565
		};
2566

2567 2568 2569
		funnel@3023000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3023000 0x1000>;
2570

2571 2572
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2573

2574 2575 2576 2577 2578 2579 2580 2581

			out-ports {
				port {
					funnel2_out: endpoint {
						remote-endpoint =
						  <&merge_funnel_in2>;
					};
				};
2582 2583 2584
			};
		};

2585 2586 2587
		funnel@3025000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3025000 0x1000>;
2588

2589 2590
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2591

2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					merge_funnel_in0: endpoint {
						remote-endpoint =
						  <&funnel0_out>;
					};
				};

				port@1 {
					reg = <1>;
					merge_funnel_in1: endpoint {
						remote-endpoint =
						  <&funnel1_out>;
					};
				};

				port@2 {
					reg = <2>;
					merge_funnel_in2: endpoint {
						remote-endpoint =
						  <&funnel2_out>;
					};
				};
			};

			out-ports {
				port {
					merge_funnel_out: endpoint {
						remote-endpoint =
						  <&etf_in>;
					};
				};
			};
2629 2630
		};

2631 2632 2633
		replicator@3026000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x3026000 0x1000>;
2634

2635 2636
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2637

2638 2639 2640 2641 2642 2643 2644 2645
			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint =
						  <&etf_out>;
					};
				};
			};
2646

2647 2648 2649
			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;
2650

2651 2652 2653 2654 2655 2656 2657
				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint =
						  <&etr_in>;
					};
				};
2658

2659 2660 2661 2662 2663 2664 2665
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint =
						  <&tpiu_in>;
					};
				};
2666 2667 2668
			};
		};

2669 2670 2671
		etf@3027000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x3027000 0x1000>;
2672

2673 2674
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2675

2676 2677 2678 2679 2680 2681 2682
			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint =
						  <&merge_funnel_out>;
					};
				};
2683 2684
			};

2685 2686 2687 2688 2689 2690 2691
			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint =
						  <&replicator_in>;
					};
				};
2692
			};
2693
		};
2694

2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709
		etr@3028000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x3028000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,scatter-gather;

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint =
						  <&replicator_out0>;
					};
				};
2710
			};
2711 2712
		};

2713 2714 2715
		debug@3810000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3810000 0x1000>;
2716

2717 2718
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
2719

2720 2721
			cpu = <&CPU0>;
		};
2722

2723 2724 2725
		etm@3840000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3840000 0x1000>;
2726

2727 2728
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2729

2730
			cpu = <&CPU0>;
2731

2732 2733 2734 2735 2736 2737 2738
			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint =
						  <&apss_funnel0_in0>;
					};
				};
2739
			};
2740
		};
2741

2742 2743 2744
		debug@3910000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3910000 0x1000>;
2745

2746 2747
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
2748

2749 2750
			cpu = <&CPU1>;
		};
2751

2752 2753 2754
		etm@3940000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3940000 0x1000>;
2755

2756 2757
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2758

2759
			cpu = <&CPU1>;
2760

2761 2762 2763 2764 2765 2766 2767
			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint =
						  <&apss_funnel0_in1>;
					};
				};
2768 2769 2770
			};
		};

2771 2772 2773
		funnel@39b0000 { /* APSS Funnel 0 */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x39b0000 0x1000>;
2774

2775 2776
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2777

2778 2779 2780
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;
2781

2782 2783 2784 2785 2786 2787
				port@0 {
					reg = <0>;
					apss_funnel0_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
2788

2789 2790 2791 2792 2793 2794 2795
				port@1 {
					reg = <1>;
					apss_funnel0_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
			};
2796

2797 2798 2799 2800 2801 2802 2803 2804
			out-ports {
				port {
					apss_funnel0_out: endpoint {
						remote-endpoint =
						  <&apss_merge_funnel_in0>;
					};
				};
			};
2805
		};
2806

2807 2808 2809 2810 2811 2812 2813 2814 2815
		debug@3a10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3a10000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU2>;
		};
2816

2817 2818 2819
		etm@3a40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3a40000 0x1000>;
2820

2821 2822
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2823

2824
			cpu = <&CPU2>;
2825

2826 2827 2828 2829 2830 2831 2832
			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint =
						  <&apss_funnel1_in0>;
					};
				};
2833 2834 2835
			};
		};

2836 2837 2838
		debug@3b10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x3b10000 0x1000>;
2839

2840 2841
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
2842

2843 2844
			cpu = <&CPU3>;
		};
2845

2846 2847 2848
		etm@3b40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x3b40000 0x1000>;
2849

2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint =
						  <&apss_funnel1_in1>;
					};
				};
2862 2863
			};
		};
2864

2865 2866 2867
		funnel@3bb0000 { /* APSS Funnel 1 */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3bb0000 0x1000>;
2868

2869 2870
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2871

2872
			in-ports {
2873 2874
				#address-cells = <1>;
				#size-cells = <0>;
2875

2876 2877 2878 2879 2880 2881
				port@0 {
					reg = <0>;
					apss_funnel1_in0: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
2882

2883 2884 2885 2886 2887 2888 2889
				port@1 {
					reg = <1>;
					apss_funnel1_in1: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};
2890

2891 2892 2893 2894 2895 2896 2897 2898
			out-ports {
				port {
					apss_funnel1_out: endpoint {
						remote-endpoint =
						  <&apss_merge_funnel_in1>;
					};
				};
			};
2899 2900
		};

2901 2902 2903
		funnel@3bc0000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x3bc0000 0x1000>;
2904

2905 2906
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
2907

2908 2909 2910
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;
2911

2912 2913 2914 2915 2916 2917 2918
				port@0 {
					reg = <0>;
					apss_merge_funnel_in0: endpoint {
						remote-endpoint =
						  <&apss_funnel0_out>;
					};
				};
2919

2920 2921 2922 2923 2924 2925 2926 2927
				port@1 {
					reg = <1>;
					apss_merge_funnel_in1: endpoint {
						remote-endpoint =
						  <&apss_funnel1_out>;
					};
				};
			};
2928

2929 2930 2931 2932 2933 2934 2935 2936 2937
			out-ports {
				port {
					apss_merge_funnel_out: endpoint {
						remote-endpoint =
						  <&funnel1_in>;
					};
				};
			};
		};
2938

2939
		kryocc: clock-controller@6400000 {
2940
			compatible = "qcom,msm8996-apcc";
2941
			reg = <0x06400000 0x90000>;
2942 2943

			clock-names = "xo";
2944
			clocks = <&rpmcc RPM_SMD_BB_CLK1>;
2945

2946
			#clock-cells = <1>;
2947 2948
		};

2949 2950 2951
		usb3: usb@6af8800 {
			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
			reg = <0x06af8800 0x400>;
2952 2953 2954 2955
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

2956 2957 2958 2959
			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "ss_phy_irq";

2960
			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2961 2962 2963 2964 2965 2966 2967 2968 2969
				 <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";
2970

2971 2972 2973
			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <120000000>;
2974

2975 2976 2977 2978
			interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
					<&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
			interconnect-names = "usb-ddr", "apps-usb";

2979 2980
			power-domains = <&gcc USB30_GDSC>;
			status = "disabled";
2981

2982
			usb3_dwc3: usb@6a00000 {
2983 2984 2985 2986 2987 2988 2989 2990 2991
				compatible = "snps,dwc3";
				reg = <0x06a00000 0xcc00>;
				interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hsusb_phy1>, <&ssusb_phy_0>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
			};
		};
2992

2993 2994 2995 2996 2997 2998
		usb3phy: phy@7410000 {
			compatible = "qcom,msm8996-qmp-usb3-phy";
			reg = <0x07410000 0x1c4>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
2999

3000 3001 3002 3003
			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_USB3_CLKREF_CLK>;
			clock-names = "aux", "cfg_ahb", "ref";
3004

3005 3006 3007 3008
			resets = <&gcc GCC_USB3_PHY_BCR>,
				<&gcc GCC_USB3PHY_PHY_BCR>;
			reset-names = "phy", "common";
			status = "disabled";
3009

3010
			ssusb_phy_0: phy@7410200 {
3011 3012 3013 3014
				reg = <0x07410200 0x200>,
				      <0x07410400 0x130>,
				      <0x07410600 0x1a8>;
				#phy-cells = <0>;
3015

3016
				#clock-cells = <0>;
3017 3018 3019
				clock-output-names = "usb3_phy_pipe_clk_src";
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
3020
			};
3021
		};
3022

3023 3024 3025 3026
		hsusb_phy1: phy@7411000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x07411000 0x180>;
			#phy-cells = <0>;
3027

3028 3029 3030
			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";
3031

3032 3033 3034 3035
			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
			nvmem-cells = <&qusb2p_hstx_trim>;
			status = "disabled";
		};
3036

3037 3038 3039 3040
		hsusb_phy2: phy@7412000 {
			compatible = "qcom,msm8996-qusb2-phy";
			reg = <0x07412000 0x180>;
			#phy-cells = <0>;
3041

3042 3043 3044
			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				<&gcc GCC_RX2_USB2_CLKREF_CLK>;
			clock-names = "cfg_ahb", "ref";
3045

3046 3047 3048 3049
			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
			nvmem-cells = <&qusb2s_hstx_trim>;
			status = "disabled";
		};
3050

3051
		sdhc1: mmc@7464900 {
3052
			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3053
			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3054
			reg-names = "hc", "core";
3055 3056 3057 3058 3059 3060 3061 3062

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clock-names = "iface", "core", "xo";
			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				<&gcc GCC_SDCC1_APPS_CLK>,
3063
				<&rpmcc RPM_SMD_BB_CLK1>;
3064
			resets = <&gcc GCC_SDCC1_BCR>;
3065 3066 3067 3068 3069 3070 3071 3072 3073 3074

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc1_state_on>;
			pinctrl-1 = <&sdc1_state_off>;

			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

3075
		sdhc2: mmc@74a4900 {
3076
			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3077
			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3078
			reg-names = "hc", "core";
3079 3080 3081 3082 3083 3084 3085 3086

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clock-names = "iface", "core", "xo";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				<&gcc GCC_SDCC2_APPS_CLK>,
3087
				<&rpmcc RPM_SMD_BB_CLK1>;
3088
			resets = <&gcc GCC_SDCC2_BCR>;
3089 3090 3091 3092 3093 3094 3095

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc2_state_on>;
			pinctrl-1 = <&sdc2_state_off>;

			bus-width = <4>;
			status = "disabled";
3096 3097
		 };

3098
		blsp1_dma: dma-controller@7544000 {
3099 3100 3101 3102 3103 3104 3105 3106 3107 3108
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07544000 0x2b000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			qcom,controlled-remotely;
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

3109
		blsp1_uart2: serial@7570000 {
3110 3111 3112 3113 3114 3115
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x07570000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
3116 3117 3118
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart2_default>;
			pinctrl-1 = <&blsp1_uart2_sleep>;
3119 3120
			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
			dma-names = "tx", "rx";
3121 3122 3123
			status = "disabled";
		};

3124
		blsp1_spi1: spi@7575000 {
3125 3126 3127 3128 3129 3130 3131
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x07575000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
3132 3133
			pinctrl-0 = <&blsp1_spi1_default>;
			pinctrl-1 = <&blsp1_spi1_sleep>;
3134 3135
			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
			dma-names = "tx", "rx";
3136 3137 3138 3139
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
3140

3141
		blsp1_i2c3: i2c@7577000 {
3142 3143 3144
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x07577000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3145 3146 3147
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
3148
			pinctrl-names = "default", "sleep";
3149 3150
			pinctrl-0 = <&blsp1_i2c3_default>;
			pinctrl-1 = <&blsp1_i2c3_sleep>;
3151 3152
			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
			dma-names = "tx", "rx";
3153 3154 3155 3156
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
3157

3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174
		blsp1_i2c6: i2c@757a000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x757a000 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c6_default>;
			pinctrl-1 = <&blsp1_i2c6_sleep>;
			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

3175
		blsp2_dma: dma-controller@7584000 {
3176 3177 3178 3179 3180 3181 3182 3183 3184 3185
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07584000 0x2b000>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "bam_clk";
			qcom,controlled-remotely;
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

3186
		blsp2_uart2: serial@75b0000 {
3187 3188 3189 3190 3191 3192 3193 3194
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x075b0000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};
3195

3196
		blsp2_uart3: serial@75b1000 {
3197 3198 3199 3200 3201 3202 3203 3204
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x075b1000 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};
3205

3206
		blsp2_i2c1: i2c@75b5000 {
3207 3208 3209
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b5000 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3210 3211 3212
			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
3213
			pinctrl-names = "default", "sleep";
3214 3215
			pinctrl-0 = <&blsp2_i2c1_default>;
			pinctrl-1 = <&blsp2_i2c1_sleep>;
3216 3217
			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
			dma-names = "tx", "rx";
3218 3219 3220 3221
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
3222

3223
		blsp2_i2c2: i2c@75b6000 {
3224 3225 3226
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b6000 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3227 3228 3229
			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
3230
			pinctrl-names = "default", "sleep";
3231 3232
			pinctrl-0 = <&blsp2_i2c2_default>;
			pinctrl-1 = <&blsp2_i2c2_sleep>;
3233 3234
			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
			dma-names = "tx", "rx";
3235 3236 3237 3238
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
3239

3240 3241 3242 3243
		blsp2_i2c3: i2c@75b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b7000 0x1000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3244 3245 3246
			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c3_default>;
			pinctrl-1 = <&blsp2_i2c3_sleep>;
			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
			dma-names = "tx", "rx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

3258 3259 3260 3261
		blsp2_i2c5: i2c@75b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x75b9000 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3262 3263 3264
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
3265 3266
			pinctrl-names = "default";
			pinctrl-0 = <&blsp2_i2c5_default>;
3267 3268
			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
			dma-names = "tx", "rx";
3269 3270 3271 3272 3273 3274 3275 3276 3277
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_i2c6: i2c@75ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x75ba000 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3278 3279 3280
			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
3281 3282 3283
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c6_default>;
			pinctrl-1 = <&blsp2_i2c6_sleep>;
3284 3285
			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
			dma-names = "tx", "rx";
3286 3287 3288 3289 3290
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

3291
		blsp2_spi6: spi@75ba000{
3292 3293 3294 3295 3296 3297 3298
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x075ba000 0x600>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default", "sleep";
3299 3300
			pinctrl-0 = <&blsp2_spi6_default>;
			pinctrl-1 = <&blsp2_spi6_sleep>;
3301 3302
			dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
			dma-names = "tx", "rx";
3303 3304 3305 3306
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
3307

3308 3309 3310 3311 3312 3313
		usb2: usb@76f8800 {
			compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
			reg = <0x076f8800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
3314

3315 3316 3317 3318 3319
			clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
				<&gcc GCC_USB20_MASTER_CLK>,
				<&gcc GCC_USB20_MOCK_UTMI_CLK>,
				<&gcc GCC_USB20_SLEEP_CLK>,
				<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3320 3321 3322 3323 3324
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";
3325

3326 3327 3328
			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB20_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <60000000>;
3329

3330
			power-domains = <&gcc USB30_GDSC>;
3331
			qcom,select-utmi-as-pipe-clk;
3332
			status = "disabled";
3333

3334
			usb2_dwc3: usb@7600000 {
3335 3336 3337 3338 3339
				compatible = "snps,dwc3";
				reg = <0x07600000 0xcc00>;
				interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hsusb_phy2>;
				phy-names = "usb2-phy";
3340
				maximum-speed = "high-speed";
3341 3342
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
3343 3344
			};
		};
3345

3346
		slimbam: dma-controller@9184000 {
3347 3348
			compatible = "qcom,bam-v1.7.0";
			qcom,controlled-remotely;
3349
			reg = <0x09184000 0x32000>;
3350
			num-channels = <31>;
3351 3352 3353 3354 3355 3356
			interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,num-ees = <2>;
		};

3357
		slim_msm: slim-ngd@91c0000 {
3358
			compatible = "qcom,slim-ngd-v1.5.0";
3359
			reg = <0x091c0000 0x2C000>;
3360
			interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3361 3362
			dmas = <&slimbam 3>, <&slimbam 4>;
			dma-names = "rx", "tx";
3363 3364
			#address-cells = <1>;
			#size-cells = <0>;
3365
			slim@1 {
3366
				reg = <1>;
3367 3368
				#address-cells = <2>;
				#size-cells = <0>;
3369

3370
				tasha_ifd: tas-ifd@0,0 {
3371
					compatible = "slim217,1a0";
3372
					reg = <0 0>;
3373 3374
				};

3375
				wcd9335: codec@1,0 {
3376 3377
					pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
					pinctrl-names = "default";
3378

3379
					compatible = "slim217,1a0";
3380
					reg = <1 0>;
3381

3382
					interrupt-parent = <&tlmm>;
3383 3384
					interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
						     <53 IRQ_TYPE_LEVEL_HIGH>;
3385
					interrupt-names = "intr1", "intr2";
3386 3387
					interrupt-controller;
					#interrupt-cells = <1>;
3388
					reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
3389

3390
					slim-ifc-dev = <&tasha_ifd>;
3391

3392 3393 3394 3395
					#sound-dai-cells = <1>;
				};
			};
		};
3396

3397 3398 3399
		adsp_pil: remoteproc@9300000 {
			compatible = "qcom,msm8996-adsp-pil";
			reg = <0x09300000 0x80000>;
3400

3401
			interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3402 3403 3404 3405
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3406 3407
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";
3408

3409
			clocks = <&rpmcc RPM_SMD_BB_CLK1>;
3410
			clock-names = "xo";
3411

3412
			memory-region = <&adsp_mem>;
3413

3414
			qcom,smem-states = <&adsp_smp2p_out 0>;
3415
			qcom,smem-state-names = "stop";
3416

3417 3418 3419 3420 3421
			power-domains = <&rpmpd MSM8996_VDDCX>;
			power-domain-names = "cx";

			status = "disabled";

3422 3423
			smd-edge {
				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3424

3425 3426 3427 3428 3429 3430 3431 3432 3433 3434
				label = "lpass";
				mboxes = <&apcs_glb 8>;
				qcom,smd-edge = <1>;
				qcom,remote-pid = <2>;
				#address-cells = <1>;
				#size-cells = <0>;
				apr {
					power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
					compatible = "qcom,apr-v2";
					qcom,smd-channels = "apr_audio_svc";
3435
					qcom,domain = <APR_DOMAIN_ADSP>;
3436 3437 3438
					#address-cells = <1>;
					#size-cells = <0>;

3439
					service@3 {
3440 3441 3442 3443
						reg = <APR_SVC_ADSP_CORE>;
						compatible = "qcom,q6core";
					};

3444
					q6afe: service@4 {
3445 3446 3447 3448 3449 3450 3451
						compatible = "qcom,q6afe";
						reg = <APR_SVC_AFE>;
						q6afedai: dais {
							compatible = "qcom,q6afe-dais";
							#address-cells = <1>;
							#size-cells = <0>;
							#sound-dai-cells = <1>;
3452
							dai@1 {
3453 3454
								reg = <1>;
							};
3455 3456 3457
						};
					};

3458
					q6asm: service@7 {
3459 3460 3461 3462
						compatible = "qcom,q6asm";
						reg = <APR_SVC_ASM>;
						q6asmdai: dais {
							compatible = "qcom,q6asm-dais";
3463 3464
							#address-cells = <1>;
							#size-cells = <0>;
3465 3466 3467 3468
							#sound-dai-cells = <1>;
							iommus = <&lpass_q6_smmu 1>;
						};
					};
3469

3470
					q6adm: service@8 {
3471 3472 3473 3474 3475 3476 3477 3478
						compatible = "qcom,q6adm";
						reg = <APR_SVC_ADM>;
						q6routing: routing {
							compatible = "qcom,q6adm-routing";
							#sound-dai-cells = <0>;
						};
					};
				};
3479

3480 3481
			};
		};
3482

3483 3484 3485
		apcs_glb: mailbox@9820000 {
			compatible = "qcom,msm8996-apcs-hmss-global";
			reg = <0x09820000 0x1000>;
3486

3487 3488
			#mbox-cells = <1>;
		};
3489

3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503
		timer@9840000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x09840000 0x1000>;
			clock-frequency = <19200000>;

			frame@9850000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09850000 0x1000>,
				      <0x09860000 0x1000>;
3504 3505
			};

3506 3507 3508 3509 3510 3511
			frame@9870000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09870000 0x1000>;
				status = "disabled";
			};
3512

3513 3514 3515 3516 3517
			frame@9880000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09880000 0x1000>;
				status = "disabled";
3518
			};
3519

3520 3521 3522 3523 3524 3525
			frame@9890000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09890000 0x1000>;
				status = "disabled";
			};
3526

3527 3528 3529 3530 3531 3532
			frame@98a0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098a0000 0x1000>;
				status = "disabled";
			};
3533

3534 3535 3536 3537 3538
			frame@98b0000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098b0000 0x1000>;
				status = "disabled";
3539 3540
			};

3541 3542 3543 3544 3545
			frame@98c0000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098c0000 0x1000>;
				status = "disabled";
3546 3547
			};
		};
3548

3549
		saw3: syscon@9a10000 {
3550
			compatible = "syscon";
3551 3552 3553
			reg = <0x09a10000 0x1000>;
		};

3554 3555 3556 3557 3558 3559 3560 3561 3562 3563
		intc: interrupt-controller@9bc0000 {
			compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x09bc0000 0x10000>,
			      <0x09c00000 0x100000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};
3564
	};
3565

3566 3567 3568
	sound: sound {
	};

3569 3570 3571 3572
	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3573

3574
			thermal-sensors = <&tsens0 3>;
3575

3576
			trips {
3577
				cpu0_alert0: trip-point0 {
3578 3579 3580 3581
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
3582

3583 3584 3585 3586 3587 3588 3589
				cpu0_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
3590

3591 3592 3593
		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3594

3595
			thermal-sensors = <&tsens0 5>;
3596

3597
			trips {
3598
				cpu1_alert0: trip-point0 {
3599 3600 3601 3602
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
3603

3604 3605 3606 3607
				cpu1_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
3608
				};
3609 3610
			};
		};
3611

3612 3613 3614 3615 3616 3617 3618
		cpu2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 8>;

			trips {
3619
				cpu2_alert0: trip-point0 {
3620 3621 3622
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
3623 3624
				};

3625 3626 3627 3628
				cpu2_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
3629 3630
				};
			};
3631 3632 3633 3634 3635 3636 3637 3638 3639
		};

		cpu3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens0 10>;

			trips {
3640
				cpu3_alert0: trip-point0 {
3641 3642 3643 3644
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
3645

3646 3647 3648 3649 3650 3651
				cpu3_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
3652
		};
3653

3654
		gpu-top-thermal {
3655 3656
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3657

3658
			thermal-sensors = <&tsens1 6>;
3659

3660
			trips {
3661
				gpu1_alert0: trip-point0 {
3662 3663
					temperature = <90000>;
					hysteresis = <2000>;
3664 3665 3666 3667 3668 3669 3670 3671
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu1_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3672 3673 3674
				};
			};
		};
3675

3676
		gpu-bottom-thermal {
3677 3678
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3679

3680 3681 3682
			thermal-sensors = <&tsens1 7>;

			trips {
3683
				gpu2_alert0: trip-point0 {
3684 3685
					temperature = <90000>;
					hysteresis = <2000>;
3686 3687 3688 3689 3690 3691 3692 3693
					type = "passive";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu2_alert0>;
					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3694 3695
				};
			};
3696 3697
		};

3698 3699 3700
		m4m-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3701

3702 3703 3704
			thermal-sensors = <&tsens0 1>;

			trips {
3705
				m4m_alert0: trip-point0 {
3706 3707 3708 3709 3710
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
3711
		};
3712

3713 3714 3715
		l3-or-venus-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3716

3717
			thermal-sensors = <&tsens0 2>;
3718

3719
			trips {
3720
				l3_or_venus_alert0: trip-point0 {
3721 3722 3723 3724 3725 3726
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};
3727

3728 3729 3730
		cluster0-l2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3731

3732 3733 3734
			thermal-sensors = <&tsens0 7>;

			trips {
3735
				cluster0_l2_alert0: trip-point0 {
3736 3737 3738 3739 3740
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
3741 3742
		};

3743 3744 3745
		cluster1-l2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3746

3747 3748 3749
			thermal-sensors = <&tsens0 12>;

			trips {
3750
				cluster1_l2_alert0: trip-point0 {
3751 3752 3753 3754 3755
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
3756 3757
		};

3758 3759 3760
		camera-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3761

3762
			thermal-sensors = <&tsens1 1>;
3763

3764
			trips {
3765
				camera_alert0: trip-point0 {
3766 3767 3768 3769 3770 3771
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};
3772

3773 3774 3775
		q6-dsp-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
3776

3777 3778 3779
			thermal-sensors = <&tsens1 2>;

			trips {
3780
				q6_dsp_alert0: trip-point0 {
3781 3782 3783 3784 3785
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
3786 3787
		};

3788 3789 3790 3791 3792 3793 3794
		mem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 3>;

			trips {
3795
				mem_alert0: trip-point0 {
3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		modemtx-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens1 4>;

			trips {
3810
				modemtx_alert0: trip-point0 {
3811 3812 3813 3814 3815
					temperature = <90000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
3816 3817 3818
		};
	};

3819 3820 3821 3822 3823 3824 3825
	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
3826
};