What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_presentWhat: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_presentWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_presentWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_presentWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_presentWhat: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_presentKernelVersion: 3.4.0Contact: linux-iio@vger.kernel.orgDescription: Reading returns either '1' or '0'. '1' means that the clock in question is present. '0' means that the clock is missing.What: /sys/bus/iio/devices/iio:deviceX/pllY_lockedKernelVersion: 3.4.0Contact: linux-iio@vger.kernel.orgDescription: Reading returns either '1' or '0'. '1' means that the pllY is locked.What: /sys/bus/iio/devices/iio:deviceX/sync_dividersKernelVersion: 3.4.0Contact: linux-iio@vger.kernel.orgDescription: Writing '1' triggers the clock distribution synchronization functionality. All dividers are reset and the channels start with their predefined phase offsets (out_altvoltageY_phase). Writing this file has the effect as driving the external /SYNC pin low.