• Conor Dooley's avatar
    RISC-V: take text_mutex during alternative patching · 9493e6f3
    Conor Dooley authored
    Guenter reported a splat during boot, that Samuel pointed out was the
    lockdep assertion failing in patch_insn_write():
    
    WARNING: CPU: 0 PID: 0 at arch/riscv/kernel/patch.c:63 patch_insn_write+0x222/0x2f6
    epc : patch_insn_write+0x222/0x2f6
     ra : patch_insn_write+0x21e/0x2f6
    epc : ffffffff800068c6 ra : ffffffff800068c2 sp : ffffffff81803df0
     gp : ffffffff81a1ab78 tp : ffffffff81814f80 t0 : ffffffffffffe000
     t1 : 0000000000000001 t2 : 4c45203a76637369 s0 : ffffffff81803e40
     s1 : 0000000000000004 a0 : 0000000000000000 a1 : ffffffffffffffff
     a2 : 0000000000000004 a3 : 0000000000000000 a4 : 0000000000000001
     a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000052464e43
     s2 : ffffffff80b4889c s3 : 000000000000082c s4 : ffffffff80b48828
     s5 : 0000000000000828 s6 : ffffffff8131a0a0 s7 : 0000000000000fff
     s8 : 0000000008000200 s9 : ffffffff8131a520 s10: 0000000000000018
     s11: 000000000000000b t3 : 0000000000000001 t4 : 000000000000000d
     t5 : ffffffffd8180000 t6 : ffffffff81803bc8
    status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
    [<ffffffff800068c6>] patch_insn_write+0x222/0x2f6
    [<ffffffff80006a36>] patch_text_nosync+0xc/0x2a
    [<ffffffff80003b86>] riscv_cpufeature_patch_func+0x52/0x98
    [<ffffffff80003348>] _apply_alternatives+0x46/0x86
    [<ffffffff80c02d36>] apply_boot_alternatives+0x3c/0xfa
    [<ffffffff80c03ad8>] setup_arch+0x584/0x5b8
    [<ffffffff80c0075a>] start_kernel+0xa2/0x8f8
    
    This issue was exposed by 702e6455 ("riscv: fpu: switch has_fpu() to
    riscv_has_extension_likely()"), as it is the patching in has_fpu() that
    triggers the splats in Guenter's report.
    
    Take the text_mutex before doing any code patching to satisfy lockdep.
    
    Fixes: ff689fd2 ("riscv: add RISC-V Svpbmt extension support")
    Fixes: a35707c3 ("riscv: add memory-type errata for T-Head")
    Fixes: 1a0e5dbd ("riscv: sifive: Add SiFive alternative ports")
    Reported-by: default avatarGuenter Roeck <linux@roeck-us.net>
    Link: https://lore.kernel.org/all/20230212154333.GA3760469@roeck-us.net/Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
    Reviewed-by: default avatarSamuel Holland <samuel@sholland.org>
    Tested-by: default avatarGuenter Roeck <linux@roeck-us.net>
    Link: https://lore.kernel.org/r/20230212194735.491785-1-conor@kernel.org
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
    9493e6f3
cpufeature.c 7.56 KB