• Tudor Ambarus's avatar
    clk: samsung: gs101: propagate PERIC0 USI SPI clock rate · 7b54d911
    Tudor Ambarus authored
    Introduce nMUX() for MUX clocks that can be reparented on clock rate
    change. "nMUX" comes from "n-to-1 selector", hopefully emphasising that
    the selector can change on clock rate changes. Ideally MUX/MUX_F()
    should change to not have the CLK_SET_RATE_NO_REPARENT flag set by
    default, and all their users to be updated to add the flag back
    (like in the case of DIV and GATE). But this is a very intrusive change
    and because for now only GS101 allows MUX reparenting on clock rate
    change, stick with nMUX().
    
    GS101 defines MUX clocks that are dedicated for each instance of the IP.
    One example is USI IP (SPI, I2C, serial). The reparenting of these MUX
    clocks will not affect other instances of the same IP or different IPs
    altogether.
    
    When SPI transfer is being prepared, the spi-s3c64xx driver will call
    clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
    is a gate (leaf) clock, so it must propagate the rate change up the
    clock tree, so that corresponding MUX/DIV clocks can actually change
    their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
    all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the
    following clocks:
    
    PERIC0 USI*:
    
        Clock                              Div range    MUX Selection
        -------------------------------------------------------------------
        gout_peric0_peric0_top0_ipclk_*    -            -
        dout_peric0_usi*_usi               /1..16       -
        mout_peric0_usi*_usi_user          -            {24.5 MHz, 400 MHz}
    
    With input clock of 400 MHz this scheme provides the following IPCLK
    rate range, for each USI block:
    
        PERIC0 USI*:       1.5 MHz ... 400 MHz
    
    Accounting for internal /4 divider in SPI blocks, and because the max
    SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
    
        PERIC0 USI_SPI*:   384 KHz ... 49.9 MHz
    
    Fixes: 893f133a ("clk: samsung: gs101: add support for cmu_peric0")
    Reviewed-by: default avatarPeter Griffin <peter.griffin@linaro.org>
    Acked-by: default avatarAndré Draszik <andre.draszik@linaro.org>
    Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
    Link: https://lore.kernel.org/r/20240419100915.2168573-2-tudor.ambarus@linaro.orgSigned-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    7b54d911
clk.h 12.9 KB