• Paul Walmsley's avatar
    ARM: OMAP3: PM: apply part of the erratum i582 workaround · 856c3c5b
    Paul Walmsley authored
    On OMAP34xx/35xx, and OMAP36xx chips with ES < 1.2, if the PER
    powerdomain goes to OSWR or OFF while CORE stays at CSWR or ON, or if,
    upon chip wakeup from OSWR or OFF, the CORE powerdomain goes ON before
    PER, the UART3/4 FIFOs and McBSP2/3 SIDETONE memories will be
    unusable.  This is erratum i582 in the OMAP36xx Silicon Errata
    document.
    
    This patch implements one of several parts of the workaround: the
    addition of the wakeup dependency between the PER and WKUP
    clockdomains, such that PER will wake up at the same time CORE_L3
    does.
    
    This is not a complete workaround.  For it to be complete:
    
    1. the PER powerdomain's next power state must not be set to OSWR or
       OFF if the CORE powerdomain's next power state is set to CSWR or
       ON;
    
    2. the UART3/4 FIFO and McBSP2/3 SIDETONE loopback tests should be run
       if the LASTPOWERSTATEENTERED bits for PER and CORE indicate that
       PER went OFF while CORE stayed on.  If loopback tests fail, then
       those devices will be unusable until PER and CORE can undergo a
       transition from ON to OSWR/OFF and back ON.
    Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
    Cc: Tero Kristo <t-kristo@ti.com>
    Cc: Kevin Hilman <khilman@ti.com>
    Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
    856c3c5b
pm34xx.c 21.7 KB