• Chris Metcalf's avatar
    arch/tile: support 4KB page size as well as 64KB · 76c567fb
    Chris Metcalf authored
    The Tilera architecture traditionally supports 64KB page sizes
    to improve TLB utilization and improve performance when the
    hardware is being used primarily to run a single application.
    
    For more generic server scenarios, it can be beneficial to run
    with 4KB page sizes, so this commit allows that to be specified
    (by modifying the arch/tile/include/hv/pagesize.h header).
    
    As part of this change, we also re-worked the PTE management
    slightly so that PTE writes all go through a __set_pte() function
    where we can do some additional validation.  The set_pte_order()
    function was eliminated since the "order" argument wasn't being used.
    
    One bug uncovered was in the PCI DMA code, which wasn't properly
    flushing the specified range.  This was benign with 64KB pages,
    but with 4KB pages we were getting some larger flushes wrong.
    
    The per-cpu memory reservation code also needed updating to
    conform with the newer percpu stuff; before it always chose 64KB,
    and that was always correct, but with 4KB granularity we now have
    to pay closer attention and reserve the amount of memory that will
    be requested when the percpu code starts allocating.
    Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    76c567fb
pgalloc.h 3.71 KB