• Chris Wilson's avatar
    drm/i915: Use SSE4.1 movntdqa to accelerate reads from WC memory · 0b1de5d5
    Chris Wilson authored
    This patch provides the infrastructure for performing a 16-byte aligned
    read from WC memory using non-temporal instructions introduced with sse4.1.
    Using movntdqa we can bypass the CPU caches and read directly from memory
    and ignoring the page attributes set on the CPU PTE i.e. negating the
    impact of an otherwise UC access. Copying using movntdqa from WC is almost
    as fast as reading from WB memory, modulo the possibility of both hitting
    the CPU cache or leaving the data in the CPU cache for the next consumer.
    (The CPU cache itself my be flushed for the region of the movntdqa and on
    later access the movntdqa reads from a separate internal buffer for the
    cacheline.) The write back to the memory is however cached.
    
    This will be used in later patches to accelerate accessing WC memory.
    
    v2: Report whether the accelerated copy is successful/possible.
    v3: Function alignment override was only necessary when using the
    function target("sse4.1") - which is not necessary for emitting movntdqa
    from __asm__.
    v4: Improve notes on CPU cache behaviour vs non-temporal stores.
    v5: Fix byte offsets for unrolled moves.
    v6: Find all remaining typos of "movntqda", use kernel_fpu_begin.
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Cc: Akash Goel <akash.goel@intel.com>
    Cc: Damien Lespiau <damien.lespiau@intel.com>
    Cc: Mika Kuoppala <mika.kuoppala@intel.com>
    Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1471001999-17787-2-git-send-email-chris@chris-wilson.co.uk
    0b1de5d5
i915_memcpy.c 2.94 KB