This has been given basic testing on Power4 pSeries and iSeries machines.

At present, the SLB miss handler has to check the SLB slot it is about to
use to ensure that it does not contain the SLBE for the current kernel
stack - throwing out the SLBE for the kernel stack can trigger the
"megabug": we have no SLBE for the stack, but we don't fault immediately
because we have an ERAT entry for it.  The ERAT entry is then lost due to a
tlbie on another CPU during the unrecoverable section of the exception
return path.

This patch implements a different approach - with this patch SLB slot 2
always (well, nearly always) contains an SLBE for the stack.  This slot is
never cast out by the normal SLB miss path.  On context switch, an SLBE for
the new stack is pinned into this slot, unless the new stack is the the
bolted segment.

For iSeries we need a special workaround because there is no way of
ensuring the stack SLBE is preserved an a shared processor switch.  So, we
still need to handle taking an SLB miss on the stack, in which case we must
make sure it is loaded into slot 2, rather than using the normal
round-robin.

This approach shaves a few ns off the slb miss time (on pSeries), but more
importantly makes it easier to experiment with different SLB castout
aporoaches without worrying about reinstating the megabug.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>