• Peter Zijlstra's avatar
    mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush · 0ed13259
    Peter Zijlstra authored
    Architectures for which we have hardware walkers of Linux page table
    should flush TLB on mmu gather batch allocation failures and batch flush.
    Some architectures like POWER supports multiple translation modes (hash
    and radix) and in the case of POWER only radix translation mode needs the
    above TLBI.  This is because for hash translation mode kernel wants to
    avoid this extra flush since there are no hardware walkers of linux page
    table.  With radix translation, the hardware also walks linux page table
    and with that, kernel needs to make sure to TLB invalidate page walk cache
    before page table pages are freed.
    
    More details in commit d86564a2 ("mm/tlb, x86/mm: Support invalidating
    TLB caches for RCU_TABLE_FREE")
    
    The changes to sparc are to make sure we keep the old behavior since we
    are now removing HAVE_RCU_TABLE_NO_INVALIDATE.  The default value for
    tlb_needs_table_invalidate is to always force an invalidate and sparc can
    avoid the table invalidate.  Hence we define tlb_needs_table_invalidate to
    false for sparc architecture.
    
    Link: http://lkml.kernel.org/r/20200116064531.483522-3-aneesh.kumar@linux.ibm.com
    Fixes: a46cc7a9 ("powerpc/mm/radix: Improve TLB/PWC flushes")
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org
    Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
    Acked-by: Michael Ellerman <mpe@ellerman.id.au>	[powerpc]
    Cc: <stable@vger.kernel.org>	[4.14+]
    Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    0ed13259
mmu_gather.c 6.69 KB