• Andre Przywara's avatar
    net: axienet: Allow DMA to beyond 4GB · 5fff0151
    Andre Przywara authored
    With all DMA address accesses wrapped, we can actually support 64-bit
    DMA if this option was chosen at IP integration time.
    If the IP has been configured for an address width greater than 32 bits,
    we assume the full 64 bit DMA width is working. In practise this will be
    limited by the actual system address bus width, which will ideally be the
    same as the DMA IP address width.
    If this is not the case, the actual width can still be configured using a
    dma-ranges property in the parent of the MAC node.
    
    This increases the DMA mask on those systems to let the kernel choose
    buffers from memory at higher addresses.
    Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    5fff0151
xilinx_axienet_main.c 60.6 KB