• Lennert Buytenhek's avatar
    mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface · 81600eea
    Lennert Buytenhek authored
    The mv643xx_eth hardware has a provision for polling the PHY's
    MII management registers to obtain the (R)(G)MII interface speed
    (10/100/1000) and duplex (half/full) and pause (off/symmetric)
    settings to use to talk to the PHY.
    
    The driver currently does not make use of this feature.  Instead,
    whenever there is a link status change event, it reads the current
    link parameters from the PHY, and programs those parameters into
    the mv643xx_eth MAC by hand.
    
    This patch switches the mv643xx_eth driver to letting the MAC
    auto-determine the (R)(G)MII link parameters by PHY polling, if there
    is a PHY present.  For PHYless ports (when e.g. the (R)(G)MII
    interface is connected to a hardware switch), we keep hardcoding the
    MII interface parameters.
    Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
    81600eea
rd88f5181l-fxo-setup.c 4.56 KB