• Huacai Chen's avatar
    LoongArch: Make WriteCombine configurable for ioremap() · 16c52e50
    Huacai Chen authored
    LoongArch maintains cache coherency in hardware, but when paired with
    LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar
    to WriteCombine) is out of the scope of cache coherency machanism for
    PCIe devices (this is a PCIe protocol violation, which may be fixed in
    newer chipsets).
    
    This means WUC can only used for write-only memory regions now, so this
    option is disabled by default, making WUC silently fallback to SUC for
    ioremap(). You can enable this option if the kernel is ensured to run on
    hardware without this bug.
    
    Kernel parameter writecombine=on/off can be used to override the Kconfig
    option.
    
    Cc: stable@vger.kernel.org
    Suggested-by: default avatarWANG Xuerui <kernel@xen0n.name>
    Reviewed-by: default avatarWANG Xuerui <kernel@xen0n.name>
    Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
    16c52e50
setup.c 14.8 KB