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Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>