This patch adds mt8195 tdm/i2s dai driver.

MCLK clock tree is as follows.
PLL -> MUX -> DIVIDER -> MCLK

For PLL source of MCLK, driver only supports APLL1 and APLL2 now.
APLL3 and APLL4 are used to track external clock source, so they are
only used when slave input is connected.

For example,
case 1: (HDMI RX connected)
DL memif (a1sys) -> etdm out2 (clk from apll1/apll2) -> codec
case 2: (HDMI RX disconnected)
HDMI RX -> a3sys -> UL memif (a3sys) -> DL memif (a3sys) -> .... ->
etdm out2 (clk from apll3) -> codec

We keep all modules in the pipeline working on the same clock domain.
MCLK is expected to output the clock generated from the same clock
source as the pipeline, so dynamic reparenting is required for MCLK
configuration.

As a result, clk_set_parent() is used to select PLL source,
and clk_set_rate() is used to configure divider to get MCLK output rate.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://lore.kernel.org/r/20210819084144.18483-4-trevor.wu@mediatek.comSigned-off-by: Mark Brown <broonie@kernel.org>