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Claudiu Beznea authored
The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with id 49. Fixes: 1e5f532c ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20221208115241.36312-1-claudiu.beznea@microchip.com
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