• Kan Liang's avatar
    perf/x86/intel/uncore: Add Ice Lake server uncore support · 2b3b76b5
    Kan Liang authored
    The uncore subsystem in Ice Lake server is similar to previous server.
    There are some differences in config register encoding and pci device
    IDs. The uncore PMON units in Ice Lake server include Ubox, Chabox, IIO,
    IRP, M2PCIE, PCU, M2M, PCIE3 and IMC.
    
     - For CHA, filter 1 register has been removed. The filter 0 register can
       be used by and of CHA events to be filterd by Thread/Core-ID. To do
       so, the control register's tid_en bit must be set to 1.
     - For IIO, there are some changes on event constraints. The MSR address
       and MSR offsets among counters are also changed.
     - For IRP, the MSR address and MSR offsets among counters are changed.
     - For M2PCIE, the counters are accessed by MSR now. Add new MSR address
       and MSR offsets. Change event constraints.
     - To determine the number of CHAs, have to read CAPID6(Low) and CAPID7
       (High) now.
     - For M2M, update the PCICFG address and Device ID.
     - For UPI, update the PCICFG address, Device ID and counter address.
     - For M3UPI, update the PCICFG address, Device ID, counter address and
       event constraints.
     - For IMC, update the formular to calculate MMIO BAR address, which is
       MMIO_BASE + specific MEM_BAR offset.
    Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
    Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
    Link: https://lkml.kernel.org/r/1585842411-150452-1-git-send-email-kan.liang@linux.intel.com
    2b3b76b5
uncore_snbep.c 153 KB