• Bailey Forrest's avatar
    gve: Add dqo descriptors · 22319818
    Bailey Forrest authored
    General description of rings and descriptors:
    
    TX ring is used for sending TX packet buffers to the NIC. It has the
    following descriptors:
    - `gve_tx_pkt_desc_dqo` - Data buffer descriptor
    - `gve_tx_tso_context_desc_dqo` - TSO context descriptor
    - `gve_tx_general_context_desc_dqo` - Generic metadata descriptor
    
    Metadata is a collection of 12 bytes. We define `gve_tx_metadata_dqo`
    which represents the logical interpetation of the metadata bytes. It's
    helpful to define this structure because the metadata bytes exist in
    multiple descriptor types (including `gve_tx_tso_context_desc_dqo`),
    and the device requires same field has the same value in all
    descriptors.
    
    The TX completion ring is used to receive completions from the NIC.
    Having a separate ring allows for completions to be out of order. The
    completion descriptor `gve_tx_compl_desc` has several different types,
    most important are packet and descriptor completions. Descriptor
    completions are used to notify the driver when descriptors sent on the
    TX ring are done being consumed. The descriptor completion is only used
    to signal that space is cleared in the TX ring. A packet completion will
    be received when a packet transmitted on the TX queue is done being
    transmitted.
    
    In addition there are "miss" and "reinjection" completions. The device
    implements a "flow-miss model". Most packets will simply receive a
    packet completion. The flow-miss system may choose to process a packet
    based on its contents. A TX packet which experiences a flow miss would
    receive a miss completion followed by a later reinjection completion.
    The miss-completion is received when the packet starts to be processed
    by the flow-miss system and the reinjection completion is received when
    the flow-miss system completes processing the packet and sends it on the
    wire.
    
    The RX buffer ring is used to send buffers to HW via the
    `gve_rx_desc_dqo` descriptor.
    
    Received packets are put into the RX queue by the device, which
    populates the `gve_rx_compl_desc_dqo` descriptor. The RX descriptors
    refer to buffers posted by the buffer queue. Received buffers may be
    returned out of order, such as when HW LRO is enabled.
    
    Important concepts:
    - "TX" and "RX buffer" queues, which send descriptors to the device, use
      MMIO doorbells to notify the device of new descriptors.
    
    - "RX" and "TX completion" queues, which receive descriptors from the
      device, use a "generation bit" to know when a descriptor was populated
      by the device. The driver initializes all bits with the "current
      generation". The device will populate received descriptors with the
      "next generation" which is inverted from the current generation. When
      the ring wraps, the current/next generation are swapped.
    
    - It's the driver's responsibility to ensure that the RX and TX
      completion queues are not overrun. This can be accomplished by
      limiting the number of descriptors posted to HW.
    
    - TX packets have a 16 bit completion_tag and RX buffers have a 16 bit
      buffer_id. These will be returned on the TX completion and RX queues
      respectively to let the driver know which packet/buffer was completed.
    
    Bitfields are used to describe descriptor fields. This notation is more
    concise and readable than shift-and-mask. It is possible because the
    driver is restricted to little endian platforms.
    Signed-off-by: default avatarBailey Forrest <bcf@google.com>
    Reviewed-by: default avatarWillem de Bruijn <willemb@google.com>
    Reviewed-by: default avatarCatherine Sullivan <csully@google.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    22319818
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