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Add the support of the revision 2 of FMC2 IP.
     - PCSCNTR register has been removed,
     - CFGR register has been added,
     - the bit used to enable the IP has moved from BCR1 to CFGR,
     - the timeout for CEx deassertion has moved from PCSCNTR to BCRx,
     - the continuous clock enable has moved from BCR1 to CFGR,
     - the clk divide ratio has moved from BCR1 to CFGR.

The MP1 SoCs have only one signal to manage all the controllers (NWAIT).
The MP25 SOC has one RNB signal for the NAND controller and one NWAIT
signal for the memory controller.

Let's use a platform data structure for parameters that will differ
between MP1 and MP25.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Link: https://lore.kernel.org/r/20240226101428.37791-4-christophe.kerello@foss.st.com

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>