• Gregory CLEMENT's avatar
    ARM: mvebu: use the virtual CPU registers to access coherency registers · b6dda00c
    Gregory CLEMENT authored
    The Armada XP provides a mechanism called "virtual CPU registers" or
    "per-CPU register banking", to access the per-CPU registers of the
    current CPU, without having to worry about finding on which CPU we're
    running. CPU0 has its registers at 0x21800, CPU1 at 0x21900, CPU2 at
    0x21A00 and CPU3 at 0x21B00. The virtual registers accessing the
    current CPU registers are at 0x21000.
    
    However, in the Device Tree node that provides the register addresses
    for the coherency unit (which is responsible for ensuring coherency
    between processors, and I/O coherency between processors and the
    DMA-capable devices), a mistake was made: the CPU0-specific registers
    were specified instead of the virtual CPU registers. This means that
    the coherency barrier needed for I/O coherency was not behaving
    properly when executed from a CPU different from CPU0. This patch
    fixes that by using the virtual CPU registers.
    Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
    Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
    Cc: <stable@vger.kernel.org> # v3.8+
    Fixes: e60304f8 "arm: mvebu: Add hardware I/O Coherency support"
    Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
    b6dda00c
armada-370-xp.dtsi 5.96 KB